From aa70d8a54a262179a53310cf9ad8273c78fd5c6f Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Tue, 2 May 2023 17:22:13 +0200
Subject: [PATCH] fixes CLIC to match clicinfo description in CLIC spec
 11.04.2023

---
 src/iss/arch/riscv_hart_m_p.h  | 6 ------
 src/iss/arch/riscv_hart_mu_p.h | 6 ------
 2 files changed, 12 deletions(-)

diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index bf1e32a..1462848 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -356,7 +356,6 @@ protected:
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
     std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
     uint8_t clic_cfg_reg{0};
-    uint32_t clic_info_reg{0};
     std::array<uint32_t, 32> clic_inttrig_reg;
     union clic_int_reg_t {
         struct{
@@ -521,7 +520,6 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
         csr_wr_cb[mintthresh] = &this_class::write_intthresh;
         clic_int_reg.resize(cfg.clic_num_irq,  clic_int_reg_t{.raw=0});
         clic_cfg_reg=0x20;
-        clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
         clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
         csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
         insert_mem_range(cfg.clic_base, 0x5000UL,
@@ -1178,8 +1176,6 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length
     if(addr==cfg.clic_base) { // cliccfg
         *data=clic_cfg_reg;
         for(auto i=1; i<length; ++i) *(data+i)=0;
-    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+8)){ // clicinfo
-        read_reg_uint32(addr, clic_info_reg, data, length);
     } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
         auto offset = ((addr&0x7fff)-0x40)/4;
         read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
@@ -1196,8 +1192,6 @@ template<typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
     if(addr==cfg.clic_base) { // cliccfg
         clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e);
-//    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
-//        write_uint32(addr, clic_info_reg, data, length);
     } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
         auto offset = ((addr&0x7fff)-0x40)/4;
         write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 94f7e08..f8ab194 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -380,7 +380,6 @@ protected:
     std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
     std::unordered_map<unsigned, wr_csr_f> csr_wr_cb;
     uint8_t clic_cfg_reg{0};
-    uint32_t clic_info_reg{0};
     std::array<uint32_t, 32> clic_inttrig_reg;
     union clic_int_reg_t {
         struct{
@@ -589,7 +588,6 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
         }
         clic_int_reg.resize(cfg.clic_num_irq,  clic_int_reg_t{.raw=0});
         clic_cfg_reg=0x30;
-        clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
         clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
         clic_uact_lvl = clic_uprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1;
         csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1;
@@ -1387,8 +1385,6 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned lengt
     if(addr==cfg.clic_base) { // cliccfg
         *data=clic_cfg_reg;
         for(auto i=1; i<length; ++i) *(data+i)=0;
-    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+8)){ // clicinfo
-        read_reg_uint32(addr, clic_info_reg, data, length);
     } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
         auto offset = ((addr&0x7fff)-0x40)/4;
         read_reg_uint32(addr, clic_inttrig_reg[offset], data, length);
@@ -1405,8 +1401,6 @@ template<typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
     if(addr==cfg.clic_base) { // cliccfg
         clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e);
-//    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
-//        write_uint32(addr, clic_info_reg, data, length);
     } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
         auto offset = ((addr&0x7fff)-0x40)/4;
         write_reg_uint32(addr, clic_inttrig_reg[offset], data, length);