From a943dd3bdfef992dea9ff3d7a559389c89bd1a32 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Wed, 15 Mar 2023 14:16:08 +0100
Subject: [PATCH] fixes wrong array size which led to unintended CSR
 definitions

---
 src/iss/arch/riscv_hart_m_p.h  | 2 +-
 src/iss/arch/riscv_hart_mu_p.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index 86d5877..36aec51 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -375,7 +375,7 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
         //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // common regs
-    const std::array<unsigned, 9> addrs{{
+    const std::array<unsigned, 8> addrs{{
     	misa, mvendorid, marchid, mimpid,
     	mepc, mtvec, mscratch, mtval
     }};
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 1c377eb..ac2e6b7 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -393,7 +393,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
         //csr_wr_cb[addr] = &this_class::write_csr_reg;
     }
     // common regs
-    const std::array<unsigned, 14> addrs{{
+    const std::array<unsigned, 12> addrs{{
         misa, mvendorid, marchid, mimpid,
         mepc, mtvec, mscratch, mtval,
         uepc, utvec, uscratch, utval,