From fbcd389580cb7257aeebc61e249a830fd0d3920a Mon Sep 17 00:00:00 2001 From: stas Date: Mon, 15 Apr 2024 13:03:47 +0200 Subject: [PATCH 1/2] fix log macro --- src/iss/arch/riscv_hart_common.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h index 037b801..829fbb1 100644 --- a/src/iss/arch/riscv_hart_common.h +++ b/src/iss/arch/riscv_hart_common.h @@ -35,13 +35,14 @@ #ifndef _RISCV_HART_COMMON #define _RISCV_HART_COMMON -#include "iss/arch_if.h" -#include "iss/log_categories.h" #include #include #include +#include +#include #include #include +#include namespace iss { namespace arch { @@ -344,7 +345,7 @@ struct riscv_hart_common { if(name != "") { this->symbol_table[name] = value; #ifndef NDEBUG - LOG(DEBUG) << "Found Symbol " << name; + CPPLOG(DEBUG) << "Found Symbol " << name; #endif } } From 6cb76fc256e6e3f54faf36b7f0c66c5259f6bc05 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 16 Apr 2024 13:09:14 +0200 Subject: [PATCH 2/2] updates tgc5c according to latest CoreDSL --- contrib/instr/TGC5C_instr.yaml | 2 +- src/vm/interp/vm_tgc5c.cpp | 114 ++++++++++++++++----------------- 2 files changed, 58 insertions(+), 58 deletions(-) diff --git a/contrib/instr/TGC5C_instr.yaml b/contrib/instr/TGC5C_instr.yaml index c1692e0..1663d37 100644 --- a/contrib/instr/TGC5C_instr.yaml +++ b/contrib/instr/TGC5C_instr.yaml @@ -349,7 +349,7 @@ Zifencei: size: 32 branch: false delay: 1 -RV32M: +RVM: MUL: index: 49 encoding: 0b00000010000000000000000000110011 diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index 10b6296..e98f30c 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -429,7 +429,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*PC + (int32_t)imm); + *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)imm )); } } } @@ -459,9 +459,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*PC + 4); + *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 4 )); } - *NEXT_PC = (uint32_t)(*PC + (int32_t)sext<21>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)sext<21>(imm) )); this->core.reg.last_branch = 1; } } @@ -489,13 +489,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t addr_mask = (uint32_t)- 2; - uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & addr_mask); + uint32_t new_pc = (uint32_t)(((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )) & (int64_t)(addr_mask )); if(new_pc % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*PC + 4); + *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 4 )); } *NEXT_PC = new_pc; this->core.reg.last_branch = 1; @@ -525,11 +525,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs1) == *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { + if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); this->core.reg.last_branch = 1; } } @@ -558,11 +558,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs1) != *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { + if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); this->core.reg.last_branch = 1; } } @@ -591,11 +591,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { + if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); this->core.reg.last_branch = 1; } } @@ -624,11 +624,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { + if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); this->core.reg.last_branch = 1; } } @@ -657,11 +657,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs1) < *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { + if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); this->core.reg.last_branch = 1; } } @@ -690,11 +690,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs1) >= *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { + if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); this->core.reg.last_branch = 1; } } @@ -722,7 +722,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); int8_t res_27 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); int8_t res = (int8_t)res_27; @@ -753,7 +753,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); int16_t res_28 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); int16_t res = (int16_t)res_28; @@ -784,7 +784,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); int32_t res_29 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); int32_t res = (int32_t)res_29; @@ -815,7 +815,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); uint8_t res_30 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint8_t res = res_30; @@ -846,7 +846,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); uint16_t res_31 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint16_t res = res_31; @@ -877,7 +877,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); super::template write_mem(traits::MEM, store_address, (uint8_t)*(X+rs2)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } @@ -904,7 +904,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); super::template write_mem(traits::MEM, store_address, (uint16_t)*(X+rs2)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } @@ -931,7 +931,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); super::template write_mem(traits::MEM, store_address, (uint32_t)*(X+rs2)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } @@ -959,7 +959,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); } } } @@ -1202,7 +1202,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) + *(X+rs2)); + *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)(*(X+rs2) )); } } } @@ -1229,7 +1229,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) - *(X+rs2)); + *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) - (uint64_t)(*(X+rs2) )); } } } @@ -1256,7 +1256,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1)); + *(X+rd) = *(X+rs1) << ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 ))); } } } @@ -1364,7 +1364,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); + *(X+rd) = *(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 ))); } } } @@ -1391,7 +1391,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1))); + *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 )))); } } } @@ -1772,7 +1772,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2)); + int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) ); if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -1800,7 +1800,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2)); + int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) ); if(rd != 0) { *(X+rd) = (uint32_t)(res >> traits::XLEN); } @@ -1828,7 +1828,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2)); + int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)(*(X+rs2) ); if(rd != 0) { *(X+rd) = (uint32_t)(res >> traits::XLEN); } @@ -1856,7 +1856,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint64_t res = (uint64_t)((uint64_t)*(X+rs1) * (uint64_t)*(X+rs2)); + uint64_t res = (uint64_t)(*(X+rs1) ) * (uint64_t)(*(X+rs2) ); if(rd != 0) { *(X+rd) = (uint32_t)(res >> traits::XLEN); } @@ -1888,7 +1888,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co int32_t divisor = (int32_t)*(X+rs2); if(rd != 0) { if(divisor != 0) { - uint32_t MMIN = ((uint32_t)1) << (traits::XLEN - 1); + uint32_t MMIN = ((uint32_t)1) << ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )); if(*(X+rs1) == MMIN && divisor == - 1) { *(X+rd) = MMIN; } @@ -1926,7 +1926,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { if(*(X+rs2) != 0) { if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) / *(X+rs2)); + *(X+rd) = *(X+rs1) / *(X+rs2); } } else { @@ -1959,7 +1959,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs2) != 0) { - uint32_t MMIN = (uint32_t)1 << (traits::XLEN - 1); + uint32_t MMIN = (uint32_t)1 << ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )); if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) { if(rd != 0) { *(X+rd) = 0; @@ -1967,7 +1967,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)((int32_t)*(X+rs1) % (int32_t)*(X+rs2)); + *(X+rd) = ((uint32_t)((int32_t)*(X+rs1) % (int32_t)*(X+rs2))); } } } @@ -2030,7 +2030,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(imm) { - *(X+rd + 8) = (uint32_t)(*(X+2) + imm); + *(X+rd + 8) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(imm )); } else { raise(0, 2); @@ -2054,7 +2054,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - uint32_t offs = (uint32_t)(*(X+rs1 + 8) + uimm); + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm )); int32_t res_38 = super::template read_mem(traits::MEM, offs); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); *(X+rd + 8) = (uint32_t)(int32_t)res_38; @@ -2077,7 +2077,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - uint32_t offs = (uint32_t)(*(X+rs1 + 8) + uimm); + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm )); super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2 + 8)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } @@ -2103,7 +2103,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rs1 != 0) { - *(X+rs1) = (uint32_t)(*(X+rs1) + (int8_t)sext<6>(imm)); + *(X+rs1) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int8_t)sext<6>(imm) )); } } } @@ -2136,8 +2136,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+1) = (uint32_t)(*PC + 2); - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm)); + *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 2 )); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<12>(imm) )); this->core.reg.last_branch = 1; } break; @@ -2207,7 +2207,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(nzimm) { - *(X+2) = (uint32_t)(*(X+2) + (int16_t)sext<10>(nzimm)); + *(X+2) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)((int16_t)sext<10>(nzimm) )); } else { raise(0, 2); @@ -2289,7 +2289,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (int8_t)sext<6>(imm)); + *(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (uint32_t)((int8_t)sext<6>(imm) )); } break; }// @suppress("No break at end of case") @@ -2308,7 +2308,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+rd + 8) = (uint32_t)(*(X+rd + 8) - *(X+rs2 + 8)); + *(X+rd + 8) = (uint32_t)((uint64_t)(*(X+rd + 8) ) - (uint64_t)(*(X+rs2 + 8) )); } break; }// @suppress("No break at end of case") @@ -2382,7 +2382,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<12>(imm) )); this->core.reg.last_branch = 1; } break; @@ -2403,7 +2403,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(*(X+rs1 + 8) == 0) { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<9>(imm) )); this->core.reg.last_branch = 1; } } @@ -2425,7 +2425,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(*(X+rs1 + 8) != 0) { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<9>(imm) )); this->core.reg.last_branch = 1; } } @@ -2476,7 +2476,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t offs = (uint32_t)(*(X+2) + uimm); + uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm )); int32_t res_39 = super::template read_mem(traits::MEM, offs); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); *(X+rd) = (uint32_t)(int32_t)res_39; @@ -2525,7 +2525,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs1 && rs1 < traits::RFS) { - *NEXT_PC = *(X+rs1 % traits::RFS) & ~ 0x1; + *NEXT_PC = *(X+(uint32_t)(rs1 ) % traits::RFS) & (uint32_t)(~ 0x1 ); this->core.reg.last_branch = 1; } else { @@ -2567,7 +2567,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rd) + *(X+rs2)); + *(X+rd) = (uint32_t)((uint64_t)(*(X+rd) ) + (uint64_t)(*(X+rs2) )); } } } @@ -2592,8 +2592,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t new_pc = *(X+rs1); - *(X+1) = (uint32_t)(*PC + 2); - *NEXT_PC = new_pc & ~ 0x1; + *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 2 )); + *NEXT_PC = new_pc & (uint32_t)(~ 0x1 ); this->core.reg.last_branch = 1; } } @@ -2631,7 +2631,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t offs = (uint32_t)(*(X+2) + uimm); + uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm )); super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); }