From 9dfca612b7491ee18695714c26b0df02abdd3981 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Fri, 25 Mar 2022 11:33:44 +0100 Subject: [PATCH] add hardware loop CSR access --- incl/iss/arch/hwl.h | 100 ++++++++++++++++++++++++++++++ incl/iss/arch/riscv_hart_m_p.h | 10 +++ incl/iss/arch/riscv_hart_msu_vp.h | 10 +++ incl/iss/arch/riscv_hart_mu_p.h | 10 +++ 4 files changed, 130 insertions(+) create mode 100644 incl/iss/arch/hwl.h diff --git a/incl/iss/arch/hwl.h b/incl/iss/arch/hwl.h new file mode 100644 index 0000000..9e954ba --- /dev/null +++ b/incl/iss/arch/hwl.h @@ -0,0 +1,100 @@ +/******************************************************************************* + * Copyright (C) 2022 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Contributors: + * eyck@minres.com - initial implementation + ******************************************************************************/ + +#ifndef _RISCV_HART_M_P_HWL_H +#define _RISCV_HART_M_P_HWL_H + +#include + +namespace iss { +namespace arch { + +template class hwl : public BASE { +public: + using base_class = BASE; + using this_class = hwl; + using reg_t = typename BASE::reg_t; + + hwl(); + virtual ~hwl() = default; + +protected: + iss::status read_custom_csr_reg(unsigned addr, reg_t &val) override; + iss::status write_custom_csr_reg(unsigned addr, reg_t val) override; +}; + + +template +inline hwl::hwl() { + for (unsigned addr = 0x800; addr < 0x803; ++addr){ + this->register_custom_csr_rd(addr); + this->register_custom_csr_wr(addr); + } + for (unsigned addr = 0x804; addr < 0x807; ++addr){ + this->register_custom_csr_rd(addr); + this->register_custom_csr_wr(addr); + } +} + +template +inline iss::status iss::arch::hwl::read_custom_csr_reg(unsigned addr, reg_t &val) { + switch(addr){ + case 0x800: val = this->reg.lpstart0; break; + case 0x801: val = this->reg.lpend0; break; + case 0x802: val = this->reg.lpcount0; break; + case 0x804: val = this->reg.lpstart1; break; + case 0x805: val = this->reg.lpend1; break; + case 0x806: val = this->reg.lpcount1; break; + } + return iss::Ok; +} + +template +inline iss::status iss::arch::hwl::write_custom_csr_reg(unsigned addr, reg_t val) { + switch(addr){ + case 0x800: this->reg.lpstart0 = val; break; + case 0x801: this->reg.lpend0 = val; break; + case 0x802: this->reg.lpcount0 = val; break; + case 0x804: this->reg.lpstart1 = val; break; + case 0x805: this->reg.lpend1 = val; break; + case 0x806: this->reg.lpcount1 = val; break; + } + return iss::Ok; +} + +} // namespace arch +} // namespace iss + + +#endif /* _RISCV_HART_M_P_H */ diff --git a/incl/iss/arch/riscv_hart_m_p.h b/incl/iss/arch/riscv_hart_m_p.h index 91dd7b4..b55625c 100644 --- a/incl/iss/arch/riscv_hart_m_p.h +++ b/incl/iss/arch/riscv_hart_m_p.h @@ -321,6 +321,16 @@ protected: iss::status read_dpc_reg(unsigned addr, reg_t &val); iss::status write_dpc_reg(unsigned addr, reg_t val); + virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;}; + virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;}; + + void register_custom_csr_rd(unsigned addr){ + csr_rd_cb[addr] = &this_class::read_custom_csr_reg; + } + void register_custom_csr_wr(unsigned addr){ + csr_wr_cb[addr] = &this_class::write_custom_csr_reg; + } + reg_t mhartid_reg{0x0}; std::functionmem_read_cb; std::function mem_write_cb; diff --git a/incl/iss/arch/riscv_hart_msu_vp.h b/incl/iss/arch/riscv_hart_msu_vp.h index 4ba669e..853a4bf 100644 --- a/incl/iss/arch/riscv_hart_msu_vp.h +++ b/incl/iss/arch/riscv_hart_msu_vp.h @@ -408,6 +408,16 @@ private: iss::status read_fcsr(unsigned addr, reg_t &val); iss::status write_fcsr(unsigned addr, reg_t val); + virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;}; + virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;}; + + void register_custom_csr_rd(unsigned addr){ + csr_rd_cb[addr] = &this_class::read_custom_csr_reg; + } + void register_custom_csr_wr(unsigned addr){ + csr_wr_cb[addr] = &this_class::write_custom_csr_reg; + } + reg_t mhartid_reg{0x0}; std::functionmem_read_cb; std::function mem_write_cb; diff --git a/incl/iss/arch/riscv_hart_mu_p.h b/incl/iss/arch/riscv_hart_mu_p.h index ab0444c..aafd204 100644 --- a/incl/iss/arch/riscv_hart_mu_p.h +++ b/incl/iss/arch/riscv_hart_mu_p.h @@ -339,6 +339,16 @@ protected: iss::status write_dpc_reg(unsigned addr, reg_t val); iss::status write_pmpcfg_reg(unsigned addr, reg_t val); + virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;}; + virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;}; + + void register_custom_csr_rd(unsigned addr){ + csr_rd_cb[addr] = &this_class::read_custom_csr_reg; + } + void register_custom_csr_wr(unsigned addr){ + csr_wr_cb[addr] = &this_class::write_custom_csr_reg; + } + reg_t mhartid_reg{0x0}; std::functionmem_read_cb; std::function mem_write_cb;