From 9970303fa493e20a707eb603a43987c94c4ff864 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sun, 22 Oct 2017 19:29:37 +0200 Subject: [PATCH] Changed handling of disassembler output so that tarcing becomes possible --- dbt-core | 2 +- riscv.sc/incl/sysc/SiFive/core_complex.h | 19 +- riscv.sc/src/sysc/core_complex.cpp | 89 +- riscv/incl/iss/arch/riscv_hart_msu_vp.h | 4 +- riscv/incl/iss/arch/rv32imac.h | 89 +- riscv/incl/iss/arch/rv64ia.h | 88 +- riscv/src/internal/vm_rv32imac.cpp | 4373 ++++++++++++---------- riscv/src/internal/vm_rv64ia.cpp | 3384 +++++++++-------- 8 files changed, 4434 insertions(+), 3614 deletions(-) diff --git a/dbt-core b/dbt-core index 35d9bbf..55b281a 160000 --- a/dbt-core +++ b/dbt-core @@ -1 +1 @@ -Subproject commit 35d9bbfe6569f2412c2ff98cd3a554c4d750b3de +Subproject commit 55b281a010a7cedc7ba23c3856a551a9ee314eb4 diff --git a/riscv.sc/incl/sysc/SiFive/core_complex.h b/riscv.sc/incl/sysc/SiFive/core_complex.h index 6a15cca..3364a90 100644 --- a/riscv.sc/incl/sysc/SiFive/core_complex.h +++ b/riscv.sc/incl/sysc/SiFive/core_complex.h @@ -46,6 +46,11 @@ #include "scc/initiator_mixin.h" #include "scc/traceable.h" +class scv_tr_db; +class scv_tr_stream; +struct _scv_tr_generator_default_data; +template < class T_begin, class T_end> class scv_tr_generator; + namespace iss { class vm_if; namespace arch { @@ -103,7 +108,7 @@ public: } } - bool read_mem(uint64_t addr, unsigned length, uint8_t *const data); + bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch); bool write_mem(uint64_t addr, unsigned length, const uint8_t *const data); @@ -113,6 +118,7 @@ public: void trace(sc_core::sc_trace_file *trf) override; + void disass_output(uint64_t pc, const std::string instr); protected: void before_end_of_elaboration(); void start_of_simulation(); @@ -125,6 +131,17 @@ protected: std::unique_ptr vm; sc_core::sc_time curr_clk; iss::debugger::target_adapter_if* tgt_adapter; +#ifdef WITH_SCV + //! transaction recording database + scv_tr_db *m_db; + //! blocking transaction recording stream handle + scv_tr_stream *stream_handle; + //! transaction generator handle for blocking transactions + scv_tr_generator<_scv_tr_generator_default_data,_scv_tr_generator_default_data> *instr_tr_handle; + scv_tr_generator *fetch_tr_handle; + scv_tr_handle tr_handle; +#endif + }; } /* namespace SiFive */ diff --git a/riscv.sc/src/sysc/core_complex.cpp b/riscv.sc/src/sysc/core_complex.cpp index 421af5a..f28448b 100644 --- a/riscv.sc/src/sysc/core_complex.cpp +++ b/riscv.sc/src/sysc/core_complex.cpp @@ -45,6 +45,9 @@ #include "iss/debugger/encoderdecoder.h" #include "sysc/SiFive/core_complex.h" +#ifdef WITH_SCV +#include +#endif namespace sysc { namespace SiFive { @@ -52,21 +55,64 @@ namespace { iss::debugger::encoder_decoder encdec; } +namespace { + +const char lvl[] = {'U', 'S', 'H', 'M'}; + +const char *trap_str[] = {"Instruction address misaligned", + "Instruction access fault", + "Illegal instruction", + "Breakpoint", + "Load address misaligned", + "Load access fault", + "Store/AMO address misaligned", + "Store/AMO access fault", + "Environment call from U-mode", + "Environment call from S-mode", + "Reserved", + "Environment call from M-mode", + "Instruction page fault", + "Load page fault", + "Reserved", + "Store/AMO page fault"}; +const char *irq_str[] = { + "User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt", + "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt", + "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}; +} + class core_wrapper : public iss::arch::riscv_hart_msu_vp { public: using core_type = iss::arch::rv32imac; using base_type = iss::arch::riscv_hart_msu_vp; using phys_addr_t = typename iss::arch::traits::phys_addr_t; core_wrapper(core_complex *owner) - : owner(owner) {} + : owner(owner) + {} + + uint32_t get_mode(){ return this->reg.machine_state; } + + base_type::hart_state& get_state() { return this->state; } void notify_phase(iss::arch_if::exec_phase phase); + void disass_output(uint64_t pc, const std::string instr) override { +#ifndef WITH_SCV + std::stringstream s; + s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0') + << std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]"; + CLOG(INFO, disass) << "0x"<disass_output(pc,instr); +#endif + }; + iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) { if (addr.type & iss::DEBUG) return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err; - else - return owner->read_mem(addr.val, length, data) ? iss::Ok : iss::Err; + else { + return owner->read_mem(addr.val, length, data,addr.type && iss::FETCH) ? iss::Ok : iss::Err; + } } iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) { @@ -127,7 +173,14 @@ core_complex::core_complex(sc_core::sc_module_name name) , NAMED(dump_ir, false, this) , read_lut(tlm_dmi_ext()) , write_lut(tlm_dmi_ext()) -, tgt_adapter(nullptr){ +, tgt_adapter(nullptr) +#ifdef WITH_SCV +, m_db(scv_tr_db::get_default_db()) +, stream_handle(nullptr) +, instr_tr_handle(nullptr) +, fetch_tr_handle(nullptr) +#endif +{ initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void { auto lut_entry = read_lut.getEntry(start); @@ -167,6 +220,25 @@ void core_complex::before_end_of_elaboration() { void core_complex::start_of_simulation() { quantum_keeper.reset(); if (elf_file.value.size() > 0) cpu->load_file(elf_file.value); +#ifdef WITH_SCV + if (stream_handle == NULL) { + string basename(this->name()); + stream_handle = new scv_tr_stream((basename + ".instr").c_str(), "TRANSACTOR", m_db); + instr_tr_handle = new scv_tr_generator<>("execute", *stream_handle); + fetch_tr_handle = new scv_tr_generator("fetch", *stream_handle); + } +#endif +} + +void core_complex::disass_output(uint64_t pc, const std::string instr_str) { +#ifdef WITH_SCV + if(tr_handle.is_active()) tr_handle.end_transaction(); + tr_handle = instr_tr_handle->begin_transaction(); + tr_handle.record_attribute("PC", pc); + tr_handle.record_attribute("INSTR", instr_str); + tr_handle.record_attribute("MODE", lvl[cpu->get_mode()]); + tr_handle.record_attribute("MSTATUS", cpu->get_state().mstatus.st.value); +#endif } void core_complex::clk_cb() { curr_clk = clk_i.read(); } @@ -181,7 +253,7 @@ void core_complex::run() { sc_core::sc_stop(); } -bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data) { +bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch) { auto lut_entry = read_lut.getEntry(addr); if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) { @@ -197,6 +269,13 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data) gp.set_data_length(length); gp.set_streaming_width(4); auto delay{quantum_keeper.get_local_time()}; +#ifdef WITH_SCV + if(tr_handle.is_valid()){ + if(is_fetch && tr_handle.is_active()) tr_handle.end_transaction(); + auto preExt = new scv4tlm::tlm_recording_extension(tr_handle, this); + gp.set_extension(preExt); + } +#endif initiator->b_transport(gp, delay); LOG(TRACE) << "read_mem(0x" << std::hex << addr << ") : " << data; if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) { diff --git a/riscv/incl/iss/arch/riscv_hart_msu_vp.h b/riscv/incl/iss/arch/riscv_hart_msu_vp.h index e567895..1f6ae7d 100644 --- a/riscv/incl/iss/arch/riscv_hart_msu_vp.h +++ b/riscv/incl/iss/arch/riscv_hart_msu_vp.h @@ -435,11 +435,11 @@ public: virtual uint64_t leave_trap(uint64_t flags) override; void wait_until(uint64_t flags) override; - virtual std::string get_additional_disass_info() { + void disass_output(uint64_t pc, const std::string instr) override { std::stringstream s; s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]"; - return s.str(); + CLOG(INFO, disass) << "0x"< // //////////////////////////////////////////////////////////////////////////////// @@ -36,30 +36,19 @@ #ifndef _RV32IMAC_H_ #define _RV32IMAC_H_ -#include #include #include +#include namespace iss { namespace arch { -class rv32imac; +struct rv32imac; -template <> class traits { -public: - enum constants { - XLEN = 32, - XLEN2 = 64, - XLEN_BIT_MASK = 31, - PCLEN = 32, - fence = 0, - fencei = 1, - fencevmal = 2, - fencevmau = 3, - MISA_VAL = 1075056897, - PGSIZE = 4096, - PGMASK = 4095 - }; +template<> +struct traits { + + enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095}; enum reg_e { X0, @@ -96,7 +85,7 @@ public: X31, PC, NUM_REGS, - NEXT_PC = NUM_REGS, + NEXT_PC=NUM_REGS, TRAP_STATE, PENDING_TRAP, MACHINE_STATE, @@ -107,64 +96,61 @@ public: using addr_t = uint32_t; - using code_word_t = uint32_t; // TODO: check removal + using code_word_t = uint32_t; //TODO: check removal using virt_addr_t = iss::typed_addr_t; using phys_addr_t = iss::typed_addr_t; constexpr static unsigned reg_bit_width(unsigned r) { - const uint32_t RV32IMAC_reg_size[] = {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 64}; + const uint32_t RV32IMAC_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}; return RV32IMAC_reg_size[r]; } constexpr static unsigned reg_byte_offset(unsigned r) { - const uint32_t RV32IMAC_reg_byte_offset[] = {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, - 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, - 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 152, 160}; + const uint32_t RV32IMAC_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160}; return RV32IMAC_reg_byte_offset[r]; } - enum sreg_flag_e { FLAGS }; + enum sreg_flag_e {FLAGS}; + + enum mem_type_e {MEM,CSR,FENCE,RES}; - enum mem_type_e { MEM, CSR, FENCE, RES }; }; -class rv32imac : public arch_if { -public: +struct rv32imac: public arch_if { + using virt_addr_t = typename traits::virt_addr_t; using phys_addr_t = typename traits::phys_addr_t; - using reg_t = typename traits::reg_t; + using reg_t = typename traits::reg_t; using addr_t = typename traits::addr_t; rv32imac(); ~rv32imac() = default; - void reset(uint64_t address = 0) override; + void reset(uint64_t address=0) override; - uint8_t *get_regs_base_ptr() override; + uint8_t* get_regs_base_ptr() override; /// deprecated - void get_reg(short idx, std::vector &value) override {} - void set_reg(short idx, const std::vector &value) override {} + void get_reg(short idx, std::vector& value) override {} + void set_reg(short idx, const std::vector& value) override {} /// deprecated - bool get_flag(int flag) override { return false; } - void set_flag(int, bool value) override{}; + bool get_flag(int flag) override {return false;} + void set_flag(int, bool value) override {}; /// deprecated - void update_flags(operations op, uint64_t opr1, uint64_t opr2) override{}; + void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {}; - void notify_phase(exec_phase phase) override { - if (phase == ISTART) { + void notify_phase(exec_phase phase){ + if(phase==ISTART){ ++reg.icount; - reg.PC = reg.NEXT_PC; - reg.trap_state = reg.pending_trap; + reg.PC=reg.NEXT_PC; + reg.trap_state=reg.pending_trap; } } - uint64_t get_icount() { return reg.icount; } + uint64_t get_icount() { return reg.icount;} - virtual phys_addr_t v2p(const iss::addr_t &pc); + virtual phys_addr_t v2p(const iss::addr_t& pc); virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; } @@ -208,6 +194,7 @@ protected: uint64_t icount; } reg; }; + } -} +} #endif /* _RV32IMAC_H_ */ diff --git a/riscv/incl/iss/arch/rv64ia.h b/riscv/incl/iss/arch/rv64ia.h index 6a32c8d..18f4ced 100644 --- a/riscv/incl/iss/arch/rv64ia.h +++ b/riscv/incl/iss/arch/rv64ia.h @@ -1,21 +1,21 @@ //////////////////////////////////////////////////////////////////////////////// // Copyright (C) 2017, MINRES Technologies GmbH // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: -// +// // 1. Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. -// +// // 2. Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution. -// +// // 3. Neither the name of the copyright holder nor the names of its contributors // may be used to endorse or promote products derived from this software // without specific prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -27,8 +27,8 @@ // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. -// -// Created on: Tue Sep 26 17:41:14 CEST 2017 +// +// Created on: Wed Oct 18 11:42:36 CEST 2017 // * rv64ia.h Author: // //////////////////////////////////////////////////////////////////////////////// @@ -36,30 +36,19 @@ #ifndef _RV64IA_H_ #define _RV64IA_H_ -#include #include #include +#include namespace iss { namespace arch { -class rv64ia; +struct rv64ia; -template <> class traits { -public: - enum constants { - XLEN = 64, - XLEN2 = 128, - XLEN_BIT_MASK = 63, - PCLEN = 64, - fence = 0, - fencei = 1, - fencevmal = 2, - fencevmau = 3, - MISA_VAL = 2147750144, - PGSIZE = 4096, - PGMASK = 4095 - }; +template<> +struct traits { + + enum constants {XLEN=64,XLEN2=128,XLEN_BIT_MASK=63,PCLEN=64,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=2147750144,PGSIZE=4096,PGMASK=4095}; enum reg_e { X0, @@ -96,7 +85,7 @@ public: X31, PC, NUM_REGS, - NEXT_PC = NUM_REGS, + NEXT_PC=NUM_REGS, TRAP_STATE, PENDING_TRAP, MACHINE_STATE, @@ -107,63 +96,61 @@ public: using addr_t = uint64_t; - using code_word_t = uint64_t; // TODO: check removal + using code_word_t = uint64_t; //TODO: check removal using virt_addr_t = iss::typed_addr_t; using phys_addr_t = iss::typed_addr_t; constexpr static unsigned reg_bit_width(unsigned r) { - const uint32_t RV64IA_reg_size[] = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, - 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 32, 32, 32, 64}; + const uint32_t RV64IA_reg_size[] = {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64}; return RV64IA_reg_size[r]; } constexpr static unsigned reg_byte_offset(unsigned r) { - const uint32_t RV64IA_reg_byte_offset[] = {0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, - 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 200, - 208, 216, 224, 232, 240, 248, 256, 264, 272, 276, 280, 288, 296}; + const uint32_t RV64IA_reg_byte_offset[] = {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296}; return RV64IA_reg_byte_offset[r]; } - enum sreg_flag_e { FLAGS }; + enum sreg_flag_e {FLAGS}; + + enum mem_type_e {MEM,CSR,FENCE,RES}; - enum mem_type_e { MEM, CSR, FENCE, RES }; }; -class rv64ia : public arch_if { -public: +struct rv64ia: public arch_if { + using virt_addr_t = typename traits::virt_addr_t; using phys_addr_t = typename traits::phys_addr_t; - using reg_t = typename traits::reg_t; + using reg_t = typename traits::reg_t; using addr_t = typename traits::addr_t; rv64ia(); ~rv64ia(); - void reset(uint64_t address = 0) override; + void reset(uint64_t address=0) override; - uint8_t *get_regs_base_ptr() override; + uint8_t* get_regs_base_ptr() override; /// deprecated - void get_reg(short idx, std::vector &value) override {} - void set_reg(short idx, const std::vector &value) override {} + void get_reg(short idx, std::vector& value) override {} + void set_reg(short idx, const std::vector& value) override {} /// deprecated - bool get_flag(int flag) override { return false; } - void set_flag(int, bool value) override{}; + bool get_flag(int flag) override {return false;} + void set_flag(int, bool value) override {}; /// deprecated - void update_flags(operations op, uint64_t opr1, uint64_t opr2) override{}; + void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {}; - void notify_phase(exec_phase phase) { - if (phase == ISTART) { + void notify_phase(exec_phase phase){ + if(phase==ISTART){ ++reg.icount; - reg.PC = reg.NEXT_PC; - reg.trap_state = reg.pending_trap; + reg.PC=reg.NEXT_PC; + reg.trap_state=reg.pending_trap; } } - uint64_t get_icount() { return reg.icount; } + uint64_t get_icount() { return reg.icount;} - virtual phys_addr_t v2p(const iss::addr_t &pc); + virtual phys_addr_t v2p(const iss::addr_t& pc); virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; } @@ -207,6 +194,7 @@ protected: uint64_t icount; } reg; }; + } -} +} #endif /* _RV64IA_H_ */ diff --git a/riscv/src/internal/vm_rv32imac.cpp b/riscv/src/internal/vm_rv32imac.cpp index d4385ad..7549ccf 100644 --- a/riscv/src/internal/vm_rv32imac.cpp +++ b/riscv/src/internal/vm_rv32imac.cpp @@ -34,8 +34,8 @@ // //////////////////////////////////////////////////////////////////////////////// -#include #include +#include #include #include #include @@ -416,3479 +416,3883 @@ private: {16, 0b1100000000000010, 0b1110000000000011, &this_class::__c_swsp}, }; // instruction LUI - std::tuple __lui(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lui(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LUI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - int32_t fld_imm_val = 0 | (signed_bit_sub<12, 20>(instr) << 12); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + int32_t fld_imm_val = 0 | (signed_bit_sub<12,20>(instr) << 12); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LUI x%1$d, 0x%2$05x"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_const(32U, fld_imm_val); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_const(32U, fld_imm_val); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AUIPC - std::tuple __auipc(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __auipc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AUIPC"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - int32_t fld_imm_val = 0 | (signed_bit_sub<12, 20>(instr) << 12); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + int32_t fld_imm_val = 0 | (signed_bit_sub<12,20>(instr) << 12); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AUIPC x%1%, 0x%2$08x"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, fld_imm_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, fld_imm_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction JAL - std::tuple __jal(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __jal(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("JAL"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - int32_t fld_imm_val = 0 | (bit_sub<12, 8>(instr) << 12) | (bit_sub<20, 1>(instr) << 11) | - (bit_sub<21, 10>(instr) << 1) | (signed_bit_sub<31, 1>(instr) << 20); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + int32_t fld_imm_val = 0 | (bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (signed_bit_sub<31,1>(instr) << 20); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("JAL x%1$d, 0x%2$x"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, 4)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, 4)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *PC_val = - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, fld_imm_val)); + Value* PC_val = this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, fld_imm_val)); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction JALR - std::tuple __jalr(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __jalr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("JALR"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("JALR x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, 4)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, 4)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *ret_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); - Value *PC_val = this->builder->CreateAnd(ret_val, this->builder->CreateNot(this->gen_const(32U, 1))); + Value* ret_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); + Value* PC_val = this->builder->CreateAnd( + ret_val, + this->builder->CreateNot(this->gen_const(32U, 1))); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction BEQ - std::tuple __beq(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __beq(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("BEQ"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | - (bit_sub<25, 6>(instr) << 5) | (signed_bit_sub<31, 1>(instr) << 12); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("BEQ x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(fld_rs1_val, 0), - this->gen_reg_load(fld_rs2_val, 0)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, 4)), 32); + pc=pc+4; + + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_EQ, + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, 4)), + 32); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction BNE - std::tuple __bne(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __bne(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("BNE"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | - (bit_sub<25, 6>(instr) << 5) | (signed_bit_sub<31, 1>(instr) << 12); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("BNE x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(fld_rs1_val, 0), - this->gen_reg_load(fld_rs2_val, 0)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, 4)), 32); + pc=pc+4; + + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, 4)), + 32); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction BLT - std::tuple __blt(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __blt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("BLT"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | - (bit_sub<25, 6>(instr) << 5) | (signed_bit_sub<31, 1>(instr) << 12); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("BLT x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_SLT, this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 32, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 32, true)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, 4)), 32); + pc=pc+4; + + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_SLT, + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 32, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 32, true)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, 4)), + 32); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction BGE - std::tuple __bge(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __bge(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("BGE"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | - (bit_sub<25, 6>(instr) << 5) | (signed_bit_sub<31, 1>(instr) << 12); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("BGE x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_SGE, this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 32, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 32, true)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, 4)), 32); + pc=pc+4; + + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_SGE, + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 32, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 32, true)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, 4)), + 32); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction BLTU - std::tuple __bltu(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __bltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("BLTU"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | - (bit_sub<25, 6>(instr) << 5) | (signed_bit_sub<31, 1>(instr) << 12); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("BLTU x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(fld_rs1_val, 0), - this->gen_reg_load(fld_rs2_val, 0)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, 4)), 32); + pc=pc+4; + + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, 4)), + 32); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction BGEU - std::tuple __bgeu(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __bgeu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("BGEU"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | - (bit_sub<25, 6>(instr) << 5) | (signed_bit_sub<31, 1>(instr) << 12); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("BGEU x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_UGE, this->gen_reg_load(fld_rs1_val, 0), - this->gen_reg_load(fld_rs2_val, 0)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, 4)), 32); + pc=pc+4; + + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_UGE, + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, 4)), + 32); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction LB - std::tuple __lb(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LB"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LB x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 8 / 8), 32, true); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 8/8), + 32, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction LH - std::tuple __lh(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LH"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LH x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 16 / 8), 32, true); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 16/8), + 32, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction LW - std::tuple __lw(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LW x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 32, true); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 32, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction LBU - std::tuple __lbu(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lbu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LBU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LBU x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 8 / 8), 32, false); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 8/8), + 32, + false); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction LHU - std::tuple __lhu(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lhu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LHU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LHU x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 16 / 8), 32, false); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 16/8), + 32, + false); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SB - std::tuple __sb(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SB"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 5>(instr)) | (signed_bit_sub<25, 7>(instr) << 5); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SB x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); - Value *MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(8))); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); + Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(8))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SH - std::tuple __sh(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SH"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 5>(instr)) | (signed_bit_sub<25, 7>(instr) << 5); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SH x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); - Value *MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(16))); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); + Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(16))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SW - std::tuple __sw(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SW"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 5>(instr)) | (signed_bit_sub<25, 7>(instr) << 5); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SW x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); - Value *MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); + Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction ADDI - std::tuple __addi(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __addi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("ADDI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("ADDI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLTI - std::tuple __slti(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __slti(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLTI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLTI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_SLT, - this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 32, true), - this->gen_ext(this->gen_const(32U, fld_imm_val), 32, true)), - this->gen_const(32U, 1), this->gen_const(32U, 0), 32); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_SLT, + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 32, true), + this->gen_ext( + this->gen_const(32U, fld_imm_val), + 32, true)), + this->gen_const(32U, 1), + this->gen_const(32U, 0), + 32); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLTIU - std::tuple __sltiu(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sltiu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLTIU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLTIU x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + int32_t full_imm_val = fld_imm_val; - if (fld_rd_val != 0) { - Value *X_rd_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_ULT, - this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 32, false), - this->gen_ext(full_imm_val, 32, false)), - this->gen_const(32U, 1), this->gen_const(32U, 0), 32); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 32, false), + this->gen_ext( + full_imm_val, + 32, false)), + this->gen_const(32U, 1), + this->gen_const(32U, 0), + 32); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction XORI - std::tuple __xori(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __xori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("XORI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("XORI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateXor(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateXor( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction ORI - std::tuple __ori(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __ori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("ORI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("ORI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateOr(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateOr( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction ANDI - std::tuple __andi(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __andi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("ANDI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAnd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_imm_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAnd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_imm_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLLI - std::tuple __slli(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __slli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLLI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_shamt_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_shamt_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLLI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateShl(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_shamt_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateShl( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_shamt_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SRLI - std::tuple __srli(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __srli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRLI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_shamt_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_shamt_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SRLI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateLShr(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_shamt_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateLShr( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_shamt_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SRAI - std::tuple __srai(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __srai(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRAI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_shamt_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_shamt_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SRAI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAShr(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_shamt_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAShr( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_shamt_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction ADD - std::tuple __add(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __add(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("ADD"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("ADD x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_reg_load(fld_rs2_val, 0)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SUB - std::tuple __sub(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sub(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SUB"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SUB x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateSub(this->gen_reg_load(fld_rs1_val, 0), this->gen_reg_load(fld_rs2_val, 0)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateSub( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLL - std::tuple __sll(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sll(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLL"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLL x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = this->builder->CreateShl( - this->gen_reg_load(fld_rs1_val, 0), this->builder->CreateAnd(this->gen_reg_load(fld_rs2_val, 0), 31)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateShl( + this->gen_reg_load(fld_rs1_val, 0), + this->builder->CreateAnd( + this->gen_reg_load(fld_rs2_val, 0), + 31)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLT - std::tuple __slt(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __slt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLT"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLT x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_SLT, - this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 32, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 32, true)), - this->gen_const(32U, 1), this->gen_const(32U, 0), 32); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_SLT, + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 32, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 32, true)), + this->gen_const(32U, 1), + this->gen_const(32U, 0), + 32); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLTU - std::tuple __sltu(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLTU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLTU x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->gen_choose(this->builder->CreateICmp( - ICmpInst::ICMP_ULT, this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 32, false), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 32, false)), - this->gen_const(32U, 1), this->gen_const(32U, 0), 32); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 32, + false), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 32, + false)), + this->gen_const(32U, 1), + this->gen_const(32U, 0), + 32); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction XOR - std::tuple __xor(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __xor(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("XOR"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("XOR x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateXor(this->gen_reg_load(fld_rs1_val, 0), this->gen_reg_load(fld_rs2_val, 0)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateXor( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SRL - std::tuple __srl(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __srl(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRL"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SRL x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = this->builder->CreateLShr( - this->gen_reg_load(fld_rs1_val, 0), this->builder->CreateAnd(this->gen_reg_load(fld_rs2_val, 0), 31)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateLShr( + this->gen_reg_load(fld_rs1_val, 0), + this->builder->CreateAnd( + this->gen_reg_load(fld_rs2_val, 0), + 31)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SRA - std::tuple __sra(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sra(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRA"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SRA x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = this->builder->CreateAShr( - this->gen_reg_load(fld_rs1_val, 0), this->builder->CreateAnd(this->gen_reg_load(fld_rs2_val, 0), 31)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAShr( + this->gen_reg_load(fld_rs1_val, 0), + this->builder->CreateAnd( + this->gen_reg_load(fld_rs2_val, 0), + 31)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction OR - std::tuple __or(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __or(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("OR"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("OR x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateOr(this->gen_reg_load(fld_rs1_val, 0), this->gen_reg_load(fld_rs2_val, 0)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateOr( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AND - std::tuple __and(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __and(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AND"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AND x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAnd(this->gen_reg_load(fld_rs1_val, 0), this->gen_reg_load(fld_rs2_val, 0)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAnd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction FENCE - std::tuple __fence(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __fence(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("FENCE"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_succ_val = 0 | (bit_sub<20, 4>(instr)); - uint8_t fld_pred_val = 0 | (bit_sub<24, 4>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_succ_val = 0 | (bit_sub<20,4>(instr)); + uint8_t fld_pred_val = 0 | (bit_sub<24,4>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("FENCE"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("FENCE"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *FENCE_fence_val = this->builder->CreateOr( - this->builder->CreateShl(this->gen_const(32U, fld_pred_val), this->gen_const(32U, 4)), + pc=pc+4; + + Value* FENCE_fence_val = this->builder->CreateOr( + this->builder->CreateShl( + this->gen_const(32U, fld_pred_val), + this->gen_const(32U, 4)), this->gen_const(32U, fld_succ_val)); - this->gen_write_mem(traits::FENCE, (uint64_t)0, - this->builder->CreateZExtOrTrunc(FENCE_fence_val, this->get_type(32))); + this->gen_write_mem( + traits::FENCE, + (uint64_t)0, + this->builder->CreateZExtOrTrunc(FENCE_fence_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction FENCE_I - std::tuple __fence_i(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __fence_i(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("FENCE_I"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_imm_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("FENCE_I"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("FENCE_I"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *FENCE_fencei_val = this->gen_const(32U, fld_imm_val); - this->gen_write_mem(traits::FENCE, (uint64_t)1, - this->builder->CreateZExtOrTrunc(FENCE_fencei_val, this->get_type(32))); + pc=pc+4; + + Value* FENCE_fencei_val = this->gen_const(32U, fld_imm_val); + this->gen_write_mem( + traits::FENCE, + (uint64_t)1, + this->builder->CreateZExtOrTrunc(FENCE_fencei_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::FLUSH, nullptr); } - + // instruction ECALL - std::tuple __ecall(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __ecall(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("ECALL"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("ECALL"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("ECALL"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + this->gen_raise_trap(0, 11); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction EBREAK - std::tuple __ebreak(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __ebreak(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("EBREAK"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("EBREAK"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("EBREAK"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + this->gen_raise_trap(0, 3); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction URET - std::tuple __uret(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __uret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("URET"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("URET"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("URET"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + this->gen_leave_trap(0); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction SRET - std::tuple __sret(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRET"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("SRET"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("SRET"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + this->gen_leave_trap(1); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction MRET - std::tuple __mret(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __mret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("MRET"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("MRET"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("MRET"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + this->gen_leave_trap(3); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction WFI - std::tuple __wfi(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __wfi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("WFI"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("WFI"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("WFI"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + this->gen_wait(1); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SFENCE.VMA - std::tuple __sfence_vma(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sfence_vma(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SFENCE.VMA"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("SFENCE.VMA"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("SFENCE.VMA"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *FENCE_fencevmal_val = this->gen_const(32U, fld_rs1_val); - this->gen_write_mem(traits::FENCE, (uint64_t)2, - this->builder->CreateZExtOrTrunc(FENCE_fencevmal_val, this->get_type(32))); - Value *FENCE_fencevmau_val = this->gen_const(32U, fld_rs2_val); - this->gen_write_mem(traits::FENCE, (uint64_t)3, - this->builder->CreateZExtOrTrunc(FENCE_fencevmau_val, this->get_type(32))); + pc=pc+4; + + Value* FENCE_fencevmal_val = this->gen_const(32U, fld_rs1_val); + this->gen_write_mem( + traits::FENCE, + (uint64_t)2, + this->builder->CreateZExtOrTrunc(FENCE_fencevmal_val,this->get_type(32))); + Value* FENCE_fencevmau_val = this->gen_const(32U, fld_rs2_val); + this->gen_write_mem( + traits::FENCE, + (uint64_t)3, + this->builder->CreateZExtOrTrunc(FENCE_fencevmau_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction CSRRW - std::tuple __csrrw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __csrrw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("CSRRW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_csr_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("CSRRW x%1$d, %2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *rs_val_val = this->gen_reg_load(fld_rs1_val, 0); - if (fld_rd_val != 0) { - Value *csr_val_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32 / 8); - Value *CSR_csr_val = rs_val_val; - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(32))); - Value *X_rd_val = csr_val_val; + pc=pc+4; + + Value* rs_val_val = this->gen_reg_load(fld_rs1_val, 0); + if(fld_rd_val != 0){ + Value* csr_val_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + Value* CSR_csr_val = rs_val_val; + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + Value* X_rd_val = csr_val_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } else { - Value *CSR_csr_val = rs_val_val; - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(32))); + Value* CSR_csr_val = rs_val_val; + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction CSRRS - std::tuple __csrrs(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __csrrs(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("CSRRS"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_csr_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("CSRRS x%1$d, %2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32 / 8); - Value *xrs1_val = this->gen_reg_load(fld_rs1_val, 0); - if (fld_rd_val != 0) { - Value *X_rd_val = xrd_val; + pc=pc+4; + + Value* xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + Value* xrs1_val = this->gen_reg_load(fld_rs1_val, 0); + if(fld_rd_val != 0){ + Value* X_rd_val = xrd_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - if (fld_rs1_val != 0) { - Value *CSR_csr_val = this->builder->CreateOr(xrd_val, xrs1_val); - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(32))); + if(fld_rs1_val != 0){ + Value* CSR_csr_val = this->builder->CreateOr( + xrd_val, + xrs1_val); + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction CSRRC - std::tuple __csrrc(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __csrrc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("CSRRC"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_csr_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("CSRRC x%1$d, %2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32 / 8); - Value *xrs1_val = this->gen_reg_load(fld_rs1_val, 0); - if (fld_rd_val != 0) { - Value *X_rd_val = xrd_val; + pc=pc+4; + + Value* xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + Value* xrs1_val = this->gen_reg_load(fld_rs1_val, 0); + if(fld_rd_val != 0){ + Value* X_rd_val = xrd_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - if (fld_rs1_val != 0) { - Value *CSR_csr_val = this->builder->CreateAnd(xrd_val, this->builder->CreateNot(xrs1_val)); - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(32))); + if(fld_rs1_val != 0){ + Value* CSR_csr_val = this->builder->CreateAnd( + xrd_val, + this->builder->CreateNot(xrs1_val)); + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction CSRRWI - std::tuple __csrrwi(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __csrrwi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("CSRRWI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_zimm_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_csr_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("CSRRWI x%1$d, %2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32 / 8); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *CSR_csr_val = this->gen_ext(this->gen_const(32U, fld_zimm_val), 32, false); - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(32))); + Value* CSR_csr_val = this->gen_ext( + this->gen_const(32U, fld_zimm_val), + 32, + false); + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction CSRRSI - std::tuple __csrrsi(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __csrrsi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("CSRRSI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_zimm_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_csr_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("CSRRSI x%1$d, %2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32 / 8); - if (fld_zimm_val != 0) { - Value *CSR_csr_val = - this->builder->CreateOr(res_val, this->gen_ext(this->gen_const(32U, fld_zimm_val), 32, false)); - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(32))); + pc=pc+4; + + Value* res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + if(fld_zimm_val != 0){ + Value* CSR_csr_val = this->builder->CreateOr( + res_val, + this->gen_ext( + this->gen_const(32U, fld_zimm_val), + 32, + false)); + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); } - if (fld_rd_val != 0) { - Value *X_rd_val = res_val; + if(fld_rd_val != 0){ + Value* X_rd_val = res_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction CSRRCI - std::tuple __csrrci(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __csrrci(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("CSRRCI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_zimm_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_csr_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("CSRRCI x%1$d, %2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32 / 8); - if (fld_rd_val != 0) { - Value *X_rd_val = res_val; + pc=pc+4; + + Value* res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + if(fld_rd_val != 0){ + Value* X_rd_val = res_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - if (fld_zimm_val != 0) { - Value *CSR_csr_val = this->builder->CreateAnd( - res_val, this->builder->CreateNot(this->gen_ext(this->gen_const(32U, fld_zimm_val), 32, false))); - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(32))); + if(fld_zimm_val != 0){ + Value* CSR_csr_val = this->builder->CreateAnd( + res_val, + this->builder->CreateNot(this->gen_ext( + this->gen_const(32U, fld_zimm_val), + 32, + false))); + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction MUL - std::tuple __mul(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __mul(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("MUL"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("MUL x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *res_val = this->builder->CreateMul(this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 64, false), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 64, false)); - Value *X_rd_val = this->gen_ext(res_val, 32, false); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* res_val = this->builder->CreateMul( + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 64, + false), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 64, + false)); + Value* X_rd_val = this->gen_ext( + res_val, + 32, + false); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction MULH - std::tuple __mulh(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __mulh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("MULH"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("MULH x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *res_val = this->builder->CreateMul(this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 64, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 64, true)); - Value *X_rd_val = this->gen_ext(this->builder->CreateLShr(res_val, 32), 32, false); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* res_val = this->builder->CreateMul( + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 64, + true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 64, + true)); + Value* X_rd_val = this->gen_ext( + this->builder->CreateLShr( + res_val, + 32), + 32, + false); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction MULHSU - std::tuple __mulhsu(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __mulhsu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("MULHSU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("MULHSU x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *res_val = this->builder->CreateMul(this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 64, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 64, false)); - Value *X_rd_val = this->gen_ext(this->builder->CreateLShr(res_val, 32), 32, false); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* res_val = this->builder->CreateMul( + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 64, + true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 64, + false)); + Value* X_rd_val = this->gen_ext( + this->builder->CreateLShr( + res_val, + 32), + 32, + false); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction MULHU - std::tuple __mulhu(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __mulhu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("MULHU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("MULHU x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *res_val = this->builder->CreateMul(this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 64, false), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 64, false)); - Value *X_rd_val = this->gen_ext(this->builder->CreateLShr(res_val, 32), 32, false); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* res_val = this->builder->CreateMul( + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 64, + false), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 64, + false)); + Value* X_rd_val = this->gen_ext( + this->builder->CreateLShr( + res_val, + 32), + 32, + false); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction DIV - std::tuple __div(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __div(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("DIV"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("DIV x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - llvm::BasicBlock *bbnext = - llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock *bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock *bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + pc=pc+4; + + if(fld_rd_val != 0){ + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder->SetInsertPoint(bb); - this->gen_cond_branch(this->builder->CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(fld_rs2_val, 0), - this->gen_const(32U, 0)), - bb_then, bb_else); + this->gen_cond_branch(this->builder->CreateICmp( + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs2_val, 0), + this->gen_const(32U, 0)), + bb_then, + bb_else); this->builder->SetInsertPoint(bb_then); { - Value *X_rd_val = - this->builder->CreateSDiv(this->gen_ext(this->gen_reg_load(fld_rs1_val, 1), 32, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 1), 32, true)); + Value* X_rd_val = this->builder->CreateSDiv( + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 1), + 32, + true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 1), + 32, + true)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->builder->CreateBr(bbnext); this->builder->SetInsertPoint(bb_else); { - Value *X_rd_val = this->builder->CreateNeg(this->gen_const(32U, 1)); + Value* X_rd_val = this->builder->CreateNeg(this->gen_const(32U, 1)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->builder->CreateBr(bbnext); - bb = bbnext; + bb=bbnext; this->builder->SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction DIVU - std::tuple __divu(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __divu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("DIVU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("DIVU x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - llvm::BasicBlock *bbnext = - llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock *bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock *bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + pc=pc+4; + + if(fld_rd_val != 0){ + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder->SetInsertPoint(bb); - this->gen_cond_branch(this->builder->CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(fld_rs2_val, 0), - this->gen_const(32U, 0)), - bb_then, bb_else); + this->gen_cond_branch(this->builder->CreateICmp( + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs2_val, 0), + this->gen_const(32U, 0)), + bb_then, + bb_else); this->builder->SetInsertPoint(bb_then); { - Value *X_rd_val = - this->builder->CreateUDiv(this->gen_ext(this->gen_reg_load(fld_rs1_val, 1), 32, false), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 1), 32, false)); + Value* X_rd_val = this->builder->CreateUDiv( + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 1), + 32, + false), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 1), + 32, + false)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->builder->CreateBr(bbnext); this->builder->SetInsertPoint(bb_else); { - Value *X_rd_val = this->builder->CreateNeg(this->gen_const(32U, 1)); + Value* X_rd_val = this->builder->CreateNeg(this->gen_const(32U, 1)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->builder->CreateBr(bbnext); - bb = bbnext; + bb=bbnext; this->builder->SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction REM - std::tuple __rem(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __rem(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("REM"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("REM x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - llvm::BasicBlock *bbnext = - llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock *bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock *bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + pc=pc+4; + + if(fld_rd_val != 0){ + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder->SetInsertPoint(bb); - this->gen_cond_branch(this->builder->CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(fld_rs2_val, 0), - this->gen_const(32U, 0)), - bb_then, bb_else); + this->gen_cond_branch(this->builder->CreateICmp( + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs2_val, 0), + this->gen_const(32U, 0)), + bb_then, + bb_else); this->builder->SetInsertPoint(bb_then); { - Value *X_rd_val = - this->builder->CreateSRem(this->gen_ext(this->gen_reg_load(fld_rs1_val, 1), 32, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 1), 32, true)); + Value* X_rd_val = this->builder->CreateSRem( + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 1), + 32, + true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 1), + 32, + true)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->builder->CreateBr(bbnext); this->builder->SetInsertPoint(bb_else); { - Value *X_rd_val = this->gen_reg_load(fld_rs1_val, 1); + Value* X_rd_val = this->gen_reg_load(fld_rs1_val, 1); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->builder->CreateBr(bbnext); - bb = bbnext; + bb=bbnext; this->builder->SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction REMU - std::tuple __remu(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __remu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("REMU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("REMU x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - llvm::BasicBlock *bbnext = - llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock *bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock *bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + pc=pc+4; + + if(fld_rd_val != 0){ + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder->SetInsertPoint(bb); - this->gen_cond_branch(this->builder->CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(fld_rs2_val, 0), - this->gen_const(32U, 0)), - bb_then, bb_else); + this->gen_cond_branch(this->builder->CreateICmp( + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs2_val, 0), + this->gen_const(32U, 0)), + bb_then, + bb_else); this->builder->SetInsertPoint(bb_then); { - Value *X_rd_val = - this->builder->CreateURem(this->gen_ext(this->gen_reg_load(fld_rs1_val, 1), 32, false), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 1), 32, false)); + Value* X_rd_val = this->builder->CreateURem( + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 1), + 32, + false), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 1), + 32, + false)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->builder->CreateBr(bbnext); this->builder->SetInsertPoint(bb_else); { - Value *X_rd_val = this->gen_reg_load(fld_rs1_val, 1); + Value* X_rd_val = this->gen_reg_load(fld_rs1_val, 1); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->builder->CreateBr(bbnext); - bb = bbnext; + bb=bbnext; this->builder->SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction LR.W - std::tuple __lr_w(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __lr_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LR.W"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LR.W x%1$d, x%2$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 32, true); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 32, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); - Value *RES_offs_val = this->gen_ext(this->builder->CreateNeg(this->gen_const(8U, 1)), 32, true); - this->gen_write_mem(traits::RES, offs_val, - this->builder->CreateZExtOrTrunc(RES_offs_val, this->get_type(32))); + Value* RES_offs_val = this->gen_ext( + this->builder->CreateNeg(this->gen_const(8U, 1)), + 32, + true); + this->gen_write_mem( + traits::RES, + offs_val, + this->builder->CreateZExtOrTrunc(RES_offs_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SC.W - std::tuple __sc_w(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sc_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SC.W"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SC.W x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res1_val = this->gen_read_mem(traits::RES, offs_val, 32 / 8); - llvm::BasicBlock *bbnext = - llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock *bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res1_val = this->gen_read_mem(traits::RES, offs_val, 32/8); + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); // this->builder->SetInsertPoint(bb); - this->gen_cond_branch(this->builder->CreateICmp(ICmpInst::ICMP_NE, res1_val, this->gen_const(32U, 0)), bb_then, - bbnext); + this->gen_cond_branch(this->builder->CreateICmp( + ICmpInst::ICMP_NE, + res1_val, + this->gen_const(32U, 0)), + bb_then, + bbnext); this->builder->SetInsertPoint(bb_then); { - Value *MEM_offs_val = this->gen_reg_load(fld_rs2_val, 1); - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 1); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); } this->builder->CreateBr(bbnext); - bb = bbnext; + bb=bbnext; this->builder->SetInsertPoint(bb); - if (fld_rd_val != 0) { - Value *X_rd_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_NE, res1_val, this->gen_const(32U, 0)), - this->gen_const(32U, 0), this->gen_const(32U, 1), 32); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_NE, + res1_val, + this->gen_const(32U, 0)), + this->gen_const(32U, 0), + this->gen_const(32U, 1), + 32); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOSWAP.W - std::tuple __amoswap_w(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amoswap_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOSWAP.W"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOSWAP.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % - (uint64_t)fld_rl_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 32, true); + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 32, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOADD.W - std::tuple __amoadd_w(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amoadd_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOADD.W"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOADD.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % - (uint64_t)fld_rl_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res1_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 32, true); - if (fld_rd_val != 0) { - Value *X_rd_val = res1_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res1_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 32, + true); + if(fld_rd_val != 0){ + Value* X_rd_val = res1_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = this->builder->CreateAdd(res1_val, this->gen_reg_load(fld_rs2_val, 0)); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + Value* res2_val = this->builder->CreateAdd( + res1_val, + this->gen_reg_load(fld_rs2_val, 0)); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOXOR.W - std::tuple __amoxor_w(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amoxor_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOXOR.W"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOXOR.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % - (uint64_t)fld_rl_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res1_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 32, true); - if (fld_rd_val != 0) { - Value *X_rd_val = res1_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res1_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 32, + true); + if(fld_rd_val != 0){ + Value* X_rd_val = res1_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = this->builder->CreateXor(res1_val, this->gen_reg_load(fld_rs2_val, 0)); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + Value* res2_val = this->builder->CreateXor( + res1_val, + this->gen_reg_load(fld_rs2_val, 0)); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOAND.W - std::tuple __amoand_w(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amoand_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOAND.W"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOAND.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % - (uint64_t)fld_rl_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res1_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 32, true); - if (fld_rd_val != 0) { - Value *X_rd_val = res1_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res1_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 32, + true); + if(fld_rd_val != 0){ + Value* X_rd_val = res1_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = this->builder->CreateAnd(res1_val, this->gen_reg_load(fld_rs2_val, 0)); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + Value* res2_val = this->builder->CreateAnd( + res1_val, + this->gen_reg_load(fld_rs2_val, 0)); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOOR.W - std::tuple __amoor_w(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amoor_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOOR.W"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOOR.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % - (uint64_t)fld_rl_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res1_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 32, true); - if (fld_rd_val != 0) { - Value *X_rd_val = res1_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res1_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 32, + true); + if(fld_rd_val != 0){ + Value* X_rd_val = res1_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = this->builder->CreateOr(res1_val, this->gen_reg_load(fld_rs2_val, 0)); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + Value* res2_val = this->builder->CreateOr( + res1_val, + this->gen_reg_load(fld_rs2_val, 0)); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOMIN.W - std::tuple __amomin_w(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amomin_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOMIN.W"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOMIN.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % - (uint64_t)fld_rl_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res1_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 32, true); - if (fld_rd_val != 0) { - Value *X_rd_val = res1_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res1_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 32, + true); + if(fld_rd_val != 0){ + Value* X_rd_val = res1_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_SGT, this->gen_ext(res1_val, 32, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 32, true)), - this->gen_reg_load(fld_rs2_val, 0), res1_val, 32); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + Value* res2_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_SGT, + this->gen_ext( + res1_val, + 32, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 32, true)), + this->gen_reg_load(fld_rs2_val, 0), + res1_val, + 32); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOMAX.W - std::tuple __amomax_w(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amomax_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOMAX.W"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOMAX.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % - (uint64_t)fld_rl_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res1_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 32, true); - if (fld_rd_val != 0) { - Value *X_rd_val = res1_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res1_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 32, + true); + if(fld_rd_val != 0){ + Value* X_rd_val = res1_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_SLT, this->gen_ext(res1_val, 32, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 32, true)), - this->gen_reg_load(fld_rs2_val, 0), res1_val, 32); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + Value* res2_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_SLT, + this->gen_ext( + res1_val, + 32, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 32, true)), + this->gen_reg_load(fld_rs2_val, 0), + res1_val, + 32); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOMINU.W - std::tuple __amominu_w(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amominu_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOMINU.W"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOMINU.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % - (uint64_t)fld_rl_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res1_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 32, false); - if (fld_rd_val != 0) { - Value *X_rd_val = res1_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res1_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 32, + false); + if(fld_rd_val != 0){ + Value* X_rd_val = res1_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_UGT, res1_val, this->gen_reg_load(fld_rs2_val, 0)), - this->gen_reg_load(fld_rs2_val, 0), res1_val, 32); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + Value* res2_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_UGT, + res1_val, + this->gen_reg_load(fld_rs2_val, 0)), + this->gen_reg_load(fld_rs2_val, 0), + res1_val, + 32); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOMAXU.W - std::tuple __amomaxu_w(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amomaxu_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOMAXU.W"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOMAXU.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % - (uint64_t)fld_rl_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res1_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 32, false); - if (fld_rd_val != 0) { - Value *X_rd_val = res1_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res1_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 32, + false); + if(fld_rd_val != 0){ + Value* X_rd_val = res1_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_ULT, this->gen_ext(res1_val, 32, false), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 32, false)), - this->gen_reg_load(fld_rs2_val, 0), res1_val, 32); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + Value* res2_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_ext( + res1_val, + 32, false), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 32, false)), + this->gen_reg_load(fld_rs2_val, 0), + res1_val, + 32); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.ADDI4SPN - std::tuple __c_addi4spn(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_addi4spn(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.ADDI4SPN"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<2, 3>(instr)); - uint16_t fld_nzuimm_val = 0 | (bit_sub<5, 1>(instr) << 3) | (bit_sub<6, 1>(instr) << 2) | - (bit_sub<7, 4>(instr) << 6) | (bit_sub<11, 2>(instr) << 4); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<2,3>(instr)); + uint16_t fld_nzuimm_val = 0 | (bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.ADDI4SPN x%1$d, 0x%2$05x"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_nzuimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - - if (fld_nzuimm_val == 0) { + pc=pc+2; + + if(fld_nzuimm_val == 0){ this->gen_raise_trap(0, 2); } uint8_t rd_idx_val = (fld_rd_val + 8); uint8_t x2_idx_val = 2; - Value *X_rd_idx_val = - this->builder->CreateAdd(this->gen_reg_load(x2_idx_val, 0), this->gen_const(32U, fld_nzuimm_val)); + Value* X_rd_idx_val = this->builder->CreateAdd( + this->gen_reg_load(x2_idx_val, 0), + this->gen_const(32U, fld_nzuimm_val)); this->builder->CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.LW - std::tuple __c_lw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_lw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.LW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<2, 3>(instr)); - uint8_t fld_uimm_val = - 0 | (bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3); - uint8_t fld_rs1_val = 0 | (bit_sub<7, 3>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<2,3>(instr)); + uint8_t fld_uimm_val = 0 | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3); + uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.LW x(8+%1$d), x(8+%2$d), 0x%3$05x"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_uimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t rs1_idx_val = (fld_rs1_val + 8); - Value *adr_val = - this->builder->CreateAdd(this->gen_reg_load(rs1_idx_val, 0), this->gen_const(32U, fld_uimm_val)); + Value* adr_val = this->builder->CreateAdd( + this->gen_reg_load(rs1_idx_val, 0), + this->gen_const(32U, fld_uimm_val)); uint8_t rd_idx_val = (fld_rd_val + 8); - Value *X_rd_idx_val = this->gen_read_mem(traits::MEM, adr_val, 32 / 8); + Value* X_rd_idx_val = this->gen_read_mem(traits::MEM, adr_val, 32/8); this->builder->CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.SW - std::tuple __c_sw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_sw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.SW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rs2_val = 0 | (bit_sub<2, 3>(instr)); - uint8_t fld_uimm_val = - 0 | (bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3); - uint8_t fld_rs1_val = 0 | (bit_sub<7, 3>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rs2_val = 0 | (bit_sub<2,3>(instr)); + uint8_t fld_uimm_val = 0 | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3); + uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.SW x(8+%1$d), x(8+%2$d), 0x%3$05x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_uimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t rs1_idx_val = (fld_rs1_val + 8); - Value *adr_val = - this->builder->CreateAdd(this->gen_reg_load(rs1_idx_val, 0), this->gen_const(32U, fld_uimm_val)); + Value* adr_val = this->builder->CreateAdd( + this->gen_reg_load(rs1_idx_val, 0), + this->gen_const(32U, fld_uimm_val)); uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value *MEM_adr_val = this->gen_reg_load(rs2_idx_val, 0); - this->gen_write_mem(traits::MEM, adr_val, - this->builder->CreateZExtOrTrunc(MEM_adr_val, this->get_type(32))); + Value* MEM_adr_val = this->gen_reg_load(rs2_idx_val, 0); + this->gen_write_mem( + traits::MEM, + adr_val, + this->builder->CreateZExtOrTrunc(MEM_adr_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.NOP - std::tuple __c_nop(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_nop(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.NOP"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.NOP "); - ins_fmter; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + ins_fmter ; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + /* TODO: describe operations for C.NOP ! */ this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.ADDI - std::tuple __c_addi(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_addi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.ADDI"); - + this->gen_sync(iss::PRE_SYNC); - - int8_t fld_nzimm_val = 0 | (bit_sub<2, 5>(instr)) | (signed_bit_sub<12, 1>(instr) << 5); - uint8_t fld_rs1_val = 0 | (bit_sub<7, 5>(instr)); - if (this->disass_enabled) { + + int8_t fld_nzimm_val = 0 | (bit_sub<2,5>(instr)) | (signed_bit_sub<12,1>(instr) << 5); + uint8_t fld_rs1_val = 0 | (bit_sub<7,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.ADDI x%1$d, 0x%2$05x"); ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_nzimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - - if (fld_nzimm_val == 0) { + pc=pc+2; + + if(fld_nzimm_val == 0){ this->gen_raise_trap(0, 2); } - Value *X_rs1_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_nzimm_val)); + Value* X_rs1_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_nzimm_val)); this->builder->CreateStore(X_rs1_val, get_reg_ptr(fld_rs1_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.JAL - std::tuple __c_jal(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_jal(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.JAL"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | - (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) | (bit_sub<8, 1>(instr) << 10) | - (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | - (signed_bit_sub<12, 1>(instr) << 11); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (signed_bit_sub<12,1>(instr) << 11); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.JAL 0x%1$05x"); ins_fmter % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t rd_val = 1; - Value *X_rd_val = this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, 2)); + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, 2)); this->builder->CreateStore(X_rd_val, get_reg_ptr(rd_val), false); - Value *PC_val = - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, fld_imm_val)); + Value* PC_val = this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, fld_imm_val)); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction C.LI - std::tuple __c_li(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_li(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.LI"); - + this->gen_sync(iss::PRE_SYNC); - - int8_t fld_imm_val = 0 | (bit_sub<2, 5>(instr)) | (signed_bit_sub<12, 1>(instr) << 5); - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - if (this->disass_enabled) { + + int8_t fld_imm_val = 0 | (bit_sub<2,5>(instr)) | (signed_bit_sub<12,1>(instr) << 5); + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.LI x%1$d, 0x%2$05x"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - - if (fld_rd_val == 0) { + pc=pc+2; + + if(fld_rd_val == 0){ this->gen_raise_trap(0, 2); } - Value *X_rd_val = this->gen_const(32U, fld_imm_val); + Value* X_rd_val = this->gen_const(32U, fld_imm_val); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.LUI - std::tuple __c_lui(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_lui(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.LUI"); - + this->gen_sync(iss::PRE_SYNC); - - int32_t fld_nzimm_val = 0 | (bit_sub<2, 5>(instr) << 12) | (signed_bit_sub<12, 1>(instr) << 17); - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - if (this->disass_enabled) { + + int32_t fld_nzimm_val = 0 | (bit_sub<2,5>(instr) << 12) | (signed_bit_sub<12,1>(instr) << 17); + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.LUI x%1$d, 0x%2$05x"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_nzimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - - if (fld_rd_val == 0) { + pc=pc+2; + + if(fld_rd_val == 0){ this->gen_raise_trap(0, 2); } - if (fld_rd_val == 2) { + if(fld_rd_val == 2){ this->gen_raise_trap(0, 2); } - if (fld_nzimm_val == 0) { + if(fld_nzimm_val == 0){ this->gen_raise_trap(0, 2); } - Value *X_rd_val = this->gen_const(32U, fld_nzimm_val); + Value* X_rd_val = this->gen_const(32U, fld_nzimm_val); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.ADDI16SP - std::tuple __c_addi16sp(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_addi16sp(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.ADDI16SP"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_nzimm_val = 0 | (bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 7) | - (bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 4) | - (signed_bit_sub<12, 1>(instr) << 9); - if (this->disass_enabled) { + + int16_t fld_nzimm_val = 0 | (bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (signed_bit_sub<12,1>(instr) << 9); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.ADDI16SP 0x%1$05x"); ins_fmter % (int64_t)fld_nzimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t x2_idx_val = 2; - Value *X_x2_idx_val = this->builder->CreateAdd(this->gen_ext(this->gen_reg_load(x2_idx_val, 0), 32, true), - this->gen_const(32U, fld_nzimm_val)); + Value* X_x2_idx_val = this->builder->CreateAdd( + this->gen_ext( + this->gen_reg_load(x2_idx_val, 0), + 32, true), + this->gen_const(32U, fld_nzimm_val)); this->builder->CreateStore(X_x2_idx_val, get_reg_ptr(x2_idx_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.SRLI - std::tuple __c_srli(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_srli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.SRLI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_shamt_val = 0 | (bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5); - uint8_t fld_rs1_val = 0 | (bit_sub<7, 3>(instr)); - if (this->disass_enabled) { + + uint8_t fld_shamt_val = 0 | (bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5); + uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.SRLI x(8+%1$d), %2$d"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - - if (fld_shamt_val > 31) { + pc=pc+2; + + if(fld_shamt_val > 31){ this->gen_raise_trap(0, 2); } uint8_t rs1_idx_val = (fld_rs1_val + 8); - Value *X_rs1_idx_val = - this->builder->CreateLShr(this->gen_reg_load(rs1_idx_val, 0), this->gen_const(32U, fld_shamt_val)); + Value* X_rs1_idx_val = this->builder->CreateLShr( + this->gen_reg_load(rs1_idx_val, 0), + this->gen_const(32U, fld_shamt_val)); this->builder->CreateStore(X_rs1_idx_val, get_reg_ptr(rs1_idx_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.SRAI - std::tuple __c_srai(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_srai(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.SRAI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_shamt_val = 0 | (bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5); - uint8_t fld_rs1_val = 0 | (bit_sub<7, 3>(instr)); - if (this->disass_enabled) { + + uint8_t fld_shamt_val = 0 | (bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5); + uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.SRAI x(8+%1$d), %2$d"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - - if (fld_shamt_val > 31) { + pc=pc+2; + + if(fld_shamt_val > 31){ this->gen_raise_trap(0, 2); } uint8_t rs1_idx_val = (fld_rs1_val + 8); - Value *X_rs1_idx_val = - this->builder->CreateAShr(this->gen_reg_load(rs1_idx_val, 0), this->gen_const(32U, fld_shamt_val)); + Value* X_rs1_idx_val = this->builder->CreateAShr( + this->gen_reg_load(rs1_idx_val, 0), + this->gen_const(32U, fld_shamt_val)); this->builder->CreateStore(X_rs1_idx_val, get_reg_ptr(rs1_idx_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.ANDI - std::tuple __c_andi(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_andi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.ANDI"); - + this->gen_sync(iss::PRE_SYNC); - - int8_t fld_imm_val = 0 | (bit_sub<2, 5>(instr)) | (signed_bit_sub<12, 1>(instr) << 5); - uint8_t fld_rs1_val = 0 | (bit_sub<7, 3>(instr)); - if (this->disass_enabled) { + + int8_t fld_imm_val = 0 | (bit_sub<2,5>(instr)) | (signed_bit_sub<12,1>(instr) << 5); + uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.ANDI x(8+%1$d), 0x%2$05x"); ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t rs1_idx_val = (fld_rs1_val + 8); - Value *X_rs1_idx_val = - this->builder->CreateAnd(this->gen_reg_load(rs1_idx_val, 0), this->gen_const(32U, fld_imm_val)); + Value* X_rs1_idx_val = this->builder->CreateAnd( + this->gen_reg_load(rs1_idx_val, 0), + this->gen_const(32U, fld_imm_val)); this->builder->CreateStore(X_rs1_idx_val, get_reg_ptr(rs1_idx_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.SUB - std::tuple __c_sub(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_sub(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.SUB"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rs2_val = 0 | (bit_sub<2, 3>(instr)); - uint8_t fld_rd_val = 0 | (bit_sub<7, 3>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rs2_val = 0 | (bit_sub<2,3>(instr)); + uint8_t fld_rd_val = 0 | (bit_sub<7,3>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.SUB x(8+%1$d), x(8+%2$d)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t rd_idx_val = (fld_rd_val + 8); uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value *X_rd_idx_val = - this->builder->CreateSub(this->gen_reg_load(rd_idx_val, 0), this->gen_reg_load(rs2_idx_val, 0)); + Value* X_rd_idx_val = this->builder->CreateSub( + this->gen_reg_load(rd_idx_val, 0), + this->gen_reg_load(rs2_idx_val, 0)); this->builder->CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.XOR - std::tuple __c_xor(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_xor(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.XOR"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rs2_val = 0 | (bit_sub<2, 3>(instr)); - uint8_t fld_rd_val = 0 | (bit_sub<7, 3>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rs2_val = 0 | (bit_sub<2,3>(instr)); + uint8_t fld_rd_val = 0 | (bit_sub<7,3>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.XOR x(8+%1$d), x(8+%2$d)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t rd_idx_val = (fld_rd_val + 8); uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value *X_rd_idx_val = - this->builder->CreateXor(this->gen_reg_load(rd_idx_val, 0), this->gen_reg_load(rs2_idx_val, 0)); + Value* X_rd_idx_val = this->builder->CreateXor( + this->gen_reg_load(rd_idx_val, 0), + this->gen_reg_load(rs2_idx_val, 0)); this->builder->CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.OR - std::tuple __c_or(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_or(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.OR"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rs2_val = 0 | (bit_sub<2, 3>(instr)); - uint8_t fld_rd_val = 0 | (bit_sub<7, 3>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rs2_val = 0 | (bit_sub<2,3>(instr)); + uint8_t fld_rd_val = 0 | (bit_sub<7,3>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.OR x(8+%1$d), x(8+%2$d)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t rd_idx_val = (fld_rd_val + 8); uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value *X_rd_idx_val = - this->builder->CreateOr(this->gen_reg_load(rd_idx_val, 0), this->gen_reg_load(rs2_idx_val, 0)); + Value* X_rd_idx_val = this->builder->CreateOr( + this->gen_reg_load(rd_idx_val, 0), + this->gen_reg_load(rs2_idx_val, 0)); this->builder->CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.AND - std::tuple __c_and(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_and(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.AND"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rs2_val = 0 | (bit_sub<2, 3>(instr)); - uint8_t fld_rd_val = 0 | (bit_sub<7, 3>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rs2_val = 0 | (bit_sub<2,3>(instr)); + uint8_t fld_rd_val = 0 | (bit_sub<7,3>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.AND x(8+%1$d), x(8+%2$d)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t rd_idx_val = (fld_rd_val + 8); uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value *X_rd_idx_val = - this->builder->CreateAnd(this->gen_reg_load(rd_idx_val, 0), this->gen_reg_load(rs2_idx_val, 0)); + Value* X_rd_idx_val = this->builder->CreateAnd( + this->gen_reg_load(rd_idx_val, 0), + this->gen_reg_load(rs2_idx_val, 0)); this->builder->CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.J - std::tuple __c_j(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __c_j(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.J"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | - (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) | (bit_sub<8, 1>(instr) << 10) | - (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | - (signed_bit_sub<12, 1>(instr) << 11); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (signed_bit_sub<12,1>(instr) << 11); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.J 0x%1$05x"); ins_fmter % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - - Value *PC_val = - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, fld_imm_val)); + pc=pc+2; + + Value* PC_val = this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, fld_imm_val)); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction C.BEQZ - std::tuple __c_beqz(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_beqz(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.BEQZ"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | - (bit_sub<5, 2>(instr) << 6) | (bit_sub<10, 2>(instr) << 3) | - (signed_bit_sub<12, 1>(instr) << 8); - uint8_t fld_rs1d_val = 0 | (bit_sub<7, 3>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (signed_bit_sub<12,1>(instr) << 8); + uint8_t fld_rs1d_val = 0 | (bit_sub<7,3>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.BEQZ x(8+%1$d), 0x%2$05x"); ins_fmter % (uint64_t)fld_rs1d_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t rs1_val = (fld_rs1d_val + 8); - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1_val, 0), this->gen_const(32U, 0)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, 2)), 32); + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_EQ, + this->gen_reg_load(rs1_val, 0), + this->gen_const(32U, 0)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, 2)), + 32); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction C.BNEZ - std::tuple __c_bnez(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_bnez(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.BNEZ"); - + this->gen_sync(iss::PRE_SYNC); - - uint16_t fld_imm_val = 0 | (bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | - (bit_sub<5, 2>(instr) << 6) | (bit_sub<10, 2>(instr) << 3) | - (bit_sub<12, 1>(instr) << 8); - uint8_t fld_rs1d_val = 0 | (bit_sub<7, 3>(instr)); - if (this->disass_enabled) { + + uint16_t fld_imm_val = 0 | (bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8); + uint8_t fld_rs1d_val = 0 | (bit_sub<7,3>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.BNEZ x(8+%1$d),, 0x%2$05x"); ins_fmter % (uint64_t)fld_rs1d_val % (uint64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t rs1_val = (fld_rs1d_val + 8); - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs1_val, 0), this->gen_const(32U, 0)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, 2)), 32); + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_NE, + this->gen_reg_load(rs1_val, 0), + this->gen_const(32U, 0)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, 2)), + 32); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction C.SLLI - std::tuple __c_slli(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_slli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.SLLI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_shamt_val = 0 | (bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5); - uint8_t fld_rs1_val = 0 | (bit_sub<7, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_shamt_val = 0 | (bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5); + uint8_t fld_rs1_val = 0 | (bit_sub<7,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.SLLI x%1$d, %2$d"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - - if (fld_rs1_val == 0) { + pc=pc+2; + + if(fld_rs1_val == 0){ this->gen_raise_trap(0, 2); } - if (fld_shamt_val > 31) { + if(fld_shamt_val > 31){ this->gen_raise_trap(0, 2); } - Value *X_rs1_val = - this->builder->CreateShl(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_shamt_val)); + Value* X_rs1_val = this->builder->CreateShl( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_shamt_val)); this->builder->CreateStore(X_rs1_val, get_reg_ptr(fld_rs1_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.LQSP - std::tuple __c_lqsp(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_lqsp(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.LQSP"); - + this->gen_sync(iss::PRE_SYNC); - - uint16_t fld_uimm_val = - 0 | (bit_sub<2, 4>(instr) << 6) | (bit_sub<6, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 5); - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - if (this->disass_enabled) { + + uint16_t fld_uimm_val = 0 | (bit_sub<2,4>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 5); + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("C.LQSP"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("C.LQSP"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + /* TODO: describe operations for C.LQSP ! */ this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.LWSP - std::tuple __c_lwsp(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_lwsp(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.LWSP"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_uimm_val = - 0 | (bit_sub<2, 2>(instr) << 6) | (bit_sub<4, 3>(instr) << 2) | (bit_sub<12, 1>(instr) << 5); - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_uimm_val = 0 | (bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5); + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.LWSP x%1$d, sp, 0x%2$05x"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_uimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t x2_idx_val = 2; - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(x2_idx_val, 0), this->gen_const(32U, fld_uimm_val)); - Value *X_rd_val = this->gen_read_mem(traits::MEM, offs_val, 32 / 8); + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(x2_idx_val, 0), + this->gen_const(32U, fld_uimm_val)); + Value* X_rd_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.MV - std::tuple __c_mv(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_mv(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.MV"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rs2_val = 0 | (bit_sub<2, 5>(instr)); - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rs2_val = 0 | (bit_sub<2,5>(instr)); + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.MV x%1$d, x%2$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - - Value *X_rd_val = this->gen_reg_load(fld_rs2_val, 0); + pc=pc+2; + + Value* X_rd_val = this->gen_reg_load(fld_rs2_val, 0); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.JR - std::tuple __c_jr(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_jr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.JR"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rs1_val = 0 | (bit_sub<7, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rs1_val = 0 | (bit_sub<7,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.JR x%1$d"); ins_fmter % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - - Value *PC_val = this->gen_reg_load(fld_rs1_val, 0); + pc=pc+2; + + Value* PC_val = this->gen_reg_load(fld_rs1_val, 0); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction C.EBREAK - std::tuple __c_ebreak(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_ebreak(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.EBREAK"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("C.EBREAK"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("C.EBREAK"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + this->gen_raise_trap(0, 3); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction C.ADD - std::tuple __c_add(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_add(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.ADD"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rs2_val = 0 | (bit_sub<2, 5>(instr)); - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rs2_val = 0 | (bit_sub<2,5>(instr)); + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.ADD x%1$d, x%2$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - - Value *X_rd_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rd_val, 0), this->gen_reg_load(fld_rs2_val, 0)); + pc=pc+2; + + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rd_val, 0), + this->gen_reg_load(fld_rs2_val, 0)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction C.JALR - std::tuple __c_jalr(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_jalr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.JALR"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rs1_val = 0 | (bit_sub<7, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rs1_val = 0 | (bit_sub<7,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.JALR x%1$d"); ins_fmter % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t rd_val = 1; - Value *X_rd_val = this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(32U, 2)); + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(32U, 2)); this->builder->CreateStore(X_rd_val, get_reg_ptr(rd_val), false); - Value *PC_val = this->gen_reg_load(fld_rs1_val, 0); + Value* PC_val = this->gen_reg_load(fld_rs1_val, 0); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction C.SWSP - std::tuple __c_swsp(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __c_swsp(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("C.SWSP"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rs2_val = 0 | (bit_sub<2, 5>(instr)); - uint8_t fld_uimm_val = 0 | (bit_sub<7, 2>(instr) << 6) | (bit_sub<9, 4>(instr) << 2); - if (this->disass_enabled) { + + uint8_t fld_rs2_val = 0 | (bit_sub<2,5>(instr)); + uint8_t fld_uimm_val = 0 | (bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("C.SWSP x2+0x%1$05x, x%2$d"); ins_fmter % (uint64_t)fld_uimm_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 2; - + pc=pc+2; + uint8_t x2_idx_val = 2; - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(x2_idx_val, 0), this->gen_const(32U, fld_uimm_val)); - Value *MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(x2_idx_val, 0), + this->gen_const(32U, fld_uimm_val)); + Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - - /* end generated code */ + +/* end generated code */ /**************************************************************************** * end opcode definitions ****************************************************************************/ @@ -4012,7 +4416,8 @@ template inline void vm_impl::gen_trap_check(llvm::BasicBl } // namespace rv32imac -template <> std::unique_ptr create(arch::rv32imac *core, unsigned short port, bool dump) { +template <> +std::unique_ptr create(arch::rv32imac *core, unsigned short port, bool dump) { std::unique_ptr> ret = std::make_unique>(*core, dump); if (port != 0) debugger::server::run_server(ret.get(), port); diff --git a/riscv/src/internal/vm_rv64ia.cpp b/riscv/src/internal/vm_rv64ia.cpp index 832884e..026e198 100644 --- a/riscv/src/internal/vm_rv64ia.cpp +++ b/riscv/src/internal/vm_rv64ia.cpp @@ -34,8 +34,8 @@ // //////////////////////////////////////////////////////////////////////////////// -#include #include +#include #include #include #include @@ -368,2615 +368,2957 @@ private: {32, 0b11100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_d}, }; // instruction LWU - std::tuple __lwu(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lwu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LWU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LWU x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 64, false); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 64, + false); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction LD - std::tuple __ld(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __ld(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LD"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LD x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 64 / 8), 64, true); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 64/8), + 64, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SD - std::tuple __sd(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sd(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SD"); - + this->gen_sync(iss::PRE_SYNC); - - uint16_t fld_imm_val = 0 | (bit_sub<7, 5>(instr)) | (signed_bit_sub<25, 7>(instr) << 5); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SD x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), - this->gen_ext(this->gen_const(64U, fld_imm_val), 64, true)); - Value *MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(64))); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_ext( + this->gen_const(64U, fld_imm_val), + 64, + true)); + Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLLI - std::tuple __slli(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __slli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLLI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_shamt_val = 0 | (bit_sub<20, 6>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_shamt_val = 0 | (bit_sub<20,6>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLLI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateShl(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_shamt_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateShl( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_shamt_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SRLI - std::tuple __srli(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __srli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRLI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_shamt_val = 0 | (bit_sub<20, 6>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_shamt_val = 0 | (bit_sub<20,6>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SRLI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateLShr(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_shamt_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateLShr( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_shamt_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SRAI - std::tuple __srai(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __srai(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRAI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_shamt_val = 0 | (bit_sub<20, 6>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_shamt_val = 0 | (bit_sub<20,6>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SRAI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAShr(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_shamt_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAShr( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_shamt_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction ADDIW - std::tuple __addiw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __addiw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("ADDIW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("ADDIW x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = this->builder->CreateAdd( - this->gen_ext(this->builder->CreateTrunc(this->gen_reg_load(fld_rs1_val, 0), this->get_type(32)), 64, - true), - this->gen_ext(this->gen_const(64U, fld_imm_val), 64, true)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAdd( + this->gen_ext( + this->builder->CreateTrunc( + this->gen_reg_load(fld_rs1_val, 0), + this-> get_type(32) + ), + 64, + true), + this->gen_ext( + this->gen_const(64U, fld_imm_val), + 64, + true)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLLIW - std::tuple __slliw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __slliw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLLIW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_shamt_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_shamt_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLLIW x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *sh_val_val = this->builder->CreateShl( - this->builder->CreateTrunc(this->gen_reg_load(fld_rs1_val, 0), this->get_type(32)), + pc=pc+4; + + if(fld_rd_val != 0){ + Value* sh_val_val = this->builder->CreateShl( + this->builder->CreateTrunc( + this->gen_reg_load(fld_rs1_val, 0), + this-> get_type(32) + ), this->gen_const(32U, fld_shamt_val)); - Value *X_rd_val = this->gen_ext(sh_val_val, 64, true); + Value* X_rd_val = this->gen_ext( + sh_val_val, + 64, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SRLIW - std::tuple __srliw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __srliw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRLIW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_shamt_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_shamt_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SRLIW x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *sh_val_val = - this->builder->CreateLShr(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_shamt_val)); - Value *X_rd_val = this->gen_ext(sh_val_val, 64, true); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* sh_val_val = this->builder->CreateLShr( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_shamt_val)); + Value* X_rd_val = this->gen_ext( + sh_val_val, + 64, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SRAIW - std::tuple __sraiw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sraiw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRAIW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_shamt_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_shamt_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SRAIW x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *sh_val_val = - this->builder->CreateAShr(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(32U, fld_shamt_val)); - Value *X_rd_val = this->gen_ext(sh_val_val, 64, true); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* sh_val_val = this->builder->CreateAShr( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(32U, fld_shamt_val)); + Value* X_rd_val = this->gen_ext( + sh_val_val, + 64, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction ADDW - std::tuple __addw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __addw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("ADDW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("ADDW"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("ADDW"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + /* TODO: describe operations for ADDW ! */ this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SUBW - std::tuple __subw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __subw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SUBW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("SUBW"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("SUBW"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + /* TODO: describe operations for SUBW ! */ this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLLW - std::tuple __sllw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sllw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLLW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLLW x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *sh_val_val = this->builder->CreateShl( + pc=pc+4; + + if(fld_rd_val != 0){ + Value* sh_val_val = this->builder->CreateShl( this->gen_reg_load(fld_rs1_val, 0), - this->builder->CreateAnd(this->gen_reg_load(fld_rs2_val, 0), this->gen_const(32U, 31))); - Value *X_rd_val = this->gen_ext(sh_val_val, 64, true); + this->builder->CreateAnd( + this->gen_reg_load(fld_rs2_val, 0), + this->gen_const(32U, 31))); + Value* X_rd_val = this->gen_ext( + sh_val_val, + 64, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SRLW - std::tuple __srlw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __srlw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRLW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SRLW x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *sh_val_val = this->builder->CreateLShr( + pc=pc+4; + + if(fld_rd_val != 0){ + Value* sh_val_val = this->builder->CreateLShr( this->gen_reg_load(fld_rs1_val, 0), - this->builder->CreateAnd(this->gen_reg_load(fld_rs2_val, 0), this->gen_const(32U, 31))); - Value *X_rd_val = this->gen_ext(sh_val_val, 64, true); + this->builder->CreateAnd( + this->gen_reg_load(fld_rs2_val, 0), + this->gen_const(32U, 31))); + Value* X_rd_val = this->gen_ext( + sh_val_val, + 64, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SRAW - std::tuple __sraw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sraw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRAW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SRAW x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *sh_val_val = this->builder->CreateAShr( + pc=pc+4; + + if(fld_rd_val != 0){ + Value* sh_val_val = this->builder->CreateAShr( this->gen_reg_load(fld_rs1_val, 0), - this->builder->CreateAnd(this->gen_reg_load(fld_rs2_val, 0), this->gen_const(32U, 31))); - Value *X_rd_val = this->gen_ext(sh_val_val, 64, true); + this->builder->CreateAnd( + this->gen_reg_load(fld_rs2_val, 0), + this->gen_const(32U, 31))); + Value* X_rd_val = this->gen_ext( + sh_val_val, + 64, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction LUI - std::tuple __lui(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lui(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LUI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - int32_t fld_imm_val = 0 | (signed_bit_sub<12, 20>(instr) << 12); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + int32_t fld_imm_val = 0 | (signed_bit_sub<12,20>(instr) << 12); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LUI x%1$d, 0x%2$05x"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_const(64U, fld_imm_val); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_const(64U, fld_imm_val); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AUIPC - std::tuple __auipc(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __auipc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AUIPC"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - int32_t fld_imm_val = 0 | (signed_bit_sub<12, 20>(instr) << 12); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + int32_t fld_imm_val = 0 | (signed_bit_sub<12,20>(instr) << 12); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AUIPC x%1%, 0x%2$08x"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, fld_imm_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, fld_imm_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction JAL - std::tuple __jal(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __jal(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("JAL"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - int32_t fld_imm_val = 0 | (bit_sub<12, 8>(instr) << 12) | (bit_sub<20, 1>(instr) << 11) | - (bit_sub<21, 10>(instr) << 1) | (signed_bit_sub<31, 1>(instr) << 20); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + int32_t fld_imm_val = 0 | (bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (signed_bit_sub<31,1>(instr) << 20); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("JAL x%1$d, 0x%2$x"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, 4)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, 4)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *PC_val = - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, fld_imm_val)); + Value* PC_val = this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, fld_imm_val)); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction JALR - std::tuple __jalr(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __jalr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("JALR"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("JALR x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, 4)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, 4)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *ret_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); - Value *PC_val = this->builder->CreateAnd(ret_val, this->builder->CreateNot(this->gen_const(64U, 1))); + Value* ret_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); + Value* PC_val = this->builder->CreateAnd( + ret_val, + this->builder->CreateNot(this->gen_const(64U, 1))); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction BEQ - std::tuple __beq(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __beq(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("BEQ"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | - (bit_sub<25, 6>(instr) << 5) | (signed_bit_sub<31, 1>(instr) << 12); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("BEQ x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(fld_rs1_val, 0), - this->gen_reg_load(fld_rs2_val, 0)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, 4)), 64); + pc=pc+4; + + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_EQ, + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, 4)), + 64); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction BNE - std::tuple __bne(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __bne(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("BNE"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | - (bit_sub<25, 6>(instr) << 5) | (signed_bit_sub<31, 1>(instr) << 12); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("BNE x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(fld_rs1_val, 0), - this->gen_reg_load(fld_rs2_val, 0)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, 4)), 64); + pc=pc+4; + + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, 4)), + 64); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction BLT - std::tuple __blt(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __blt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("BLT"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | - (bit_sub<25, 6>(instr) << 5) | (signed_bit_sub<31, 1>(instr) << 12); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("BLT x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_SLT, this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 64, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 64, true)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, 4)), 64); + pc=pc+4; + + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_SLT, + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 64, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 64, true)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, 4)), + 64); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction BGE - std::tuple __bge(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __bge(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("BGE"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | - (bit_sub<25, 6>(instr) << 5) | (signed_bit_sub<31, 1>(instr) << 12); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("BGE x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_SGE, this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 64, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 64, true)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, 4)), 64); + pc=pc+4; + + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_SGE, + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 64, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 64, true)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, 4)), + 64); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction BLTU - std::tuple __bltu(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __bltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("BLTU"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | - (bit_sub<25, 6>(instr) << 5) | (signed_bit_sub<31, 1>(instr) << 12); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("BLTU x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(fld_rs1_val, 0), - this->gen_reg_load(fld_rs2_val, 0)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, 4)), 64); + pc=pc+4; + + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, 4)), + 64); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction BGEU - std::tuple __bgeu(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __bgeu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("BGEU"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | - (bit_sub<25, 6>(instr) << 5) | (signed_bit_sub<31, 1>(instr) << 12); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("BGEU x%1$d, x%2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *PC_val = this->gen_choose( - this->builder->CreateICmp(ICmpInst::ICMP_UGE, this->gen_reg_load(fld_rs1_val, 0), - this->gen_reg_load(fld_rs2_val, 0)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, fld_imm_val)), - this->builder->CreateAdd(this->gen_reg_load(traits::PC, 0), this->gen_const(64U, 4)), 64); + pc=pc+4; + + Value* PC_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_UGE, + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, fld_imm_val)), + this->builder->CreateAdd( + this->gen_reg_load(traits::PC, 0), + this->gen_const(64U, 4)), + 64); this->builder->CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction LB - std::tuple __lb(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LB"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LB x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 8 / 8), 64, true); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 8/8), + 64, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction LH - std::tuple __lh(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LH"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LH x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 16 / 8), 64, true); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 16/8), + 64, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction LW - std::tuple __lw(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LW x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 32 / 8), 64, true); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 32/8), + 64, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction LBU - std::tuple __lbu(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lbu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LBU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LBU x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 8 / 8), 64, false); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 8/8), + 64, + false); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction LHU - std::tuple __lhu(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __lhu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LHU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LHU x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 16 / 8), 64, false); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 16/8), + 64, + false); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SB - std::tuple __sb(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SB"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 5>(instr)) | (signed_bit_sub<25, 7>(instr) << 5); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SB x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); - Value *MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(8))); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); + Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(8))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SH - std::tuple __sh(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SH"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 5>(instr)) | (signed_bit_sub<25, 7>(instr) << 5); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SH x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); - Value *MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(16))); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); + Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(16))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SW - std::tuple __sw(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SW"); - + this->gen_sync(iss::PRE_SYNC); - - int16_t fld_imm_val = 0 | (bit_sub<7, 5>(instr)) | (signed_bit_sub<25, 7>(instr) << 5); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SW x%1$d, %2%(x%3$d)"); ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); - Value *MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(32))); + pc=pc+4; + + Value* offs_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); + Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction ADDI - std::tuple __addi(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __addi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("ADDI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("ADDI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLTI - std::tuple __slti(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __slti(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLTI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLTI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_SLT, - this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 64, true), - this->gen_ext(this->gen_const(64U, fld_imm_val), 64, true)), - this->gen_const(64U, 1), this->gen_const(64U, 0), 64); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_SLT, + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 64, true), + this->gen_ext( + this->gen_const(64U, fld_imm_val), + 64, true)), + this->gen_const(64U, 1), + this->gen_const(64U, 0), + 64); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLTIU - std::tuple __sltiu(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sltiu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLTIU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLTIU x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + int64_t full_imm_val = fld_imm_val; - if (fld_rd_val != 0) { - Value *X_rd_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_ULT, - this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 64, false), - this->gen_ext(full_imm_val, 64, false)), - this->gen_const(64U, 1), this->gen_const(64U, 0), 64); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 64, false), + this->gen_ext( + full_imm_val, + 64, false)), + this->gen_const(64U, 1), + this->gen_const(64U, 0), + 64); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction XORI - std::tuple __xori(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __xori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("XORI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("XORI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateXor(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateXor( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction ORI - std::tuple __ori(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __ori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("ORI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("ORI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateOr(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateOr( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction ANDI - std::tuple __andi(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __andi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("ANDI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - int16_t fld_imm_val = 0 | (signed_bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAnd(this->gen_reg_load(fld_rs1_val, 0), this->gen_const(64U, fld_imm_val)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAnd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_const(64U, fld_imm_val)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction ADD - std::tuple __add(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __add(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("ADD"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("ADD x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAdd(this->gen_reg_load(fld_rs1_val, 0), this->gen_reg_load(fld_rs2_val, 0)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAdd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SUB - std::tuple __sub(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sub(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SUB"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SUB x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateSub(this->gen_reg_load(fld_rs1_val, 0), this->gen_reg_load(fld_rs2_val, 0)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateSub( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLL - std::tuple __sll(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sll(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLL"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLL x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = this->builder->CreateShl( - this->gen_reg_load(fld_rs1_val, 0), this->builder->CreateAnd(this->gen_reg_load(fld_rs2_val, 0), 63)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateShl( + this->gen_reg_load(fld_rs1_val, 0), + this->builder->CreateAnd( + this->gen_reg_load(fld_rs2_val, 0), + 63)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLT - std::tuple __slt(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __slt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLT"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLT x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_SLT, - this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 64, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 64, true)), - this->gen_const(64U, 1), this->gen_const(64U, 0), 64); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_SLT, + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 64, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 64, true)), + this->gen_const(64U, 1), + this->gen_const(64U, 0), + 64); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SLTU - std::tuple __sltu(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SLTU"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SLTU x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->gen_choose(this->builder->CreateICmp( - ICmpInst::ICMP_ULT, this->gen_ext(this->gen_reg_load(fld_rs1_val, 0), 64, false), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 64, false)), - this->gen_const(64U, 1), this->gen_const(64U, 0), 64); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_ext( + this->gen_reg_load(fld_rs1_val, 0), + 64, + false), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 64, + false)), + this->gen_const(64U, 1), + this->gen_const(64U, 0), + 64); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction XOR - std::tuple __xor(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __xor(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("XOR"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("XOR x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateXor(this->gen_reg_load(fld_rs1_val, 0), this->gen_reg_load(fld_rs2_val, 0)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateXor( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SRL - std::tuple __srl(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __srl(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRL"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SRL x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = this->builder->CreateLShr( - this->gen_reg_load(fld_rs1_val, 0), this->builder->CreateAnd(this->gen_reg_load(fld_rs2_val, 0), 63)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateLShr( + this->gen_reg_load(fld_rs1_val, 0), + this->builder->CreateAnd( + this->gen_reg_load(fld_rs2_val, 0), + 63)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SRA - std::tuple __sra(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __sra(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRA"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SRA x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = this->builder->CreateAShr( - this->gen_reg_load(fld_rs1_val, 0), this->builder->CreateAnd(this->gen_reg_load(fld_rs2_val, 0), 63)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAShr( + this->gen_reg_load(fld_rs1_val, 0), + this->builder->CreateAnd( + this->gen_reg_load(fld_rs2_val, 0), + 63)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction OR - std::tuple __or(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __or(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("OR"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("OR x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateOr(this->gen_reg_load(fld_rs1_val, 0), this->gen_reg_load(fld_rs2_val, 0)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateOr( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AND - std::tuple __and(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __and(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AND"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AND x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = - this->builder->CreateAnd(this->gen_reg_load(fld_rs1_val, 0), this->gen_reg_load(fld_rs2_val, 0)); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->builder->CreateAnd( + this->gen_reg_load(fld_rs1_val, 0), + this->gen_reg_load(fld_rs2_val, 0)); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction FENCE - std::tuple __fence(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __fence(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("FENCE"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_succ_val = 0 | (bit_sub<20, 4>(instr)); - uint8_t fld_pred_val = 0 | (bit_sub<24, 4>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_succ_val = 0 | (bit_sub<20,4>(instr)); + uint8_t fld_pred_val = 0 | (bit_sub<24,4>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("FENCE"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("FENCE"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *FENCE_fence_val = this->builder->CreateOr( - this->builder->CreateShl(this->gen_const(64U, fld_pred_val), this->gen_const(64U, 4)), + pc=pc+4; + + Value* FENCE_fence_val = this->builder->CreateOr( + this->builder->CreateShl( + this->gen_const(64U, fld_pred_val), + this->gen_const(64U, 4)), this->gen_const(64U, fld_succ_val)); - this->gen_write_mem(traits::FENCE, (uint64_t)0, - this->builder->CreateZExtOrTrunc(FENCE_fence_val, this->get_type(64))); + this->gen_write_mem( + traits::FENCE, + (uint64_t)0, + this->builder->CreateZExtOrTrunc(FENCE_fence_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction FENCE_I - std::tuple __fence_i(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __fence_i(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("FENCE_I"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_imm_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("FENCE_I"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("FENCE_I"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *FENCE_fencei_val = this->gen_const(64U, fld_imm_val); - this->gen_write_mem(traits::FENCE, (uint64_t)1, - this->builder->CreateZExtOrTrunc(FENCE_fencei_val, this->get_type(64))); + pc=pc+4; + + Value* FENCE_fencei_val = this->gen_const(64U, fld_imm_val); + this->gen_write_mem( + traits::FENCE, + (uint64_t)1, + this->builder->CreateZExtOrTrunc(FENCE_fencei_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::FLUSH, nullptr); } - + // instruction ECALL - std::tuple __ecall(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __ecall(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("ECALL"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("ECALL"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("ECALL"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + this->gen_raise_trap(0, 11); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction EBREAK - std::tuple __ebreak(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __ebreak(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("EBREAK"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("EBREAK"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("EBREAK"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + this->gen_raise_trap(0, 3); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction URET - std::tuple __uret(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __uret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("URET"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("URET"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("URET"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + this->gen_leave_trap(0); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction SRET - std::tuple __sret(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SRET"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("SRET"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("SRET"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + this->gen_leave_trap(1); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction MRET - std::tuple __mret(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __mret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("MRET"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("MRET"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("MRET"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + this->gen_leave_trap(3); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ this->gen_trap_check(this->leave_blk); return std::make_tuple(iss::vm::BRANCH, nullptr); } - + // instruction WFI - std::tuple __wfi(virt_addr_t &pc, code_word_t instr, llvm::BasicBlock *bb) { + std::tuple __wfi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("WFI"); - + this->gen_sync(iss::PRE_SYNC); - + ; - if (this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("WFI"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("WFI"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - + pc=pc+4; + this->gen_wait(1); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SFENCE.VMA - std::tuple __sfence_vma(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sfence_vma(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SFENCE.VMA"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ - std::string opcode("SFENCE.VMA"); - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v"); - fmter % pc.val % opcode; - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr("SFENCE.VMA"), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *FENCE_fencevmal_val = this->gen_const(64U, fld_rs1_val); - this->gen_write_mem(traits::FENCE, (uint64_t)2, - this->builder->CreateZExtOrTrunc(FENCE_fencevmal_val, this->get_type(64))); - Value *FENCE_fencevmau_val = this->gen_const(64U, fld_rs2_val); - this->gen_write_mem(traits::FENCE, (uint64_t)3, - this->builder->CreateZExtOrTrunc(FENCE_fencevmau_val, this->get_type(64))); + pc=pc+4; + + Value* FENCE_fencevmal_val = this->gen_const(64U, fld_rs1_val); + this->gen_write_mem( + traits::FENCE, + (uint64_t)2, + this->builder->CreateZExtOrTrunc(FENCE_fencevmal_val,this->get_type(64))); + Value* FENCE_fencevmau_val = this->gen_const(64U, fld_rs2_val); + this->gen_write_mem( + traits::FENCE, + (uint64_t)3, + this->builder->CreateZExtOrTrunc(FENCE_fencevmau_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction CSRRW - std::tuple __csrrw(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __csrrw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("CSRRW"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_csr_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("CSRRW x%1$d, %2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *rs_val_val = this->gen_reg_load(fld_rs1_val, 0); - if (fld_rd_val != 0) { - Value *csr_val_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64 / 8); - Value *CSR_csr_val = rs_val_val; - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(64))); - Value *X_rd_val = csr_val_val; + pc=pc+4; + + Value* rs_val_val = this->gen_reg_load(fld_rs1_val, 0); + if(fld_rd_val != 0){ + Value* csr_val_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64/8); + Value* CSR_csr_val = rs_val_val; + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); + Value* X_rd_val = csr_val_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } else { - Value *CSR_csr_val = rs_val_val; - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(64))); + Value* CSR_csr_val = rs_val_val; + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction CSRRS - std::tuple __csrrs(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __csrrs(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("CSRRS"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_csr_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("CSRRS x%1$d, %2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64 / 8); - Value *xrs1_val = this->gen_reg_load(fld_rs1_val, 0); - if (fld_rd_val != 0) { - Value *X_rd_val = xrd_val; + pc=pc+4; + + Value* xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64/8); + Value* xrs1_val = this->gen_reg_load(fld_rs1_val, 0); + if(fld_rd_val != 0){ + Value* X_rd_val = xrd_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - if (fld_rs1_val != 0) { - Value *CSR_csr_val = this->builder->CreateOr(xrd_val, xrs1_val); - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(64))); + if(fld_rs1_val != 0){ + Value* CSR_csr_val = this->builder->CreateOr( + xrd_val, + xrs1_val); + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction CSRRC - std::tuple __csrrc(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __csrrc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("CSRRC"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_csr_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("CSRRC x%1$d, %2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64 / 8); - Value *xrs1_val = this->gen_reg_load(fld_rs1_val, 0); - if (fld_rd_val != 0) { - Value *X_rd_val = xrd_val; + pc=pc+4; + + Value* xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64/8); + Value* xrs1_val = this->gen_reg_load(fld_rs1_val, 0); + if(fld_rd_val != 0){ + Value* X_rd_val = xrd_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - if (fld_rs1_val != 0) { - Value *CSR_csr_val = this->builder->CreateAnd(xrd_val, this->builder->CreateNot(xrs1_val)); - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(64))); + if(fld_rs1_val != 0){ + Value* CSR_csr_val = this->builder->CreateAnd( + xrd_val, + this->builder->CreateNot(xrs1_val)); + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction CSRRWI - std::tuple __csrrwi(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __csrrwi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("CSRRWI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_zimm_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_csr_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("CSRRWI x%1$d, %2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64 / 8); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64/8); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *CSR_csr_val = this->gen_ext(this->gen_const(64U, fld_zimm_val), 64, false); - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(64))); + Value* CSR_csr_val = this->gen_ext( + this->gen_const(64U, fld_zimm_val), + 64, + false); + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction CSRRSI - std::tuple __csrrsi(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __csrrsi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("CSRRSI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_zimm_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_csr_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("CSRRSI x%1$d, %2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64 / 8); - if (fld_zimm_val != 0) { - Value *CSR_csr_val = - this->builder->CreateOr(res_val, this->gen_ext(this->gen_const(64U, fld_zimm_val), 64, false)); - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(64))); + pc=pc+4; + + Value* res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64/8); + if(fld_zimm_val != 0){ + Value* CSR_csr_val = this->builder->CreateOr( + res_val, + this->gen_ext( + this->gen_const(64U, fld_zimm_val), + 64, + false)); + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); } - if (fld_rd_val != 0) { - Value *X_rd_val = res_val; + if(fld_rd_val != 0){ + Value* X_rd_val = res_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction CSRRCI - std::tuple __csrrci(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __csrrci(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("CSRRCI"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_zimm_val = 0 | (bit_sub<15, 5>(instr)); - uint16_t fld_csr_val = 0 | (bit_sub<20, 12>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr)); + uint16_t fld_csr_val = 0 | (bit_sub<20,12>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("CSRRCI x%1$d, %2$d, 0x%3$x"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64 / 8); - if (fld_rd_val != 0) { - Value *X_rd_val = res_val; + pc=pc+4; + + Value* res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64/8); + if(fld_rd_val != 0){ + Value* X_rd_val = res_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - if (fld_zimm_val != 0) { - Value *CSR_csr_val = this->builder->CreateAnd( - res_val, this->builder->CreateNot(this->gen_ext(this->gen_const(64U, fld_zimm_val), 64, false))); - this->gen_write_mem(traits::CSR, fld_csr_val, - this->builder->CreateZExtOrTrunc(CSR_csr_val, this->get_type(64))); + if(fld_zimm_val != 0){ + Value* CSR_csr_val = this->builder->CreateAnd( + res_val, + this->builder->CreateNot(this->gen_ext( + this->gen_const(64U, fld_zimm_val), + 64, + false))); + this->gen_write_mem( + traits::CSR, + fld_csr_val, + this->builder->CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction LR.D - std::tuple __lr_d(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __lr_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("LR.D"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("LR.D x%1$d, x%2$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - if (fld_rd_val != 0) { - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 64 / 8), 64, true); + pc=pc+4; + + if(fld_rd_val != 0){ + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 64/8), + 64, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); - Value *RES_offs_val = this->gen_ext(this->builder->CreateNeg(this->gen_const(8U, 1)), 64, true); - this->gen_write_mem(traits::RES, offs_val, - this->builder->CreateZExtOrTrunc(RES_offs_val, this->get_type(64))); + Value* RES_offs_val = this->gen_ext( + this->builder->CreateNeg(this->gen_const(8U, 1)), + 64, + true); + this->gen_write_mem( + traits::RES, + offs_val, + this->builder->CreateZExtOrTrunc(RES_offs_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction SC.D - std::tuple __sc_d(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __sc_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("SC.D"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("SC.D x%1$d, x%2$d, x%3$d"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res_val = this->gen_read_mem(traits::RES, offs_val, 8 / 8); - llvm::BasicBlock *bbnext = - llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock *bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock *bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res_val = this->gen_read_mem(traits::RES, offs_val, 8/8); + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder->SetInsertPoint(bb); - this->gen_cond_branch(this->builder->CreateICmp(ICmpInst::ICMP_NE, res_val, this->gen_const(64U, 0)), bb_then, - bb_else); + this->gen_cond_branch(this->builder->CreateICmp( + ICmpInst::ICMP_NE, + res_val, + this->gen_const(64U, 0)), + bb_then, + bb_else); this->builder->SetInsertPoint(bb_then); { - Value *MEM_offs_val = this->gen_reg_load(fld_rs2_val, 1); - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(64))); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_const(64U, 0); + Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 1); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_const(64U, 0); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } } this->builder->CreateBr(bbnext); this->builder->SetInsertPoint(bb_else); { - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_const(64U, 1); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_const(64U, 1); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } } this->builder->CreateBr(bbnext); - bb = bbnext; + bb=bbnext; this->builder->SetInsertPoint(bb); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOSWAP.D - std::tuple __amoswap_d(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amoswap_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOSWAP.D"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOSWAP.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - if (fld_rd_val != 0) { - Value *X_rd_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 64 / 8), 64, true); + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + if(fld_rd_val != 0){ + Value* X_rd_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 64/8), + 64, + true); this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(64))); + Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val, 0); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOADD.D - std::tuple __amoadd_d(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amoadd_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOADD.D"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOADD.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 64 / 8), 64, true); - if (fld_rd_val != 0) { - Value *X_rd_val = res_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 64/8), + 64, + true); + if(fld_rd_val != 0){ + Value* X_rd_val = res_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = this->builder->CreateAdd(res_val, this->gen_reg_load(fld_rs2_val, 0)); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(64))); + Value* res2_val = this->builder->CreateAdd( + res_val, + this->gen_reg_load(fld_rs2_val, 0)); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOXOR.D - std::tuple __amoxor_d(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amoxor_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOXOR.D"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOXOR.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 64 / 8), 64, true); - if (fld_rd_val != 0) { - Value *X_rd_val = res_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 64/8), + 64, + true); + if(fld_rd_val != 0){ + Value* X_rd_val = res_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = this->builder->CreateXor(res_val, this->gen_reg_load(fld_rs2_val, 0)); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(64))); + Value* res2_val = this->builder->CreateXor( + res_val, + this->gen_reg_load(fld_rs2_val, 0)); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOAND.D - std::tuple __amoand_d(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amoand_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOAND.D"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOAND.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 64 / 8), 64, true); - if (fld_rd_val != 0) { - Value *X_rd_val = res_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 64/8), + 64, + true); + if(fld_rd_val != 0){ + Value* X_rd_val = res_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = this->builder->CreateAnd(res_val, this->gen_reg_load(fld_rs2_val, 0)); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(64))); + Value* res2_val = this->builder->CreateAnd( + res_val, + this->gen_reg_load(fld_rs2_val, 0)); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOOR.D - std::tuple __amoor_d(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amoor_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOOR.D"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOOR.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 64 / 8), 64, true); - if (fld_rd_val != 0) { - Value *X_rd_val = res_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 64/8), + 64, + true); + if(fld_rd_val != 0){ + Value* X_rd_val = res_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = this->builder->CreateOr(res_val, this->gen_reg_load(fld_rs2_val, 0)); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(64))); + Value* res2_val = this->builder->CreateOr( + res_val, + this->gen_reg_load(fld_rs2_val, 0)); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOMIN.D - std::tuple __amomin_d(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amomin_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOMIN.D"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOMIN.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 64 / 8), 64, true); - if (fld_rd_val != 0) { - Value *X_rd_val = res_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 64/8), + 64, + true); + if(fld_rd_val != 0){ + Value* X_rd_val = res_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_SGT, this->gen_ext(res_val, 64, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 64, true)), - this->gen_reg_load(fld_rs2_val, 0), res_val, 64); - Value *MEM_offs_val = res_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(64))); + Value* res2_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_SGT, + this->gen_ext( + res_val, + 64, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 64, true)), + this->gen_reg_load(fld_rs2_val, 0), + res_val, + 64); + Value* MEM_offs_val = res_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOMAX.D - std::tuple __amomax_d(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amomax_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOMAX.D"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOMAX.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 64 / 8), 64, true); - if (fld_rd_val != 0) { - Value *X_rd_val = res_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 64/8), + 64, + true); + if(fld_rd_val != 0){ + Value* X_rd_val = res_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_SLT, this->gen_ext(res_val, 64, true), - this->gen_ext(this->gen_reg_load(fld_rs2_val, 0), 64, true)), - this->gen_reg_load(fld_rs2_val, 0), res_val, 64); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(64))); + Value* res2_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_SLT, + this->gen_ext( + res_val, + 64, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val, 0), + 64, true)), + this->gen_reg_load(fld_rs2_val, 0), + res_val, + 64); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOMINU.D - std::tuple __amominu_d(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amominu_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOMINU.D"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOMINU.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 64 / 8), 64, false); - if (fld_rd_val != 0) { - Value *X_rd_val = res_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 64/8), + 64, + false); + if(fld_rd_val != 0){ + Value* X_rd_val = res_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_UGT, res_val, this->gen_reg_load(fld_rs2_val, 0)), - this->gen_reg_load(fld_rs2_val, 0), res_val, 64); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(64))); + Value* res2_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_UGT, + res_val, + this->gen_reg_load(fld_rs2_val, 0)), + this->gen_reg_load(fld_rs2_val, 0), + res_val, + 64); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - + // instruction AMOMAXU.D - std::tuple __amomaxu_d(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple __amomaxu_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ bb->setName("AMOMAXU.D"); - + this->gen_sync(iss::PRE_SYNC); - - uint8_t fld_rd_val = 0 | (bit_sub<7, 5>(instr)); - uint8_t fld_rs1_val = 0 | (bit_sub<15, 5>(instr)); - uint8_t fld_rs2_val = 0 | (bit_sub<20, 5>(instr)); - uint8_t fld_rl_val = 0 | (bit_sub<25, 1>(instr)); - uint8_t fld_aq_val = 0 | (bit_sub<26, 1>(instr)); - if (this->disass_enabled) { + + uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); + uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); + uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr)); + uint8_t fld_rl_val = 0 | (bit_sub<25,1>(instr)); + uint8_t fld_aq_val = 0 | (bit_sub<26,1>(instr)); + if(this->disass_enabled){ /* generate console output when executing the command */ boost::format ins_fmter("AMOMAXU.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - boost::format fmter("0x%1$016x\t\t%2$-40s\t\t"); - fmter % pc.val % ins_fmter.str(); - std::vector args{this->core_ptr, this->builder->CreateGlobalStringPtr(fmter.str())}; + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder->CreateGlobalStringPtr(ins_fmter.str()), + }; this->builder->CreateCall(this->mod->getFunction("print_disass"), args); } - pc = pc + 4; - - Value *offs_val = this->gen_reg_load(fld_rs1_val, 0); - Value *res_val = this->gen_ext(this->gen_read_mem(traits::MEM, offs_val, 64 / 8), 64, false); - if (fld_rd_val != 0) { - Value *X_rd_val = res_val; + pc=pc+4; + + Value* offs_val = this->gen_reg_load(fld_rs1_val, 0); + Value* res_val = this->gen_ext( + this->gen_read_mem(traits::MEM, offs_val, 64/8), + 64, + false); + if(fld_rd_val != 0){ + Value* X_rd_val = res_val; this->builder->CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false); } - Value *res2_val = - this->gen_choose(this->builder->CreateICmp(ICmpInst::ICMP_ULT, res_val, this->gen_reg_load(fld_rs2_val, 0)), - this->gen_reg_load(fld_rs2_val, 0), res_val, 64); - Value *MEM_offs_val = res2_val; - this->gen_write_mem(traits::MEM, offs_val, - this->builder->CreateZExtOrTrunc(MEM_offs_val, this->get_type(64))); + Value* res2_val = this->gen_choose( + this->builder->CreateICmp( + ICmpInst::ICMP_ULT, + res_val, + this->gen_reg_load(fld_rs2_val, 0)), + this->gen_reg_load(fld_rs2_val, 0), + res_val, + 64); + Value* MEM_offs_val = res2_val; + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder->CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */ - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, - this->leave_blk); /* create next BasicBlock in chain */ + bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(vm::CONT, bb); } - - /* end generated code */ + +/* end generated code */ /**************************************************************************** * end opcode definitions ****************************************************************************/ @@ -3100,8 +3442,10 @@ template inline void vm_impl::gen_trap_check(llvm::BasicBl } // namespace rv64ia -template <> std::unique_ptr create(arch::rv64ia *core, unsigned short port, bool dump) { - std::unique_ptr> ret = std::make_unique>(*core, dump); +template <> +std::unique_ptr create(arch::rv64ia *core, unsigned short port, bool dump) { + std::unique_ptr> ret = + std::make_unique>(*core, dump); if (port != 0) debugger::server::run_server(ret.get(), port); return ret; }