diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index 924f928..d85a562 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -719,23 +719,23 @@ template <typename BASE, typename LOGCAT = logging::disass> struct riscv_hart_co
     }
 
     iss::status read_vxsat(unsigned addr, reg_t& val) {
-        val = csr[vxsat];
+        val = this->get_vxsat();
         return iss::Ok;
     }
 
     iss::status write_vxsat(unsigned addr, reg_t val) {
-        csr[vxsat] = val & 1;
+        this->set_vxsat(val & 1);
         csr[vcsr] = (~1ULL & csr[vcsr]) | (val & 1);
         return iss::Ok;
     }
 
     iss::status read_vxrm(unsigned addr, reg_t& val) {
-        val = csr[vxrm];
+        val = this->get_vxrm();
         return iss::Ok;
     }
 
     iss::status write_vxrm(unsigned addr, reg_t val) {
-        csr[vxrm] = val & 0b11;
+        this->set_vxrm(val & 0b11);
         csr[vcsr] = (~0b110ULL & csr[vcsr]) | ((val & 0b11) << 1);
         return iss::Ok;
     }
diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h
index 42b8517..b11c162 100644
--- a/src/iss/arch/tgc5c.h
+++ b/src/iss/arch/tgc5c.h
@@ -246,6 +246,7 @@ struct tgc5c: public arch_if {
         uint32_t last_branch = 0; // indicates if last branch was taken
     } reg;
 #pragma pack(pop)
+    std::array<address_type, 4> addr_mode;
     
     uint64_t interrupt_sim=0;
 
diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp
index a8e8e36..dee3a67 100644
--- a/src/vm/interp/vm_tgc5c.cpp
+++ b/src/vm/interp/vm_tgc5c.cpp
@@ -734,11 +734,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-<<<<<<< HEAD
-                                        uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-=======
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) ));
->>>>>>> 530e9da (updates templates and adds newly generated files)
                                         int16_t res_2 = super::template read_mem<int16_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         int16_t res = (int16_t)res_2;
@@ -770,11 +766,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-<<<<<<< HEAD
-                                        uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-=======
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) ));
->>>>>>> 530e9da (updates templates and adds newly generated files)
                                         int32_t res_3 = super::template read_mem<int32_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         int32_t res = (int32_t)res_3;
@@ -806,11 +798,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-<<<<<<< HEAD
-                                        uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-=======
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) ));
->>>>>>> 530e9da (updates templates and adds newly generated files)
                                         uint8_t res_4 = super::template read_mem<uint8_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         uint8_t res = res_4;
@@ -842,11 +830,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         raise(0, traits::RV_CAUSE_ILLEGAL_INSTRUCTION);
                                     }
                                     else {
-<<<<<<< HEAD
-                                        uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
-=======
                                         uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (int64_t)((int16_t)sext<12>(imm) ));
->>>>>>> 530e9da (updates templates and adds newly generated files)
                                         uint16_t res_5 = super::template read_mem<uint16_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         uint16_t res = res_5;
@@ -2784,12 +2768,11 @@ std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short por
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
-#include <iss/arch/riscv_hart_msu_vp.h>
 #include <iss/arch/riscv_hart_mu_p.h>
 #include <iss/factory.h>
 namespace iss {
 namespace {
-volatile std::array<bool, 3> dummy = {
+volatile std::array<bool, 2> dummy = {
         core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
 		    auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
@@ -2809,18 +2792,8 @@ volatile std::array<bool, 3> dummy = {
                 cpu->set_semihosting_callback(*cb);
             }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
-        }),
-        core_factory::instance().register_creator("tgc5c|mus_vp|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
-            auto* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::tgc5c>();
-		    auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
-		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
-            if(init_data){
-                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
-                cpu->set_semihosting_callback(*cb);
-            }
-            return {cpu_ptr{cpu}, vm_ptr{vm}};
         })
 };
 }
 }
-// clang-format on
+// clang-format on
\ No newline at end of file