diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index 5b0c92a..6abd9d0 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -1065,8 +1065,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned length
 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
     if(addr==cfg.clic_base) { // cliccfg
-        clic_cfg_reg = *data;
-        clic_cfg_reg&= 0x7e;
+        clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e);
 //    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
 //        write_uint32(addr, clic_info_reg, data, length);
     } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 7cf099f..2a6c29e 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -473,7 +473,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
         csr_wr_cb[mintthresh] = &this_class::write_intthresh;
 
         clic_int_reg.resize(cfg.clic_num_irq,  clic_int_reg_t{.raw=0});
-        clic_cfg_reg=0x20;
+        clic_cfg_reg=0x30;
         clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq;
         insert_mem_range(cfg.clic_base, 0x5000UL,
                 [this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);},
@@ -1231,8 +1231,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned lengt
 template<typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
     if(addr==cfg.clic_base) { // cliccfg
-        clic_cfg_reg = *data;
-        clic_cfg_reg&= 0x7e;
+        clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e);
 //    } else if(addr>=(cfg.clic_base+4) && (addr+length)<=(cfg.clic_base+4)){ // clicinfo
 //        write_uint32(addr, clic_info_reg, data, length);
     } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig