From 836ba269e3e25f3e437bfc0ad5e93db61e04772c Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Mon, 16 Aug 2021 15:05:05 +0200
Subject: [PATCH] fix clic reset values

---
 incl/iss/arch/riscv_hart_mu_p.h | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/incl/iss/arch/riscv_hart_mu_p.h b/incl/iss/arch/riscv_hart_mu_p.h
index c59de82..78bcf00 100644
--- a/incl/iss/arch/riscv_hart_mu_p.h
+++ b/incl/iss/arch/riscv_hart_mu_p.h
@@ -326,6 +326,7 @@ private:
     iss::status write_edeleg(unsigned addr, reg_t val);
     iss::status read_hartid(unsigned addr, reg_t &val);
     iss::status write_epc(unsigned addr, reg_t val);
+    iss::status write_intstatus(unsigned addr, reg_t val);
     iss::status write_intthresh(unsigned addr, reg_t val);
 
     reg_t mhartid_reg{0x0};
@@ -348,7 +349,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
     // reset values
     csr[misa] = traits<BASE>::MISA_VAL;
     csr[mvendorid] = 0x669;
-    csr[marchid] = 0x80000003;
+    csr[marchid] = 0x80000004;
     csr[mimpid] = 1;
     csr[mclicbase] = 0xc0000000; // TODO: should be taken from YAML file
 
@@ -446,7 +447,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
         csr_rd_cb[mxnti] = &this_class::read_csr_reg;
         csr_wr_cb[mxnti] = &this_class::write_csr_reg;
         csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
-        csr_wr_cb[mintstatus] = &this_class::write_csr_reg;
+        csr_wr_cb[mintstatus] = &this_class::write_null;
         csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg;
         csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg;
         csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg;
@@ -459,7 +460,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
         clic_base_addr=0xC0000000;
         clic_num_irq=16;
         clic_int_reg.resize(clic_num_irq);
-        clic_cfg_reg=0x40;
+        clic_cfg_reg=0x20;
         clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + clic_num_irq;
         mcause_max_irq=clic_num_irq+16;
     }
@@ -934,7 +935,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
 }
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_edeleg(unsigned addr, reg_t val) {
-    auto mask = 0xf7f7; // bit 11 (Env call) and 3 (break) are hardwired to 0
+    auto mask = 0b1011001111110111; // bit 14/10 (reserved), bit 11 (Env call), and 3 (break) are hardwired to 0
     csr[medeleg] = (csr[medeleg] & ~mask) | (val & mask);
     return iss::Ok;
 }
@@ -1100,7 +1101,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_clic(uint64_t addr, unsigned lengt
     if(addr==clic_base_addr) { // cliccfg
         *data=clic_cfg_reg;
         for(auto i=1; i<length; ++i) *(data+i)=0;
-    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+4)){ // clicinfo
+    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+8)){ // clicinfo
         read_uint32(addr, clic_info_reg, data, length);
     } else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0x40+clic_num_trigger*4)){ // clicinttrig
         auto offset = ((addr&0x7fff)-0x40)/4;
@@ -1119,8 +1120,8 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned leng
     if(addr==clic_base_addr) { // cliccfg
         clic_cfg_reg = *data;
         clic_cfg_reg&= 0x7f;
-    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+4)){ // clicinfo
-        write_uint32(addr, clic_info_reg, data, length);
+//    } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+4)){ // clicinfo
+//        write_uint32(addr, clic_info_reg, data, length);
     } else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0xC0)){ // clicinttrig
         auto offset = ((addr&0x7fff)-0x40)/4;
         write_uint32(addr, clic_inttrig_reg[offset], data, length);