From 769610d6fc227efa4970808741ef0a857503152d Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sat, 24 Nov 2018 20:29:24 +0100 Subject: [PATCH] Improved disassembly of running ISS --- conanfile.txt | 8 +- dbt-core | 2 +- riscv/gen_input/RV32A.core_desc | 22 +- riscv/gen_input/RV32C.core_desc | 74 +- riscv/gen_input/RV32D.core_desc | 52 +- riscv/gen_input/RV32F.core_desc | 52 +- riscv/gen_input/RV32IBase.core_desc | 119 +- riscv/gen_input/RV32M.core_desc | 16 +- riscv/gen_input/RV64A.core_desc | 22 +- riscv/gen_input/RV64IBase.core_desc | 26 +- riscv/gen_input/RV64M.core_desc | 10 +- riscv/gen_input/templates/incl-CORENAME.h.gtl | 58 +- .../gen_input/templates/src-CORENAME.cpp.gtl | 4 +- .../templates/vm-vm_CORENAME.cpp.gtl | 87 +- riscv/gen_input/templates/vm_riscv.in.cpp | 322 -- riscv/incl/iss/arch/riscv_hart_msu_vp.h | 7 +- riscv/incl/iss/arch/rv32gc.h | 136 +- riscv/incl/iss/arch/rv32imac.h | 105 +- riscv/incl/iss/arch/rv64ia.h | 134 +- .../incl/iss/debugger/riscv_target_adapter.h | 25 +- riscv/src/internal/vm_rv32gc.cpp | 3917 +++++++++-------- riscv/src/internal/vm_rv32imac.cpp | 2938 +++++++------ riscv/src/internal/vm_rv64ia.cpp | 2229 +++++----- riscv/src/iss/rv32gc.cpp | 5 + riscv/src/iss/rv32imac.cpp | 6 +- riscv/src/iss/rv64ia.cpp | 5 + sc-components | 2 +- 27 files changed, 5277 insertions(+), 5106 deletions(-) delete mode 100644 riscv/gen_input/templates/vm_riscv.in.cpp diff --git a/conanfile.txt b/conanfile.txt index c1205ab..3d6f0e2 100644 --- a/conanfile.txt +++ b/conanfile.txt @@ -1,6 +1,7 @@ [requires] - gsl_microsoft/20180102@bincrafters/stable - spdlog/0.16.3@bincrafters/stable + gsl_microsoft/20180102@bincrafters/stable + spdlog/0.16.3@bincrafters/stable + fmt/5.2.1@bincrafters/stable Seasocks/1.3.2@minres/stable SystemC/2.3.2@minres/stable SystemCVerification/2.0.1@minres/stable @@ -11,7 +12,8 @@ [options] Seasocks:shared=True + fmt:header_only=True SystemC:stdcxx=14 SystemC:shared=True SystemCVerification:stdcxx=14 - SystemC-CCI:stdcxx=14 \ No newline at end of file + SystemC-CCI:stdcxx=14 diff --git a/dbt-core b/dbt-core index 0b499d2..83cd591 160000 --- a/dbt-core +++ b/dbt-core @@ -1 +1 @@ -Subproject commit 0b499d216a2835015b889180ca5108b2daaed9b9 +Subproject commit 83cd591e4935d5c1916e4e56d9c6147e3aab8480 diff --git a/riscv/gen_input/RV32A.core_desc b/riscv/gen_input/RV32A.core_desc index 16638c5..694da0f 100644 --- a/riscv/gen_input/RV32A.core_desc +++ b/riscv/gen_input/RV32A.core_desc @@ -9,7 +9,7 @@ InsructionSet RV32A extends RV32IBase{ instructions{ LR.W { encoding: b00010 | aq[0:0] | rl[0:0] | b00000 | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d"; + args_disass: "{name(rd)}, {name(rs1)}"; if(rd!=0){ val offs[XLEN] <= X[rs1]; X[rd]<= sext(MEM[offs]{32}, XLEN); @@ -18,7 +18,7 @@ InsructionSet RV32A extends RV32IBase{ } SC.W { encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)}"; val offs[XLEN] <= X[rs1]; val res1[32] <= RES[offs]{32}; if(res1!=0) @@ -27,14 +27,14 @@ InsructionSet RV32A extends RV32IBase{ } AMOSWAP.W{ encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN]<=X[rs1]; if(rd!=0) X[rd]<=sext(MEM[offs]{32}); MEM[offs]{32}<=X[rs2]; } AMOADD.W{ encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN]<=X[rs1]; val res1[XLEN] <= sext(MEM[offs]{32}); if(rd!=0) X[rd]<=res1; @@ -43,7 +43,7 @@ InsructionSet RV32A extends RV32IBase{ } AMOXOR.W{ encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN]<=X[rs1]; val res1[XLEN] <= sext(MEM[offs]{32}); if(rd!=0) X[rd]<=res1; @@ -52,7 +52,7 @@ InsructionSet RV32A extends RV32IBase{ } AMOAND.W{ encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN]<=X[rs1]; val res1[XLEN] <= sext(MEM[offs]{32}); if(rd!=0) X[rd]<=res1; @@ -61,7 +61,7 @@ InsructionSet RV32A extends RV32IBase{ } AMOOR.W { encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN]<=X[rs1]; val res1[XLEN] <= sext(MEM[offs]{32}); if(rd!=0) X[rd]<=res1; @@ -70,7 +70,7 @@ InsructionSet RV32A extends RV32IBase{ } AMOMIN.W{ encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN]<=X[rs1]; val res1[XLEN] <= sext(MEM[offs]{32}); if(rd!=0) X[rd]<=res1; @@ -79,7 +79,7 @@ InsructionSet RV32A extends RV32IBase{ } AMOMAX.W{ encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN]<=X[rs1]; val res1[XLEN] <= sext(MEM[offs]{32}); if(rd!=0) X[rd]<=res1; @@ -88,7 +88,7 @@ InsructionSet RV32A extends RV32IBase{ } AMOMINU.W{ encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN]<=X[rs1]; val res1[XLEN] <= zext(MEM[offs]{32}); if(rd!=0) X[rd]<=res1; @@ -97,7 +97,7 @@ InsructionSet RV32A extends RV32IBase{ } AMOMAXU.W{ encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN]<=X[rs1]; val res1[XLEN] <= zext(MEM[offs]{32}); if(rd!=0) X[rd]<=res1; diff --git a/riscv/gen_input/RV32C.core_desc b/riscv/gen_input/RV32C.core_desc index f7de2f6..7c92b55 100644 --- a/riscv/gen_input/RV32C.core_desc +++ b/riscv/gen_input/RV32C.core_desc @@ -14,7 +14,7 @@ InsructionSet RV32IC { instructions{ JALR(no_cont){ // overwriting the implementation if rv32i, alignment does not need to be word encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111; - args_disass: "x%rd$d, x%rs1$d, 0x%imm$x"; + args_disass: "{name(rd)}, {name(rs1)}, {imm:#0x}"; val new_pc[XLEN] <= X[rs1]s+ imm; val align[XLEN] <= new_pc & 0x1; if(align != 0){ @@ -26,25 +26,25 @@ InsructionSet RV32IC { } C.ADDI4SPN { //(RES, imm=0) encoding: b000 | imm[5:4] | imm[9:6] | imm[2:2] | imm[3:3] | rd[2:0] | b00; - args_disass: "x%rd$d, 0x%imm$05x"; + args_disass: "{name(rd)}, {imm:#05x}"; if(imm == 0) raise(0, 2); X[rd+8] <= X[2] + imm; } C.LW { // (RV32) encoding: b010 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00; - args_disass: "x(8+%rd$d), x(8+%rs1$d), 0x%uimm$05x"; + args_disass: "{name(8+rd)}, {name(8+rs1)}, {uimm:#05x}"; val offs[XLEN] <= X[rs1+8]+uimm; X[rd+8] <= MEM[offs]{32}; } C.SW {//(RV32) encoding: b110 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00; - args_disass: "x(8+%rs1$d), x(8+%rs2$d), 0x%uimm$05x"; + args_disass: "{name(8+rs1)}, {name(8+rs2)}, {uimm:#05x}"; val offs[XLEN] <= X[rs1+8]+uimm; MEM[offs]{32} <= X[rs2+8]; } C.ADDI {//(RV32) encoding:b000 | imm[5:5]s | rs1[4:0] | imm[4:0]s | b01; - args_disass: "x%rs1$d, 0x%imm$05x"; + args_disass: "{name(rs1)}, {imm:#05x}"; X[rs1] <= X[rs1]'s + imm; } C.NOP { @@ -53,118 +53,118 @@ InsructionSet RV32IC { // C.JAL will be overwritten by C.ADDIW for RV64/128 C.JAL(no_cont) {//(RV32) encoding: b001 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01; - args_disass: "0x%imm$05x"; + args_disass: "{imm:#05x}"; X[1] <= PC+2; PC<=PC's+imm; } C.LI {//(RV32) encoding:b010 | imm[5:5]s | rd[4:0] | imm[4:0]s | b01; - args_disass: "x%rd$d, 0x%imm$05x"; + args_disass: "{name(rd)}, {imm:#05x}"; if(rd == 0) raise(0, 2); //TODO: should it be handled as trap? X[rd] <= imm; } // order matters here as C.ADDI16SP overwrites C.LUI vor rd==2 C.LUI {//(RV32) encoding:b011 | imm[17:17] | rd[4:0] | imm[16:12]s | b01; - args_disass: "x%rd$d, 0x%imm$05x"; + args_disass: "{name(rd)}, {imm:#05x}"; if(rd == 0) raise(0, 2); //TODO: should it be handled as trap? if(imm == 0) raise(0, 2); //TODO: should it be handled as trap? X[rd] <= imm; } C.ADDI16SP {//(RV32) encoding:b011 | imm[9:9]s | b00010 | imm[4:4]s | imm[6:6]s | imm[8:7]s | imm[5:5]s | b01; - args_disass: "0x%imm$05x"; + args_disass: "{imm:#05x}"; X[2] <= X[2]s + imm; } C.SRLI {//(RV32 nse) encoding:b100 | b0 | b00 | rs1[2:0] | shamt[4:0] | b01; - args_disass: "x(8+%rs1$d), %shamt$d"; + args_disass: "{name(8+rs1)}, {shamt}"; val rs1_idx[5] <= rs1+8; X[rs1_idx] <= shrl(X[rs1_idx], shamt); } C.SRAI {//(RV32) encoding:b100 | b0 | b01 | rs1[2:0] | shamt[4:0] | b01; - args_disass: "x(8+%rs1$d), %shamt$d"; + args_disass: "{name(8+rs1)}, {shamt}"; val rs1_idx[5] <= rs1+8; X[rs1_idx] <= shra(X[rs1_idx], shamt); } C.ANDI {//(RV32) encoding:b100 | imm[5:5] | b10 | rs1[2:0] | imm[4:0] | b01; - args_disass: "x(8+%rs1$d), 0x%imm$05x"; + args_disass: "{name(8+rs1)}, {imm:#05x}"; val rs1_idx[5] <= rs1 + 8; X[rs1_idx] <= X[rs1_idx] & imm; } C.SUB {//(RV32) encoding:b100 | b0 | b11 | rd[2:0] | b00 | rs2[2:0] | b01; - args_disass: "x(8+%rd$d), x(8+%rs2$d)"; + args_disass: "{name(8+rd)}, {name(8+rs2)}"; val rd_idx[5] <= rd + 8; X[rd_idx] <= X[rd_idx] - X[rs2 + 8]; } C.XOR {//(RV32) encoding:b100 | b0 | b11 | rd[2:0] | b01 | rs2[2:0] | b01; - args_disass: "x(8+%rd$d), x(8+%rs2$d)"; + args_disass: "{name(8+rd)}, {name(8+rs2)}"; val rd_idx[5] <= rd + 8; X[rd_idx] <= X[rd_idx] ^ X[rs2 + 8]; } C.OR {//(RV32) encoding:b100 | b0 | b11 | rd[2:0] | b10 | rs2[2:0] | b01; - args_disass: "x(8+%rd$d), x(8+%rs2$d)"; + args_disass: "{name(8+rd)}, {name(8+rs2)}"; val rd_idx[5] <= rd + 8; X[rd_idx] <= X[rd_idx] | X[rs2 + 8]; } C.AND {//(RV32) encoding:b100 | b0 | b11 | rd[2:0] | b11 | rs2[2:0] | b01; - args_disass: "x(8+%rd$d), x(8+%rs2$d)"; + args_disass: "{name(8+rd)}, {name(8+rs2)}"; val rd_idx[5] <= rd + 8; X[rd_idx] <= X[rd_idx] & X[rs2 + 8]; } C.J(no_cont) {//(RV32) encoding:b101 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01; - args_disass: "0x%imm$05x"; + args_disass: "{imm:#05x}"; PC<=PC's+imm; } C.BEQZ(no_cont,cond) {//(RV32) encoding:b110 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s |imm[2:1]s | imm[5:5]s | b01; - args_disass: "x(8+%rs1$d), 0x%imm$05x"; + args_disass: "{name(8+rs1)}, {imm:#05x}"; PC<=choose(X[rs1+8]==0, PC's+imm, PC+2); } C.BNEZ(no_cont,cond) {//(RV32) encoding:b111 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s | imm[2:1]s | imm[5:5]s | b01; - args_disass: "x(8+%rs1$d), 0x%imm$05x"; + args_disass: "{name(8+rs1)}, {imm:#05x}"; PC<=choose(X[rs1+8]!=0, PC's+imm, PC+2); } C.SLLI {//(RV32) encoding:b000 | b0 | rs1[4:0] | shamt[4:0] | b10; - args_disass: "x%rs1$d, %shamt$d"; + args_disass: "{name(rs1)}, {shamt}"; if(rs1 == 0) raise(0, 2); X[rs1] <= shll(X[rs1], shamt); } C.LWSP {// encoding:b010 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10; - args_disass: "x%rd$d, sp, 0x%uimm$05x"; + args_disass: "{name(rd)}, sp, {uimm:#05x}"; val offs[XLEN] <= X[2] + uimm; X[rd] <= MEM[offs]{32}; } // order matters as C.JR is a special case of C.MV C.MV {//(RV32) encoding:b100 | b0 | rd[4:0] | rs2[4:0] | b10; - args_disass: "x%rd$d, x%rs2$d"; + args_disass: "{name(rd)}, {name(rs2)}"; X[rd] <= X[rs2]; } C.JR(no_cont) {//(RV32) encoding:b100 | b0 | rs1[4:0] | b00000 | b10; - args_disass: "x%rs1$d"; + args_disass: "{name(rs1)}"; PC <= X[rs1]; } // order matters as C.EBREAK is a special case of C.JALR which is a special case of C.ADD C.ADD {//(RV32) encoding:b100 | b1 | rd[4:0] | rs2[4:0] | b10; - args_disass: "x%rd$d, x%rs2$d"; + args_disass: "{name(rd)}, {name(rs2)}"; X[rd] <= X[rd] + X[rs2]; } C.JALR(no_cont) {//(RV32) encoding:b100 | b1 | rs1[4:0] | b00000 | b10; - args_disass: "x%rs1$d"; + args_disass: "{name(rs1)}"; X[1] <= PC+2; PC<=X[rs1]; } @@ -174,7 +174,7 @@ InsructionSet RV32IC { } C.SWSP {// encoding:b110 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10; - args_disass: "x2+0x%uimm$05x, x%rs2$d"; + args_disass: "x2+{uimm:#05x}, {name(rs2)}"; val offs[XLEN] <= X[2] + uimm; MEM[offs]{32} <= X[rs2]; } @@ -199,7 +199,7 @@ InsructionSet RV32FC extends RV32IC{ instructions{ C.FLW { encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00; - args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))"; + args_disass:"f(8+{rd}), {uimm}({name(8+rs1)})"; val offs[XLEN] <= X[rs1+8]+uimm; val res[32] <= MEM[offs]{32}; if(FLEN==32) @@ -211,13 +211,13 @@ InsructionSet RV32FC extends RV32IC{ } C.FSW { encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00; - args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))"; + args_disass:"f(8+{rs2}), {uimm}({name(8+rs1)})"; val offs[XLEN] <= X[rs1+8]+uimm; MEM[offs]{32}<=F[rs2+8]{32}; } C.FLWSP { encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10; - args_disass:"f%rd$d, %uimm%(x2)"; + args_disass:"f{rd}, {uimm}(x2)"; val offs[XLEN] <= X[2]+uimm; val res[32] <= MEM[offs]{32}; if(FLEN==32) @@ -229,7 +229,7 @@ InsructionSet RV32FC extends RV32IC{ } C.FSWSP { encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10; - args_disass:"f%rs2$d, %uimm%(x2), "; + args_disass:"f{rs2}, {uimm}(x2), "; val offs[XLEN] <= X[2]+uimm; MEM[offs]{32}<=F[rs2]{32}; } @@ -250,7 +250,7 @@ InsructionSet RV32DC extends RV32IC{ instructions{ C.FLD { //(RV32/64) encoding: b001 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00; - args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))"; + args_disass:"f(8+{rd}), {uimm}({name(8+rs1)})"; val offs[XLEN] <= X[rs1+8]+uimm; val res[64] <= MEM[offs]{64}; if(FLEN==64) @@ -262,13 +262,13 @@ InsructionSet RV32DC extends RV32IC{ } C.FSD { //(RV32/64) encoding: b101 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00; - args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))"; + args_disass:"f(8+{rs2}), {uimm}({name(8+rs1)})"; val offs[XLEN] <= X[rs1+8]+uimm; MEM[offs]{64}<=F[rs2+8]{64}; } C.FLDSP {//(RV32/64) encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10; - args_disass:"f%rd$d, %uimm%(x2)"; + args_disass:"f{rd}, {uimm}(x2)"; val offs[XLEN] <= X[2]+uimm; val res[64] <= MEM[offs]{64}; if(FLEN==64) @@ -280,7 +280,7 @@ InsructionSet RV32DC extends RV32IC{ } C.FSDSP {//(RV32/64) encoding:b101 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10; - args_disass:"f%rs2$d, %uimm%(x2), "; + args_disass:"f{rs2}, {uimm}(x2), "; val offs[XLEN] <= X[2]+uimm; MEM[offs]{64}<=F[rs2]{64}; } @@ -307,11 +307,11 @@ InsructionSet RV64IC extends RV32IC { } C.SUBW {//(RV64/128, RV32 res) encoding:b100 | b1 | b11 | rd[2:0] | b00 | rs2[2:0] | b01; - args_disass: "x%rd$d, sp, 0x%imm$05x"; + args_disass: "{name(rd)}, sp, {imm:#05x}"; } C.ADDW {//(RV64/128 RV32 res) encoding:b100 | b1 | b11 | rd[2:0] | b01 | rs2[2:0] | b01; - args_disass: "x%rd$d, sp, 0x%imm$05x"; + args_disass: "{name(rd)}, sp, {imm:#05x}"; } C.ADDIW {//(RV64/128) encoding:b001 | imm[5:5] | rs1[4:0] | imm[4:0] | b01; @@ -327,7 +327,7 @@ InsructionSet RV64IC extends RV32IC { } C.LDSP {//(RV64/128 encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10; - args_disass: "x%rd$d, sp, 0x%imm$05x"; + args_disass: "{name(rd)}, sp, {imm:#05x}"; } C.SDSP {//(RV64/128) encoding:b111 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10; diff --git a/riscv/gen_input/RV32D.core_desc b/riscv/gen_input/RV32D.core_desc index caefac5..4b579b7 100644 --- a/riscv/gen_input/RV32D.core_desc +++ b/riscv/gen_input/RV32D.core_desc @@ -10,7 +10,7 @@ InsructionSet RV32D extends RV32IBase{ instructions{ FLD { encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000111; - args_disass:"f%rd$d, %imm%(x%rs1$d)"; + args_disass:"f{rd}, {imm}({rs1})"; val offs[XLEN] <= X[rs1]'s + imm; val res[64] <= MEM[offs]{64}; if(FLEN==64) @@ -22,13 +22,13 @@ InsructionSet RV32D extends RV32IBase{ } FSD { encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100111; - args_disass:"f%rs2$d, %imm%(x%rs1$d)"; + args_disass:"f{rs2}, {imm}({rs1})"; val offs[XLEN] <= X[rs1]'s + imm; MEM[offs]{64}<=F[rs2]{64}; } FMADD.D { encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}"; //F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f; val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(0, 64), choose(rm<7, rm{8}, FCSR{8})); if(FLEN==64) @@ -42,7 +42,7 @@ InsructionSet RV32D extends RV32IBase{ } FMSUB.D { encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}"; //F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f; val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8})); if(FLEN==64) @@ -56,7 +56,7 @@ InsructionSet RV32D extends RV32IBase{ } FNMADD.D { encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}"; //F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f; val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8})); if(FLEN==64) @@ -70,7 +70,7 @@ InsructionSet RV32D extends RV32IBase{ } FNMSUB.D { encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}"; //F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f; val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8})); if(FLEN==64) @@ -84,7 +84,7 @@ InsructionSet RV32D extends RV32IBase{ } FADD.D { encoding: b0000001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"{name(rd)}, f{rs1}, f{rs2}"; // F[rd]f <= F[rs1]f + F[rs2]f; val res[64] <= fdispatch_fadd_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8})); if(FLEN==64) @@ -98,7 +98,7 @@ InsructionSet RV32D extends RV32IBase{ } FSUB.D { encoding: b0000101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"{name(rd)}, f{rs1}, f{rs2}"; // F[rd]f <= F[rs1]f - F[rs2]f; val res[64] <= fdispatch_fsub_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8})); if(FLEN==64) @@ -112,7 +112,7 @@ InsructionSet RV32D extends RV32IBase{ } FMUL.D { encoding: b0001001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"{name(rd)}, f{rs1}, f{rs2}"; // F[rd]f <= F[rs1]f * F[rs2]f; val res[64] <= fdispatch_fmul_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8})); if(FLEN==64) @@ -126,7 +126,7 @@ InsructionSet RV32D extends RV32IBase{ } FDIV.D { encoding: b0001101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"{name(rd)}, f{rs1}, f{rs2}"; // F[rd]f <= F[rs1]f / F[rs2]f; val res[64] <= fdispatch_fdiv_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8})); if(FLEN==64) @@ -140,7 +140,7 @@ InsructionSet RV32D extends RV32IBase{ } FSQRT.D { encoding: b0101101 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; + args_disass:"{name(rd)}, f{rs1}"; //F[rd]f<=sqrt(F[rs1]f); val res[64] <= fdispatch_fsqrt_d(F[rs1]{64}, choose(rm<7, rm{8}, FCSR{8})); if(FLEN==64) @@ -154,7 +154,7 @@ InsructionSet RV32D extends RV32IBase{ } FSGNJ.D { encoding: b0010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"f{rd}, f{rs1}, f{rs2}"; val res[64] <= (F[rs1]{64} & 0x7fffffff) | (F[rs2]{64} & 0x80000000); if(FLEN==64) F[rd] <= res; @@ -165,7 +165,7 @@ InsructionSet RV32D extends RV32IBase{ } FSGNJN.D { encoding: b0010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"f{rd}, f{rs1}, f{rs2}"; val res[64] <= (F[rs1]{64} & 0x7fffffff) | (~F[rs2]{64} & 0x80000000); if(FLEN==64) F[rd] <= res; @@ -176,7 +176,7 @@ InsructionSet RV32D extends RV32IBase{ } FSGNJX.D { encoding: b0010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"f{rd}, f{rs1}, f{rs2}"; val res[64] <= F[rs1]{64} ^ (F[rs2]{64} & 0x80000000); if(FLEN==64) F[rd] <= res; @@ -187,7 +187,7 @@ InsructionSet RV32D extends RV32IBase{ } FMIN.D { encoding: b0010101 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"f{rd}, f{rs1}, f{rs2}"; //F[rd]f<= choose(F[rs1]fF[rs2]f, F[rs1]f, F[rs2]f); val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32)); if(FLEN==64) @@ -215,7 +215,7 @@ InsructionSet RV32D extends RV32IBase{ } FCVT.S.D { encoding: b0100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d"; + args_disass:"f{rd}, f{rs1}"; val res[32] <= fdispatch_fconv_d2f(F[rs1], rm{8}); // NaN boxing val upper[FLEN] <= -1; @@ -223,7 +223,7 @@ InsructionSet RV32D extends RV32IBase{ } FCVT.D.S { encoding: b0100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d"; + args_disass:"f{rd}, f{rs1}"; val res[64] <= fdispatch_fconv_f2d(F[rs1]{32}, rm{8}); if(FLEN==64){ F[rd] <= res; @@ -234,47 +234,47 @@ InsructionSet RV32D extends RV32IBase{ } FEQ.D { encoding: b1010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"{name(rd)}, f{rs1}, f{rs2}"; X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32)); val flags[32] <= fdispatch_fget_flags(); FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; } FLT.D { encoding: b1010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"{name(rd)}, f{rs1}, f{rs2}"; X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(2, 32)); val flags[32] <= fdispatch_fget_flags(); FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; } FLE.D { encoding: b1010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"{name(rd)}, f{rs1}, f{rs2}"; X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32)); val flags[32] <= fdispatch_fget_flags(); FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; } FCLASS.D { encoding: b1110001 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; + args_disass:"{name(rd)}, f{rs1}"; X[rd]<=fdispatch_fclass_d(F[rs1]{64}); } FCVT.W.D { encoding: b1100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; + args_disass:"{name(rd)}, f{rs1}"; X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(0, 32), rm{8}), XLEN); val flags[32] <= fdispatch_fget_flags(); FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; } FCVT.WU.D { encoding: b1100001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; + args_disass:"{name(rd)}, f{rs1}"; X[rd]<= zext(fdispatch_fcvt_d(F[rs1]{64}, zext(1, 32), rm{8}), XLEN); val flags[32] <= fdispatch_fget_flags(); FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; } FCVT.D.W { encoding: b1101001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, x%rs1$d"; + args_disass:"f{rd}, {rs1}"; val res[64] <= fdispatch_fcvt_d(sext(X[rs1],64), zext(2, 32), rm{8}); if(FLEN==64) F[rd] <= res; @@ -285,7 +285,7 @@ InsructionSet RV32D extends RV32IBase{ } FCVT.D.WU { encoding: b1101001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, x%rs1$d"; + args_disass:"f{rd}, {rs1}"; val res[64] <=fdispatch_fcvt_d(zext(X[rs1],64), zext(3,32), rm{8}); if(FLEN==64) F[rd] <= res; diff --git a/riscv/gen_input/RV32F.core_desc b/riscv/gen_input/RV32F.core_desc index 1fc02b2..5723a4f 100644 --- a/riscv/gen_input/RV32F.core_desc +++ b/riscv/gen_input/RV32F.core_desc @@ -10,7 +10,7 @@ InsructionSet RV32F extends RV32IBase{ instructions{ FLW { encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111; - args_disass:"f%rd$d, %imm%(x%rs1$d)"; + args_disass:"f{rd}, {imm}(x{rs1})"; val offs[XLEN] <= X[rs1]'s + imm; val res[32] <= MEM[offs]{32}; if(FLEN==32) @@ -22,13 +22,13 @@ InsructionSet RV32F extends RV32IBase{ } FSW { encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111; - args_disass:"f%rs2$d, %imm%(x%rs1$d)"; + args_disass:"f{rs2}, {imm}(x{rs1})"; val offs[XLEN] <= X[rs1]'s + imm; MEM[offs]{32}<=F[rs2]{32}; } FMADD.S { encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}"; //F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f; val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(0, 32), choose(rm<7, rm{8}, FCSR{8})); if(FLEN==32) @@ -42,7 +42,7 @@ InsructionSet RV32F extends RV32IBase{ } FMSUB.S { encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}"; //F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f; val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8})); if(FLEN==32) @@ -56,7 +56,7 @@ InsructionSet RV32F extends RV32IBase{ } FNMADD.S { encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}"; //F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f; val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8})); if(FLEN==32) @@ -70,7 +70,7 @@ InsructionSet RV32F extends RV32IBase{ } FNMSUB.S { encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}"; //F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f; val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8})); if(FLEN==32) @@ -84,7 +84,7 @@ InsructionSet RV32F extends RV32IBase{ } FADD.S { encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"f{rd}, f{rs1}, f{rs2}"; // F[rd]f <= F[rs1]f + F[rs2]f; val res[32] <= fdispatch_fadd_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8})); if(FLEN==32) @@ -98,7 +98,7 @@ InsructionSet RV32F extends RV32IBase{ } FSUB.S { encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"f{rd}, f{rs1}, f{rs2}"; // F[rd]f <= F[rs1]f - F[rs2]f; val res[32] <= fdispatch_fsub_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8})); if(FLEN==32) @@ -112,7 +112,7 @@ InsructionSet RV32F extends RV32IBase{ } FMUL.S { encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"f{rd}, f{rs1}, f{rs2}"; // F[rd]f <= F[rs1]f * F[rs2]f; val res[32] <= fdispatch_fmul_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8})); if(FLEN==32) @@ -126,7 +126,7 @@ InsructionSet RV32F extends RV32IBase{ } FDIV.S { encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"f{rd}, f{rs1}, f{rs2}"; // F[rd]f <= F[rs1]f / F[rs2]f; val res[32] <= fdispatch_fdiv_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8})); if(FLEN==32) @@ -140,7 +140,7 @@ InsructionSet RV32F extends RV32IBase{ } FSQRT.S { encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d"; + args_disass:"f{rd}, f{rs1}"; //F[rd]f<=sqrt(F[rs1]f); val res[32] <= fdispatch_fsqrt_s(F[rs1]{32}, choose(rm<7, rm{8}, FCSR{8})); if(FLEN==32) @@ -154,7 +154,7 @@ InsructionSet RV32F extends RV32IBase{ } FSGNJ.S { encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"f{rd}, f{rs1}, f{rs2}"; val res[32] <= (F[rs1]{32} & 0x7fffffff) | (F[rs2]{32} & 0x80000000); if(FLEN==32) F[rd] <= res; @@ -165,7 +165,7 @@ InsructionSet RV32F extends RV32IBase{ } FSGNJN.S { encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"f{rd}, f{rs1}, f{rs2}"; val res[32] <= (F[rs1]{32} & 0x7fffffff) | (~F[rs2]{32} & 0x80000000); if(FLEN==32) F[rd] <= res; @@ -176,7 +176,7 @@ InsructionSet RV32F extends RV32IBase{ } FSGNJX.S { encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"f{rd}, f{rs1}, f{rs2}"; val res[32] <= F[rs1]{32} ^ (F[rs2]{32} & 0x80000000); if(FLEN==32) F[rd] <= res; @@ -187,7 +187,7 @@ InsructionSet RV32F extends RV32IBase{ } FMIN.S { encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"f{rd}, f{rs1}, f{rs2}"; //F[rd]f<= choose(F[rs1]fF[rs2]f, F[rs1]f, F[rs2]f); val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32)); if(FLEN==32) @@ -215,47 +215,47 @@ InsructionSet RV32F extends RV32IBase{ } FCVT.W.S { encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; + args_disass:"x{rd}, f{rs1}"; X[rd]<= sext(fdispatch_fcvt_s(F[rs1]{32}, zext(0, 32), rm{8}), XLEN); val flags[32] <= fdispatch_fget_flags(); FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; } FCVT.WU.S { encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; + args_disass:"x{rd}, f{rs1}"; X[rd]<= zext(fdispatch_fcvt_s(F[rs1]{32}, zext(1, 32), rm{8}), XLEN); val flags[32] <= fdispatch_fget_flags(); FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; } FEQ.S { encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"x{rd}, f{rs1}, f{rs2}"; X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32)); val flags[32] <= fdispatch_fget_flags(); FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; } FLT.S { encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"x{rd}, f{rs1}, f{rs2}"; X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32)); val flags[32] <= fdispatch_fget_flags(); FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; } FLE.S { encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + args_disass:"x{rd}, f{rs1}, f{rs2}"; X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32)); val flags[32] <= fdispatch_fget_flags(); FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; } FCLASS.S { encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; + args_disass:"x{rd}, f{rs1}"; X[rd]<=fdispatch_fclass_s(F[rs1]{32}); } FCVT.S.W { encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, x%rs1$d"; + args_disass:"f{rd}, x{rs1}"; val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8}); if(FLEN==32) F[rd] <= res; @@ -266,7 +266,7 @@ InsructionSet RV32F extends RV32IBase{ } FCVT.S.WU { encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, x%rs1$d"; + args_disass:"f{rd}, x{rs1}"; val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8}); if(FLEN==32) F[rd] <= res; @@ -277,12 +277,12 @@ InsructionSet RV32F extends RV32IBase{ } FMV.X.W { encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; + args_disass:"x{rd}, f{rs1}"; X[rd]<=sext(F[rs1]{32}); } FMV.W.X { encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"f%rd$d, x%rs1$d"; + args_disass:"f{rd}, x{rs1}"; if(FLEN==32) F[rd] <= X[rs1]; else { // NaN boxing diff --git a/riscv/gen_input/RV32IBase.core_desc b/riscv/gen_input/RV32IBase.core_desc index 123e1d1..b93351c 100644 --- a/riscv/gen_input/RV32IBase.core_desc +++ b/riscv/gen_input/RV32IBase.core_desc @@ -14,29 +14,60 @@ InsructionSet RV32IBase { registers { [31:0] X[XLEN], PC[XLEN](is_pc), - alias ZERO[XLEN] is X[0] + alias ZERO[XLEN] is X[0], + alias RA[XLEN] is X[1], + alias SP[XLEN] is X[2], + alias GP[XLEN] is X[3], + alias TP[XLEN] is X[4], + alias T0[XLEN] is X[5], + alias T1[XLEN] is X[6], + alias T2[XLEN] is X[7], + alias S0[XLEN] is X[8], + alias S1[XLEN] is X[9], + alias A0[XLEN] is X[10], + alias A1[XLEN] is X[11], + alias A2[XLEN] is X[12], + alias A3[XLEN] is X[13], + alias A4[XLEN] is X[14], + alias A5[XLEN] is X[15], + alias A6[XLEN] is X[16], + alias A7[XLEN] is X[17], + alias S2[XLEN] is X[18], + alias S3[XLEN] is X[19], + alias S4[XLEN] is X[20], + alias S5[XLEN] is X[21], + alias S6[XLEN] is X[22], + alias S7[XLEN] is X[23], + alias S8[XLEN] is X[24], + alias S9[XLEN] is X[25], + alias S10[XLEN] is X[26], + alias S11[XLEN] is X[27], + alias T3[XLEN] is X[28], + alias T4[XLEN] is X[29], + alias T5[XLEN] is X[30], + alias T6[XLEN] is X[31] } instructions { LUI{ encoding: imm[31:12]s | rd[4:0] | b0110111; - args_disass: "x%rd$d, 0x%imm$05x"; + args_disass: "{name(rd)}, {imm:#05x}"; if(rd!=0) X[rd] <= imm; } AUIPC{ encoding: imm[31:12]s | rd[4:0] | b0010111; - args_disass: "x%rd%, 0x%imm$08x"; + args_disass: "{name(rd)}, {imm:#08x}"; if(rd!=0) X[rd] <= PC's+imm; } JAL(no_cont){ encoding: imm[20:20]s | imm[10:1]s | imm[11:11]s | imm[19:12]s | rd[4:0] | b1101111; - args_disass: "x%rd$d, 0x%imm$x"; + args_disass: "{name(rd)}, {imm:#0x}"; if(rd!=0) X[rd] <= PC+4; PC<=PC's+imm; } JALR(no_cont){ encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111; - args_disass: "x%rd$d, x%rs1$d, 0x%imm$x"; + args_disass: "{name(rd)}, {name(rs1)}, {imm:#0x}"; val new_pc[XLEN] <= X[rs1]'s+ imm; val align[XLEN] <= new_pc & 0x2; if(align != 0){ @@ -48,116 +79,116 @@ InsructionSet RV32IBase { } BEQ(no_cont,cond){ encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011; - args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x"; + args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}"; PC<=choose(X[rs1]==X[rs2], PC's+imm, PC+4); } BNE(no_cont,cond){ encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011; - args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x"; + args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}"; PC<=choose(X[rs1]!=X[rs2], PC's+imm, PC+4); } BLT(no_cont,cond){ encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011; - args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x"; + args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}"; PC<=choose(X[rs1]s=X[rs2]s, PC's+imm, PC+4); } BLTU(no_cont,cond) { encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011; - args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x"; + args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}"; PC<=choose(X[rs1]=X[rs2], PC's+imm, PC+4); } LB { encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; + args_disass:"{name(rd)}, {imm}({name(rs1)})"; val offs[XLEN] <= X[rs1]'s+imm; if(rd!=0) X[rd]<=sext(MEM[offs]); } LH { encoding: imm[11:0]s | rs1[4:0] | b001 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; + args_disass:"{name(rd)}, {imm}({name(rs1)})"; val offs[XLEN] <= X[rs1]'s+imm; if(rd!=0) X[rd]<=sext(MEM[offs]{16}); } LW { encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; + args_disass:"{name(rd)}, {imm}({name(rs1)})"; val offs[XLEN] <= X[rs1]'s+imm; if(rd!=0) X[rd]<=sext(MEM[offs]{32}); } LBU { encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; + args_disass:"{name(rd)}, {imm}({name(rs1)})"; val offs[XLEN] <= X[rs1]'s+imm; if(rd!=0) X[rd]<=zext(MEM[offs]); } LHU { encoding: imm[11:0]s | rs1[4:0] | b101 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; + args_disass:"{name(rd)}, {imm}({name(rs1)})"; val offs[XLEN] <= X[rs1]'s+imm; if(rd!=0) X[rd]<=zext(MEM[offs]{16}); } SB { encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:0]s | b0100011; - args_disass:"x%rs2$d, %imm%(x%rs1$d)"; + args_disass:"{name(rs2)}, {imm}({name(rs1)})"; val offs[XLEN] <= X[rs1]'s + imm; MEM[offs] <= X[rs2]; } SH { encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:0]s | b0100011; - args_disass:"x%rs2$d, %imm%(x%rs1$d)"; + args_disass:"{name(rs2)}, {imm}({name(rs1)})"; val offs[XLEN] <= X[rs1]'s + imm; MEM[offs]{16} <= X[rs2]; } SW { encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100011; - args_disass:"x%rs2$d, %imm%(x%rs1$d)"; + args_disass:"{name(rs2)}, {imm}({name(rs1)})"; val offs[XLEN] <= X[rs1]'s + imm; MEM[offs]{32} <= X[rs2]; } ADDI { encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; + args_disass:"{name(rd)}, {name(rs1)}, {imm}"; if(rd != 0) X[rd] <= X[rs1]'s + imm; } SLTI { encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; + args_disass:"{name(rd)}, {name(rs1)}, {imm}"; if (rd != 0) X[rd] <= choose(X[rs1]s < imm's, 1, 0); } SLTIU { encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; + args_disass:"{name(rd)}, {name(rs1)}, {imm}"; val full_imm[XLEN] <= imm's; if (rd != 0) X[rd] <= choose(X[rs1]'u < full_imm'u, 1, 0); } XORI { encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; + args_disass:"{name(rd)}, {name(rs1)}, {imm}"; if(rd != 0) X[rd] <= X[rs1]s ^ imm; } ORI { encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; + args_disass:"{name(rd)}, {name(rs1)}, {imm}"; if(rd != 0) X[rd] <= X[rs1]s | imm; } ANDI { encoding: imm[11:0]s | rs1[4:0] | b111 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; + args_disass:"{name(rd)}, {name(rs1)}, {imm}"; if(rd != 0) X[rd] <= X[rs1]s & imm; } SLLI { encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; + args_disass:"{name(rd)}, {name(rs1)}, {shamt}"; if(shamt > 31){ raise(0,0); } else { @@ -166,7 +197,7 @@ InsructionSet RV32IBase { } SRLI { encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; + args_disass:"{name(rd)}, {name(rs1)}, {shamt}"; if(shamt > 31){ raise(0,0); } else { @@ -175,7 +206,7 @@ InsructionSet RV32IBase { } SRAI { encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; + args_disass:"{name(rd)}, {name(rs1)}, {shamt}"; if(shamt > 31){ raise(0,0); } else { @@ -184,52 +215,52 @@ InsructionSet RV32IBase { } ADD { encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0) X[rd] <= X[rs1] + X[rs2]; } SUB { encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0) X[rd] <= X[rs1] - X[rs2]; } SLL { encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0) X[rd] <= shll(X[rs1], X[rs2]&(XLEN-1)); } SLT { encoding: b0000000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if (rd != 0) X[rd] <= choose(X[rs1]s < X[rs2]s, 1, 0); } SLTU { encoding: b0000000 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if (rd != 0) X[rd] <= choose(zext(X[rs1]) < zext(X[rs2]), 1, 0); } XOR { encoding: b0000000 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0) X[rd] <= X[rs1] ^ X[rs2]; } SRL { encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0) X[rd] <= shrl(X[rs1], X[rs2]&(XLEN-1)); } SRA { encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0) X[rd] <= shra(X[rs1], X[rs2]&(XLEN-1)); } OR { encoding: b0000000 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0) X[rd] <= X[rs1] | X[rs2]; } AND { encoding: b0000000 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0) X[rd] <= X[rs1] & X[rs2]; } FENCE { @@ -271,7 +302,7 @@ InsructionSet RV32IBase { } CSRRW { encoding: csr[11:0] | rs1[4:0] | b001 | rd[4:0] | b1110011; - args_disass:"x%rd$d, %csr$d, x%rs1$d"; + args_disass:"{name(rd)}, {csr}, {name(rs1)}"; val rs_val[XLEN] <= X[rs1]; if(rd!=0){ val csr_val[XLEN] <= CSR[csr]; @@ -284,7 +315,7 @@ InsructionSet RV32IBase { } CSRRS { encoding: csr[11:0] | rs1[4:0] | b010 | rd[4:0] | b1110011; - args_disass:"x%rd$d, %csr$d, x%rs1$d"; + args_disass:"{name(rd)}, {csr}, {name(rs1)}"; val xrd[XLEN] <= CSR[csr]; val xrs1[XLEN] <= X[rs1]; if(rd!=0) X[rd] <= xrd; @@ -292,7 +323,7 @@ InsructionSet RV32IBase { } CSRRC { encoding: csr[11:0] | rs1[4:0] | b011 | rd[4:0] | b1110011; - args_disass:"x%rd$d, %csr$d, x%rs1$d"; + args_disass:"{name(rd)}, {csr}, {name(rs1)}"; val xrd[XLEN] <= CSR[csr]; val xrs1[XLEN] <= X[rs1]; if(rd!=0) X[rd] <= xrd; @@ -300,13 +331,13 @@ InsructionSet RV32IBase { } CSRRWI { encoding: csr[11:0] | zimm[4:0] | b101 | rd[4:0] | b1110011; - args_disass:"x%rd$d, %csr$d, 0x%zimm$x"; + args_disass:"{name(rd)}, {csr}, {zimm:#0x}"; if(rd!=0) X[rd] <= CSR[csr]; CSR[csr] <= zext(zimm); } CSRRSI { encoding: csr[11:0] | zimm[4:0] | b110 | rd[4:0] | b1110011; - args_disass:"x%rd$d, %csr$d, 0x%zimm$x"; + args_disass:"{name(rd)}, {csr}, {zimm:#0x}"; val res[XLEN] <= CSR[csr]; if(zimm!=0) CSR[csr] <= res | zext(zimm); // make sure rd is written after csr write succeeds @@ -314,7 +345,7 @@ InsructionSet RV32IBase { } CSRRCI { encoding: csr[11:0] | zimm[4:0] | b111 | rd[4:0] | b1110011; - args_disass:"x%rd$d, %csr$d, 0x%zimm$x"; + args_disass:"{name(rd)}, {csr}, {zimm:#0x}"; val res[XLEN] <= CSR[csr]; if(rd!=0) X[rd] <= res; if(zimm!=0) CSR[csr] <= res & ~zext(zimm, XLEN); diff --git a/riscv/gen_input/RV32M.core_desc b/riscv/gen_input/RV32M.core_desc index a115295..c1c456c 100644 --- a/riscv/gen_input/RV32M.core_desc +++ b/riscv/gen_input/RV32M.core_desc @@ -7,7 +7,7 @@ InsructionSet RV32M extends RV32IBase { instructions{ MUL{ encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN); X[rd]<= zext(res , XLEN); @@ -15,7 +15,7 @@ InsructionSet RV32M extends RV32IBase { } MULH { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN); X[rd]<= zext(res >> XLEN, XLEN); @@ -23,7 +23,7 @@ InsructionSet RV32M extends RV32IBase { } MULHSU { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ val res[MAXLEN] <= sext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN); X[rd]<= zext(res >> XLEN, XLEN); @@ -31,7 +31,7 @@ InsructionSet RV32M extends RV32IBase { } MULHU { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN); X[rd]<= zext(res >> XLEN, XLEN); @@ -39,7 +39,7 @@ InsructionSet RV32M extends RV32IBase { } DIV { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ if(X[rs2]!=0){ val M1[XLEN] <= -1; @@ -57,7 +57,7 @@ InsructionSet RV32M extends RV32IBase { } DIVU { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ if(X[rs2]!=0) X[rd] <= zext(X[rs1], 32) / zext(X[rs2], 32); @@ -67,7 +67,7 @@ InsructionSet RV32M extends RV32IBase { } REM { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ if(X[rs2]!=0) { val M1[XLEN] <= -1; @@ -85,7 +85,7 @@ InsructionSet RV32M extends RV32IBase { } REMU { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ if(X[rs2]!=0) X[rd] <= zext(X[rs1], 32) % zext(X[rs2], 32); diff --git a/riscv/gen_input/RV64A.core_desc b/riscv/gen_input/RV64A.core_desc index 5080d11..c95f7d2 100644 --- a/riscv/gen_input/RV64A.core_desc +++ b/riscv/gen_input/RV64A.core_desc @@ -10,7 +10,7 @@ InsructionSet RV64A extends RV64IBase { instructions{ LR.D { encoding: b00010 | aq[0:0] | rl[0:0] | b00000 | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d"; + args_disass: "{name(rd)}, {name(rs1)}"; if(rd!=0){ val offs[XLEN] <= X[rs1]; X[rd]<= sext(MEM[offs]{64}, XLEN); @@ -19,7 +19,7 @@ InsructionSet RV64A extends RV64IBase { } SC.D { encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)}"; val offs[XLEN] <= X[rs1]; val res[64] <= RES[offs]; if(res!=0){ @@ -31,14 +31,14 @@ InsructionSet RV64A extends RV64IBase { } AMOSWAP.D{ encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN] <= X[rs1]; if(rd!=0) X[rd] <= sext(MEM[offs]{64}); MEM[offs]{64} <= X[rs2]; } AMOADD.D{ encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN] <= X[rs1]; val res[XLEN] <= sext(MEM[offs]{64}); if(rd!=0) X[rd]<=res; @@ -47,7 +47,7 @@ InsructionSet RV64A extends RV64IBase { } AMOXOR.D{ encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN] <= X[rs1]; val res[XLEN] <= sext(MEM[offs]{64}); if(rd!=0) X[rd] <= res; @@ -56,7 +56,7 @@ InsructionSet RV64A extends RV64IBase { } AMOAND.D{ encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN] <= X[rs1]; val res[XLEN] <= sext(MEM[offs]{64}); if(rd!=0) X[rd] <= res; @@ -65,7 +65,7 @@ InsructionSet RV64A extends RV64IBase { } AMOOR.D { encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN] <= X[rs1]; val res[XLEN] <= sext(MEM[offs]{64}); if(rd!=0) X[rd] <= res; @@ -74,7 +74,7 @@ InsructionSet RV64A extends RV64IBase { } AMOMIN.D{ encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN] <= X[rs1]; val res[XLEN] <= sext(MEM[offs]{64}); if(rd!=0) X[rd] <= res; @@ -83,7 +83,7 @@ InsructionSet RV64A extends RV64IBase { } AMOMAX.D{ encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN] <= X[rs1]; val res[XLEN] <= sext(MEM[offs]{64}); if(rd!=0) X[rd] <= res; @@ -92,7 +92,7 @@ InsructionSet RV64A extends RV64IBase { } AMOMINU.D{ encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN] <= X[rs1]; val res[XLEN] <= zext(MEM[offs]{64}); if(rd!=0) X[rd] <= res; @@ -101,7 +101,7 @@ InsructionSet RV64A extends RV64IBase { } AMOMAXU.D{ encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})"; val offs[XLEN] <= X[rs1]; val res[XLEN] <= zext(MEM[offs]{64}); if(rd!=0) X[rd] <= res; diff --git a/riscv/gen_input/RV64IBase.core_desc b/riscv/gen_input/RV64IBase.core_desc index e44f754..45c2242 100644 --- a/riscv/gen_input/RV64IBase.core_desc +++ b/riscv/gen_input/RV64IBase.core_desc @@ -4,40 +4,40 @@ InsructionSet RV64IBase extends RV32IBase { instructions{ LWU { // 80000104: 0000ef03 lwu t5,0(ra) encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; + args_disass:"{name(rd)}, {imm}({name(rs1)})"; val offs[XLEN] <= X[rs1]'s+imm; if(rd!=0) X[rd]<=zext(MEM[offs]{32}); } LD{ encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; + args_disass:"{name(rd)}, {imm}({name(rs1)})"; val offs[XLEN] <= X[rs1]'s + imm; if(rd!=0) X[rd]<=sext(MEM[offs]{64}); } SD{ encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100011; - args_disass:"x%rs2$d, %imm%(x%rs1$d)"; + args_disass:"{name(rs2)}, {imm}({name(rs1)})"; val offs[XLEN] <= X[rs1]'s + imm; MEM[offs]{64} <= X[rs2]; } SLLI { encoding: b000000 | shamt[5:0] | rs1[4:0] | b001 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; + args_disass:"{name(rd)}, {name(rs1)}, {shamt}"; if(rd != 0) X[rd] <= shll(X[rs1], shamt); } SRLI { encoding: b000000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; + args_disass:"{name(rd)}, {name(rs1)}, {shamt}"; if(rd != 0) X[rd] <= shrl(X[rs1], shamt); } SRAI { encoding: b010000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; + args_disass:"{name(rd)}, {name(rs1)}, {shamt}"; if(rd != 0) X[rd] <= shra(X[rs1], shamt); } ADDIW { encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0011011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; + args_disass:"{name(rd)}, {name(rs1)}, {imm}"; if(rd != 0){ val res[32] <= X[rs1]{32}'s + imm; X[rd] <= sext(res); @@ -45,7 +45,7 @@ InsructionSet RV64IBase extends RV32IBase { } SLLIW { encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0011011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; + args_disass:"{name(rd)}, {name(rs1)}, {shamt}"; if(rd != 0){ val sh_val[32] <= shll(X[rs1]{32}, shamt); X[rd] <= sext(sh_val); @@ -53,7 +53,7 @@ InsructionSet RV64IBase extends RV32IBase { } SRLIW { encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; + args_disass:"{name(rd)}, {name(rs1)}, {shamt}"; if(rd != 0){ val sh_val[32] <= shrl(X[rs1]{32}, shamt); X[rd] <= sext(sh_val); @@ -61,7 +61,7 @@ InsructionSet RV64IBase extends RV32IBase { } SRAIW { encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; + args_disass:"{name(rd)}, {name(rs1)}, {shamt}"; if(rd != 0){ val sh_val[32] <= shra(X[rs1]{32}, shamt); X[rd] <= sext(sh_val); @@ -83,7 +83,7 @@ InsructionSet RV64IBase extends RV32IBase { } SLLW { encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ val mask[32] <= 0x1f; val count[32] <= X[rs2]{32} & mask; @@ -93,7 +93,7 @@ InsructionSet RV64IBase extends RV32IBase { } SRLW { encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ val mask[32] <= 0x1f; val count[32] <= X[rs2]{32} & mask; @@ -103,7 +103,7 @@ InsructionSet RV64IBase extends RV32IBase { } SRAW { encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ val mask[32] <= 0x1f; val count[32] <= X[rs2]{32} & mask; diff --git a/riscv/gen_input/RV64M.core_desc b/riscv/gen_input/RV64M.core_desc index cb53da9..fa8b210 100644 --- a/riscv/gen_input/RV64M.core_desc +++ b/riscv/gen_input/RV64M.core_desc @@ -4,35 +4,35 @@ InsructionSet RV64M extends RV64IBase { instructions{ MULW{ encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ X[rd]<= X[rs1] * X[rs2]; } } DIVW { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ X[rd] <= X[rs1]s / X[rs2]s; } } DIVUW { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ X[rd] <= X[rs1] / X[rs2]; } } REMW { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ X[rd] <= X[rs1]s % X[rs2]s; } } REMUW { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}"; if(rd != 0){ X[rd] <= X[rs1] % X[rs2]; } diff --git a/riscv/gen_input/templates/incl-CORENAME.h.gtl b/riscv/gen_input/templates/incl-CORENAME.h.gtl index 95052f8..139d39d 100644 --- a/riscv/gen_input/templates/incl-CORENAME.h.gtl +++ b/riscv/gen_input/templates/incl-CORENAME.h.gtl @@ -33,9 +33,44 @@ <% import com.minres.coredsl.coreDsl.Register import com.minres.coredsl.coreDsl.RegisterFile +import com.minres.coredsl.coreDsl.RegisterAlias def getTypeSize(size){ if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8 } +def getOriginalName(reg){ + if( reg.original instanceof RegisterFile) { + if( reg.index != null ) { + return reg.original.name+generator.generateHostCode(reg.index) + } else { + return reg.original.name + } + } else if(reg.original instanceof Register){ + return reg.original.name + } +} +def getRegisterNames(){ + def regNames = [] + allRegs.each { reg -> + if( reg instanceof RegisterFile) { + (reg.range.right..reg.range.left).each{ + regNames+=reg.name.toLowerCase()+it + } + } else if(reg instanceof Register){ + regNames+=reg.name.toLowerCase() + } + } + return regNames +} +def getRegisterAliasNames(){ + def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]} + return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg -> + if( reg instanceof RegisterFile) { + return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() } + } else if(reg instanceof Register){ + regMap[reg.name]?:reg.name.toLowerCase() + } + }.flatten() +} %> #ifndef _${coreDef.name.toUpperCase()}_H_ #define _${coreDef.name.toUpperCase()}_H_ @@ -54,6 +89,12 @@ template <> struct traits<${coreDef.name.toLowerCase()}> { constexpr static char const* const core_type = "${coreDef.name}"; + static constexpr std::array reg_names{ + {"${getRegisterNames().join("\", \"")}"}}; + + static constexpr std::array reg_aliases{ + {"${getRegisterAliasNames().join("\", \"")}"}}; + enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}}; constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0}; @@ -65,7 +106,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> { ${reg.name}${it},<% } } else if(reg instanceof Register){ %> - ${reg.name},<% + ${reg.name},<% } }%> NUM_REGS, @@ -74,7 +115,12 @@ template <> struct traits<${coreDef.name.toLowerCase()}> { PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, - ICOUNT + ICOUNT<% + allRegs.each { reg -> + if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>, + ${reg.name} = ${aliasname}<% + } + }%> }; using reg_t = uint${regDataWidth}_t; @@ -87,16 +133,12 @@ template <> struct traits<${coreDef.name.toLowerCase()}> { using phys_addr_t = iss::typed_addr_t; - static constexpr std::array ${coreDef.name}_reg_size{ + static constexpr std::array reg_bit_widths{ {${regSizes.join(",")}}}; - static constexpr unsigned reg_bit_width(unsigned r) { return ${coreDef.name}_reg_size[r]; } - - static constexpr std::array ${coreDef.name}_reg_byte_offset{ + static constexpr std::array reg_byte_offsets{ {${regOffsets.join(",")}}}; - constexpr static unsigned reg_byte_offset(unsigned r) { return ${coreDef.name}_reg_byte_offset[r]; } - static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); enum sreg_flag_e { FLAGS }; diff --git a/riscv/gen_input/templates/src-CORENAME.cpp.gtl b/riscv/gen_input/templates/src-CORENAME.cpp.gtl index 58d0342..83dd26c 100644 --- a/riscv/gen_input/templates/src-CORENAME.cpp.gtl +++ b/riscv/gen_input/templates/src-CORENAME.cpp.gtl @@ -49,8 +49,8 @@ extern "C" { using namespace iss::arch; -constexpr std::array iss::arch::traits::${coreDef.name}_reg_size; -constexpr std::array iss::arch::traits::${coreDef.name}_reg_byte_offset; +constexpr std::array iss::arch::traits::reg_sizes; +constexpr std::array iss::arch::traits::reg_byte_offset; ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() { reg.icount = 0; diff --git a/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl b/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl index c6f8d37..c989810 100644 --- a/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl +++ b/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl @@ -38,7 +38,7 @@ #include #include -#include +#include #include #include @@ -54,10 +54,11 @@ namespace ${coreDef.name.toLowerCase()} { using namespace iss::arch; using namespace llvm; using namespace iss::debugger; +using namespace iss::vm::llvm; -template class vm_impl : public vm::vm_base { +template class vm_impl : public vm_base { public: - using super = typename vm::vm_base; + using super = typename iss::vm::llvm::vm_base; using virt_addr_t = typename super::virt_addr_t; using phys_addr_t = typename super::phys_addr_t; using code_word_t = typename super::code_word_t; @@ -71,31 +72,32 @@ public: target_adapter_if *accquire_target_adapter(server_if *srv) override { debugger_if::dbg_enabled = true; - if (vm::vm_base::tgt_adapter == nullptr) - vm::vm_base::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); - return vm::vm_base::tgt_adapter; + if (vm_base::tgt_adapter == nullptr) + vm_base::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); + return vm_base::tgt_adapter; } protected: - using vm::vm_base::get_reg_ptr; + using vm_base::get_reg_ptr; - template inline llvm::ConstantInt *size(T type) { - return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits())); + inline const char *name(size_t index){return traits::reg_aliases.at(index);} + + template inline ConstantInt *size(T type) { + return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits())); } - void setup_module(llvm::Module *m) override { + void setup_module(Module* m) override { super::setup_module(m); - vm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE); + iss::vm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE); } - inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal, unsigned size) { + inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) { return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size)); } - std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, - llvm::BasicBlock *) override; + std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override; - void gen_leave_behavior(llvm::BasicBlock *leave_blk) override; + void gen_leave_behavior(BasicBlock *leave_blk) override; void gen_raise_trap(uint16_t trap_id, uint16_t cause); @@ -103,17 +105,17 @@ protected: void gen_wait(unsigned type); - void gen_trap_behavior(llvm::BasicBlock *) override; + void gen_trap_behavior(BasicBlock *) override; - void gen_trap_check(llvm::BasicBlock *bb); + void gen_trap_check(BasicBlock *bb); - inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) { + inline Value *gen_reg_load(unsigned i, unsigned level = 0) { return this->builder.CreateLoad(get_reg_ptr(i), false); } inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) { - llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), - this->get_type(traits::XLEN)); + Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), + this->get_type(traits::XLEN)); this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true); } @@ -124,9 +126,9 @@ protected: enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) }; using this_class = vm_impl; - using compile_func = std::tuple (this_class::*)(virt_addr_t &pc, - code_word_t instr, - llvm::BasicBlock *bb); + using compile_func = std::tuple (this_class::*)(virt_addr_t &pc, + code_word_t instr, + BasicBlock *bb); std::array lut; std::array lut_00, lut_01, lut_10; @@ -192,15 +194,14 @@ private: /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %> /* instruction ${idx}: ${instr.name} */ - std::tuple __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){<%instr.code.eachLine{%> + std::tuple __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){<%instr.code.eachLine{%> ${it}<%}%> } <%}%> /**************************************************************************** * end opcode definitions ****************************************************************************/ - std::tuple illegal_intruction(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { + std::tuple illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) { this->gen_sync(iss::PRE_SYNC, instr_descr.size()); this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits::NEXT_PC), true), get_reg_ptr(traits::PC), true); @@ -212,7 +213,7 @@ private: this->gen_raise_trap(0, 2); // illegal instruction trap this->gen_sync(iss::POST_SYNC, instr_descr.size()); this->gen_trap_check(this->leave_blk); - return std::make_tuple(iss::vm::BRANCH, nullptr); + return std::make_tuple(BRANCH, nullptr); } }; @@ -225,7 +226,7 @@ template vm_impl::vm_impl() { this(new ARCH()); } template vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) -: vm::vm_base(core, core_id, cluster_id) { +: vm_base(core, core_id, cluster_id) { qlut[0] = lut_00.data(); qlut[1] = lut_01.data(); qlut[2] = lut_10.data(); @@ -237,8 +238,8 @@ vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) } template -std::tuple -vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, llvm::BasicBlock *this_block) { +std::tuple +vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) { // we fetch at max 4 byte, alignment is 2 code_word_t insn = 0; const typename traits::addr_t upper_bits = ~traits::PGMASK; @@ -270,7 +271,7 @@ vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, return (this->*f)(pc, insn, this_block); } -template void vm_impl::gen_leave_behavior(llvm::BasicBlock *leave_blk) { +template void vm_impl::gen_leave_behavior(BasicBlock *leave_blk) { this->builder.SetInsertPoint(leave_blk); this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits::NEXT_PC), false)); } @@ -278,45 +279,39 @@ template void vm_impl::gen_leave_behavior(llvm::BasicBlock template void vm_impl::gen_raise_trap(uint16_t trap_id, uint16_t cause) { auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id); this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true); - this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), - get_reg_ptr(traits::LAST_BRANCH), false); + this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); } template void vm_impl::gen_leave_trap(unsigned lvl) { - std::vector args{ - this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)), - }; + std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) }; this->builder.CreateCall(this->mod->getFunction("leave_trap"), args); auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), - get_reg_ptr(traits::LAST_BRANCH), false); + this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); } template void vm_impl::gen_wait(unsigned type) { - std::vector args{ - this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)), - }; + std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) }; this->builder.CreateCall(this->mod->getFunction("wait"), args); } -template void vm_impl::gen_trap_behavior(llvm::BasicBlock *trap_blk) { +template void vm_impl::gen_trap_behavior(BasicBlock *trap_blk) { this->builder.SetInsertPoint(trap_blk); auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits::TRAP_STATE), true); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); - std::vector args{this->core_ptr, this->adj_to64(trap_state_val), - this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits::PC), false))}; + std::vector args{this->core_ptr, this->adj_to64(trap_state_val), + this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits::PC), false))}; this->builder.CreateCall(this->mod->getFunction("enter_trap"), args); auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateRet(trap_addr_val); } -template inline void vm_impl::gen_trap_check(llvm::BasicBlock *bb) { +template inline void vm_impl::gen_trap_check(BasicBlock *bb) { auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits::TRAP_STATE), true); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_EQ, v, - llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))), + ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))), bb, this->trap_blk, 1); } diff --git a/riscv/gen_input/templates/vm_riscv.in.cpp b/riscv/gen_input/templates/vm_riscv.in.cpp deleted file mode 100644 index cead0af..0000000 --- a/riscv/gen_input/templates/vm_riscv.in.cpp +++ /dev/null @@ -1,322 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -namespace iss { -namespace vm { -namespace fp_impl { -void add_fp_functions_2_module(llvm::Module *, unsigned); -} -} - -namespace CORE_DEF_NAME { -using namespace iss::arch; -using namespace llvm; -using namespace iss::debugger; - -template class vm_impl : public vm::vm_base { -public: - using super = typename vm::vm_base; - using virt_addr_t = typename super::virt_addr_t; - using phys_addr_t = typename super::phys_addr_t; - using code_word_t = typename super::code_word_t; - using addr_t = typename super::addr_t; - - vm_impl(); - - vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); - - void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } - - target_adapter_if *accquire_target_adapter(server_if *srv) override { - debugger_if::dbg_enabled = true; - if (vm::vm_base::tgt_adapter == nullptr) - vm::vm_base::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); - return vm::vm_base::tgt_adapter; - } - -protected: - using vm::vm_base::get_reg_ptr; - - template inline llvm::ConstantInt *size(T type) { - return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits())); - } - - void setup_module(llvm::Module *m) override { - super::setup_module(m); - vm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE); - } - - inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal, unsigned size) { - return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size)); - } - - std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, - llvm::BasicBlock *) override; - - void gen_leave_behavior(llvm::BasicBlock *leave_blk) override; - - void gen_raise_trap(uint16_t trap_id, uint16_t cause); - - void gen_leave_trap(unsigned lvl); - - void gen_wait(unsigned type); - - void gen_trap_behavior(llvm::BasicBlock *) override; - - void gen_trap_check(llvm::BasicBlock *bb); - - inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) { - return this->builder.CreateLoad(get_reg_ptr(i), false); - } - - inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) { - llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), - this->get_type(traits::XLEN)); - this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true); - } - - // some compile time constants - // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 }; - enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 }; - enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 }; - enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) }; - - using this_class = vm_impl; - using compile_func = std::tuple (this_class::*)(virt_addr_t &pc, - code_word_t instr, - llvm::BasicBlock *bb); - std::array lut; - - std::array lut_00, lut_01, lut_10; - std::array lut_11; - - std::array qlut; - - std::array lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}}; - - void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[], - compile_func f) { - if (pos < 0) { - lut[idx] = f; - } else { - auto bitmask = 1UL << pos; - if ((mask & bitmask) == 0) { - expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f); - } else { - if ((valid & bitmask) == 0) { - expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f); - expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f); - } else { - auto new_val = idx << 1; - if ((value & bitmask) != 0) new_val++; - expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f); - } - } - } - } - - inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); } - - uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) { - if (pos >= 0) { - auto bitmask = 1UL << pos; - if ((mask & bitmask) == 0) { - lut_val = extract_fields(pos - 1, val, mask, lut_val); - } else { - auto new_val = lut_val << 1; - if ((val & bitmask) != 0) new_val++; - lut_val = extract_fields(pos - 1, val, mask, new_val); - } - } - return lut_val; - } - -private: - /**************************************************************************** - * start opcode definitions - ****************************************************************************/ - struct InstructionDesriptor { - size_t length; - uint32_t value; - uint32_t mask; - compile_func op; - }; - - /* «start generated code» */ - std::array instr_descr = {{}}; - /* «end generated code» */ - /**************************************************************************** - * end opcode definitions - ****************************************************************************/ - std::tuple illegal_intruction(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { - this->gen_sync(iss::PRE_SYNC, instr_descr.size()); - this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits::NEXT_PC), true), - get_reg_ptr(traits::PC), true); - this->builder.CreateStore( - this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits::ICOUNT), true), - this->gen_const(64U, 1)), - get_reg_ptr(traits::ICOUNT), true); - pc = pc + ((instr & 3) == 3 ? 4 : 2); - this->gen_raise_trap(0, 2); // illegal instruction trap - this->gen_sync(iss::POST_SYNC, instr_descr.size()); - this->gen_trap_check(this->leave_blk); - return std::make_tuple(iss::vm::BRANCH, nullptr); - } -}; - -template void debug_fn(CODE_WORD insn) { - volatile CODE_WORD x = insn; - insn = 2 * x; -} - -template vm_impl::vm_impl() { this(new ARCH()); } - -template -vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) -: vm::vm_base(core, core_id, cluster_id) { - qlut[0] = lut_00.data(); - qlut[1] = lut_01.data(); - qlut[2] = lut_10.data(); - qlut[3] = lut_11.data(); - for (auto instr : instr_descr) { - auto quantrant = instr.value & 0x3; - expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op); - } -} - -template -std::tuple -vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, llvm::BasicBlock *this_block) { - // we fetch at max 4 byte, alignment is 2 - code_word_t insn = 0; - const typename traits::addr_t upper_bits = ~traits::PGMASK; - phys_addr_t paddr(pc); - try { - auto *const data = (uint8_t *)&insn; - paddr = this->core.v2p(pc); - if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary - auto res = this->core.read(paddr, 2, data); - if (res != iss::Ok) throw trap_access(1, pc.val); - if ((insn & 0x3) == 0x3) { // this is a 32bit instruction - res = this->core.read(this->core.v2p(pc + 2), 2, data + 2); - } - } else { - auto res = this->core.read(paddr, 4, data); - if (res != iss::Ok) throw trap_access(1, pc.val); - } - } catch (trap_access &ta) { - throw trap_access(ta.id, pc.val); - } - if (insn == 0x0000006f || (insn & 0xffff) == 0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0' - // curr pc on stack - ++inst_cnt; - auto lut_val = extract_fields(insn); - auto f = qlut[insn & 0x3][lut_val]; - if (f == nullptr) { - f = &this_class::illegal_intruction; - } - return (this->*f)(pc, insn, this_block); -} - -template void vm_impl::gen_leave_behavior(llvm::BasicBlock *leave_blk) { - this->builder.SetInsertPoint(leave_blk); - this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits::NEXT_PC), false)); -} - -template void vm_impl::gen_raise_trap(uint16_t trap_id, uint16_t cause) { - auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id); - this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true); - this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), - get_reg_ptr(traits::LAST_BRANCH), false); -} - -template void vm_impl::gen_leave_trap(unsigned lvl) { - std::vector args{ - this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)), - }; - this->builder.CreateCall(this->mod->getFunction("leave_trap"), args); - auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8); - this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), - get_reg_ptr(traits::LAST_BRANCH), false); -} - -template void vm_impl::gen_wait(unsigned type) { - std::vector args{ - this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)), - }; - this->builder.CreateCall(this->mod->getFunction("wait"), args); -} - -template void vm_impl::gen_trap_behavior(llvm::BasicBlock *trap_blk) { - this->builder.SetInsertPoint(trap_blk); - auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits::TRAP_STATE), true); - this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), - get_reg_ptr(traits::LAST_BRANCH), false); - std::vector args{this->core_ptr, this->adj_to64(trap_state_val), - this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits::PC), false))}; - this->builder.CreateCall(this->mod->getFunction("enter_trap"), args); - auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateRet(trap_addr_val); -} - -template inline void vm_impl::gen_trap_check(llvm::BasicBlock *bb) { - auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits::TRAP_STATE), true); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_EQ, v, - llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))), - bb, this->trap_blk, 1); -} - -} // namespace CORE_DEF_NAME - -template <> std::unique_ptr create(arch::CORE_DEF_NAME *core, unsigned short port, bool dump) { - auto ret = new CORE_DEF_NAME::vm_impl(*core, dump); - if (port != 0) debugger::server::run_server(ret, port); - return std::unique_ptr(ret); -} - -} // namespace iss diff --git a/riscv/incl/iss/arch/riscv_hart_msu_vp.h b/riscv/incl/iss/arch/riscv_hart_msu_vp.h index a8a9bab..d6fbc76 100644 --- a/riscv/incl/iss/arch/riscv_hart_msu_vp.h +++ b/riscv/incl/iss/arch/riscv_hart_msu_vp.h @@ -40,6 +40,7 @@ #include "iss/instrumentation_if.h" #include "iss/log_categories.h" #include "iss/vm_if.h" +#include #include #include #include @@ -478,10 +479,8 @@ public: void wait_until(uint64_t flags) override; void disass_output(uint64_t pc, const std::string instr) override { - std::stringstream s; - s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0') - << std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]"; - CLOG(INFO, disass) << "0x" << std::setw(16) << std::setfill('0') << std::hex << pc << "\t\t" << instr << "\t" << s.str(); + CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", + pc, instr, lvl[this->reg.machine_state], (reg_t)state.mstatus, this->reg.icount); }; iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; } diff --git a/riscv/incl/iss/arch/rv32gc.h b/riscv/incl/iss/arch/rv32gc.h index da24040..649a4c5 100644 --- a/riscv/incl/iss/arch/rv32gc.h +++ b/riscv/incl/iss/arch/rv32gc.h @@ -1,53 +1,59 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2017, MINRES Technologies GmbH -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -//////////////////////////////////////////////////////////////////////////////// +/******************************************************************************* + * Copyright (C) 2017, 2018 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + #ifndef _RV32GC_H_ #define _RV32GC_H_ +#include +#include #include #include -#include -#include namespace iss { namespace arch { struct rv32gc; -template<> -struct traits { +template <> struct traits { constexpr static char const* const core_type = "RV32GC"; + static constexpr std::array reg_names{ + {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}}; + + static constexpr std::array reg_aliases{ + {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}}; + enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff}; constexpr static unsigned FP_REGS_SIZE = 64; @@ -125,7 +131,39 @@ struct traits { PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, - ICOUNT + ICOUNT, + ZERO = X0, + RA = X1, + SP = X2, + GP = X3, + TP = X4, + T0 = X5, + T1 = X6, + T2 = X7, + S0 = X8, + S1 = X9, + A0 = X10, + A1 = X11, + A2 = X12, + A3 = X13, + A4 = X14, + A5 = X15, + A6 = X16, + A7 = X17, + S2 = X18, + S3 = X19, + S4 = X20, + S5 = X21, + S6 = X22, + S7 = X23, + S8 = X24, + S9 = X25, + S10 = X26, + S11 = X27, + T3 = X28, + T4 = X29, + T5 = X30, + T6 = X31 }; using reg_t = uint32_t; @@ -138,21 +176,17 @@ struct traits { using phys_addr_t = iss::typed_addr_t; - constexpr static unsigned reg_bit_width(unsigned r) { - constexpr std::array RV32GC_reg_size{{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,32,32,32,64}}; - return RV32GC_reg_size[r]; - } + static constexpr std::array reg_bit_widths{ + {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,32,32,32,64}}; - constexpr static unsigned reg_byte_offset(unsigned r) { - constexpr std::array RV32GC_reg_byte_offset{{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,280,288,296,304,312,320,328,336,344,352,360,368,376,384,392,396,400,404,408,412,416,424}}; - return RV32GC_reg_byte_offset[r]; - } + static constexpr std::array reg_byte_offsets{ + {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,280,288,296,304,312,320,328,336,344,352,360,368,376,384,392,396,400,404,408,412,416,424}}; static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); - enum sreg_flag_e {FLAGS}; + enum sreg_flag_e { FLAGS }; - enum mem_type_e {MEM, CSR, FENCE, RES}; + enum mem_type_e { MEM, CSR, FENCE, RES }; }; struct rv32gc: public arch_if { @@ -177,14 +211,13 @@ struct rv32gc: public arch_if { /// deprecated void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {}; - uint64_t get_icount() { return reg.icount;} + inline uint64_t get_icount() { return reg.icount; } inline bool should_stop() { return interrupt_sim; } inline phys_addr_t v2p(const iss::addr_t& addr){ - if(addr.space != traits::MEM || - addr.type == iss::address_type::PHYSICAL || - addr_mode[static_cast(addr.access)&0x3]==address_type::PHYSICAL){ + if (addr.space != traits::MEM || addr.type == iss::address_type::PHYSICAL || + addr_mode[static_cast(addr.access)&0x3]==address_type::PHYSICAL) { return phys_addr_t(addr.access, addr.space, addr.val&traits::addr_mask); } else return virt2phys(addr); @@ -194,8 +227,7 @@ struct rv32gc: public arch_if { virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - inline - uint32_t get_last_branch(){return reg.last_branch;} + inline uint32_t get_last_branch() { return reg.last_branch; } protected: struct RV32GC_regs { diff --git a/riscv/incl/iss/arch/rv32imac.h b/riscv/incl/iss/arch/rv32imac.h index 74a0183..d187084 100644 --- a/riscv/incl/iss/arch/rv32imac.h +++ b/riscv/incl/iss/arch/rv32imac.h @@ -30,6 +30,7 @@ * *******************************************************************************/ + #ifndef _RV32IMAC_H_ #define _RV32IMAC_H_ @@ -45,15 +46,15 @@ struct rv32imac; template <> struct traits { - constexpr static char const *const core_type = "RV32IMAC"; + constexpr static char const* const core_type = "RV32IMAC"; + + static constexpr std::array reg_names{ + {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}}; + + static constexpr std::array reg_aliases{ + {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}}; - enum constants { - XLEN = 32, - PCLEN = 32, - MISA_VAL = 0b1000000000101000001000100000101, - PGSIZE = 0x1000, - PGMASK = 0xfff - }; + enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000101000001000100000101, PGSIZE=0x1000, PGMASK=0xfff}; constexpr static unsigned FP_REGS_SIZE = 0; @@ -92,35 +93,61 @@ template <> struct traits { X31, PC, NUM_REGS, - NEXT_PC = NUM_REGS, + NEXT_PC=NUM_REGS, TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, - ICOUNT + ICOUNT, + ZERO = X0, + RA = X1, + SP = X2, + GP = X3, + TP = X4, + T0 = X5, + T1 = X6, + T2 = X7, + S0 = X8, + S1 = X9, + A0 = X10, + A1 = X11, + A2 = X12, + A3 = X13, + A4 = X14, + A5 = X15, + A6 = X16, + A7 = X17, + S2 = X18, + S3 = X19, + S4 = X20, + S5 = X21, + S6 = X22, + S7 = X23, + S8 = X24, + S9 = X25, + S10 = X26, + S11 = X27, + T3 = X28, + T4 = X29, + T5 = X30, + T6 = X31 }; using reg_t = uint32_t; using addr_t = uint32_t; - using code_word_t = uint32_t; // TODO: check removal + using code_word_t = uint32_t; //TODO: check removal using virt_addr_t = iss::typed_addr_t; using phys_addr_t = iss::typed_addr_t; - static constexpr std::array RV32IMAC_reg_size{ - {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 64}}; + static constexpr std::array reg_bit_widths{ + {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}}; - constexpr static unsigned reg_bit_width(unsigned r) { return RV32IMAC_reg_size[r]; } - - static constexpr std::array RV32IMAC_reg_byte_offset{ - {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, - 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148, 152, 160}}; - - constexpr static unsigned reg_byte_offset(unsigned r) { return RV32IMAC_reg_byte_offset[r]; } + static constexpr std::array reg_byte_offsets{ + {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,160}}; static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); @@ -129,41 +156,41 @@ template <> struct traits { enum mem_type_e { MEM, CSR, FENCE, RES }; }; -struct rv32imac : public arch_if { +struct rv32imac: public arch_if { using virt_addr_t = typename traits::virt_addr_t; using phys_addr_t = typename traits::phys_addr_t; - using reg_t = typename traits::reg_t; + using reg_t = typename traits::reg_t; using addr_t = typename traits::addr_t; rv32imac(); ~rv32imac(); - void reset(uint64_t address = 0) override; + void reset(uint64_t address=0) override; - uint8_t *get_regs_base_ptr() override; + uint8_t* get_regs_base_ptr() override; /// deprecated - void get_reg(short idx, std::vector &value) override {} - void set_reg(short idx, const std::vector &value) override {} + void get_reg(short idx, std::vector& value) override {} + void set_reg(short idx, const std::vector& value) override {} /// deprecated - bool get_flag(int flag) override { return false; } - void set_flag(int, bool value) override{}; + bool get_flag(int flag) override {return false;} + void set_flag(int, bool value) override {}; /// deprecated - void update_flags(operations op, uint64_t opr1, uint64_t opr2) override{}; + void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {}; inline uint64_t get_icount() { return reg.icount; } inline bool should_stop() { return interrupt_sim; } - inline phys_addr_t v2p(const iss::addr_t &addr) { + inline phys_addr_t v2p(const iss::addr_t& addr){ if (addr.space != traits::MEM || addr.type == iss::address_type::PHYSICAL || - addr_mode[static_cast(addr.access) & 0x3] == address_type::PHYSICAL) { - return phys_addr_t(addr.access, addr.space, addr.val & traits::addr_mask); + addr_mode[static_cast(addr.access)&0x3]==address_type::PHYSICAL) { + return phys_addr_t(addr.access, addr.space, addr.val&traits::addr_mask); } else return virt2phys(addr); } - virtual phys_addr_t virt2phys(const iss::addr_t &addr); + virtual phys_addr_t virt2phys(const iss::addr_t& addr); virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } @@ -210,12 +237,14 @@ protected: } reg; std::array addr_mode; + + bool interrupt_sim=false; - bool interrupt_sim = false; + uint32_t get_fcsr(){return 0;} + void set_fcsr(uint32_t val){} - uint32_t get_fcsr() { return 0; } - void set_fcsr(uint32_t val) {} }; + } -} +} #endif /* _RV32IMAC_H_ */ diff --git a/riscv/incl/iss/arch/rv64ia.h b/riscv/incl/iss/arch/rv64ia.h index be17b06..c14584f 100644 --- a/riscv/incl/iss/arch/rv64ia.h +++ b/riscv/incl/iss/arch/rv64ia.h @@ -1,53 +1,59 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2017, MINRES Technologies GmbH -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -//////////////////////////////////////////////////////////////////////////////// +/******************************************************************************* + * Copyright (C) 2017, 2018 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + #ifndef _RV64IA_H_ #define _RV64IA_H_ +#include +#include #include #include -#include -#include namespace iss { namespace arch { struct rv64ia; -template<> -struct traits { +template <> struct traits { constexpr static char const* const core_type = "RV64IA"; + static constexpr std::array reg_names{ + {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}}; + + static constexpr std::array reg_aliases{ + {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}}; + enum constants {XLEN=64, PCLEN=64, MISA_VAL=0b10000000000001000000000100000001, PGSIZE=0x1000, PGMASK=0xfff}; constexpr static unsigned FP_REGS_SIZE = 0; @@ -92,7 +98,39 @@ struct traits { PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, - ICOUNT + ICOUNT, + ZERO = X0, + RA = X1, + SP = X2, + GP = X3, + TP = X4, + T0 = X5, + T1 = X6, + T2 = X7, + S0 = X8, + S1 = X9, + A0 = X10, + A1 = X11, + A2 = X12, + A3 = X13, + A4 = X14, + A5 = X15, + A6 = X16, + A7 = X17, + S2 = X18, + S3 = X19, + S4 = X20, + S5 = X21, + S6 = X22, + S7 = X23, + S8 = X24, + S9 = X25, + S10 = X26, + S11 = X27, + T3 = X28, + T4 = X29, + T5 = X30, + T6 = X31 }; using reg_t = uint64_t; @@ -105,21 +143,17 @@ struct traits { using phys_addr_t = iss::typed_addr_t; - constexpr static unsigned reg_bit_width(unsigned r) { - constexpr std::array RV64IA_reg_size{{64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,32,64}}; - return RV64IA_reg_size[r]; - } + static constexpr std::array reg_bit_widths{ + {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,32,64}}; - constexpr static unsigned reg_byte_offset(unsigned r) { - constexpr std::array RV64IA_reg_byte_offset{{0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,284,288,296}}; - return RV64IA_reg_byte_offset[r]; - } + static constexpr std::array reg_byte_offsets{ + {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,284,288,296}}; static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); - enum sreg_flag_e {FLAGS}; + enum sreg_flag_e { FLAGS }; - enum mem_type_e {MEM, CSR, FENCE, RES}; + enum mem_type_e { MEM, CSR, FENCE, RES }; }; struct rv64ia: public arch_if { @@ -149,9 +183,8 @@ struct rv64ia: public arch_if { inline bool should_stop() { return interrupt_sim; } inline phys_addr_t v2p(const iss::addr_t& addr){ - if(addr.space != traits::MEM || - addr.type == iss::address_type::PHYSICAL || - addr_mode[static_cast(addr.access)&0x3]==address_type::PHYSICAL){ + if (addr.space != traits::MEM || addr.type == iss::address_type::PHYSICAL || + addr_mode[static_cast(addr.access)&0x3]==address_type::PHYSICAL) { return phys_addr_t(addr.access, addr.space, addr.val&traits::addr_mask); } else return virt2phys(addr); @@ -161,8 +194,7 @@ struct rv64ia: public arch_if { virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - inline - uint32_t get_last_branch(){return reg.last_branch;} + inline uint32_t get_last_branch() { return reg.last_branch; } protected: struct RV64IA_regs { diff --git a/riscv/incl/iss/debugger/riscv_target_adapter.h b/riscv/incl/iss/debugger/riscv_target_adapter.h index 7133e34..e6ec40e 100644 --- a/riscv/incl/iss/debugger/riscv_target_adapter.h +++ b/riscv/incl/iss/debugger/riscv_target_adapter.h @@ -40,6 +40,7 @@ #include #include +#include #include namespace iss { @@ -180,8 +181,8 @@ status riscv_target_adapter::read_registers(std::vector &data, st avail.clear(); const uint8_t *reg_base = core->get_regs_base_ptr(); for (size_t reg_no = 0; reg_no < arch::traits::NUM_REGS; ++reg_no) { - auto reg_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no)) / 8; - unsigned offset = traits::reg_byte_offset(reg_no); + auto reg_width = arch::traits::reg_bit_widths[static_cast::reg_e>(reg_no)] / 8; + unsigned offset = traits::reg_byte_offsets[reg_no]; for (size_t j = 0; j < reg_width; ++j) { data.push_back(*(reg_base + offset + j)); avail.push_back(0xff); @@ -215,8 +216,8 @@ template status riscv_target_adapter::write_registers(cons auto *reg_base = core->get_regs_base_ptr(); auto iter = data.data(); for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) { - auto reg_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no)) / 8; - auto offset = traits::reg_byte_offset(reg_no); + auto reg_width = arch::traits::reg_bit_widths[static_cast::reg_e>(reg_no)] / 8; + auto offset = traits::reg_byte_offsets[reg_no]; std::copy(iter, iter + reg_width, reg_base); iter += 4; reg_base += offset; @@ -231,10 +232,10 @@ status riscv_target_adapter::read_single_register(unsigned int reg_no, std // auto reg_size = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; auto *reg_base = core->get_regs_base_ptr(); - auto reg_width = arch::traits::reg_bit_width(reg_no) / 8; + auto reg_width = arch::traits::reg_bit_widths[reg_no] / 8; data.resize(reg_width); avail.resize(reg_width); - auto offset = traits::reg_byte_offset(reg_no); + auto offset = traits::reg_byte_offsets[reg_no]; std::copy(reg_base + offset, reg_base + offset + reg_width, data.begin()); std::fill(avail.begin(), avail.end(), 0xff); } else { @@ -251,8 +252,8 @@ template status riscv_target_adapter::write_single_register(unsigned int reg_no, const std::vector &data) { if (reg_no < 65) { auto *reg_base = core->get_regs_base_ptr(); - auto reg_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no)) / 8; - auto offset = traits::reg_byte_offset(reg_no); + auto reg_width = arch::traits::reg_bit_widths[static_cast::reg_e>(reg_no)] / 8; + auto offset = traits::reg_byte_offsets[reg_no]; std::copy(data.begin(), data.begin() + reg_width, reg_base + offset); } else { typed_addr_t a(iss::access_type::DEBUG_WRITE, traits::CSR, reg_no - 65); @@ -296,9 +297,7 @@ template status riscv_target_adapter::raw_query(std::strin template status riscv_target_adapter::threadinfo_query(int first, std::string &out_buf) { if (first) { - std::stringstream ss; - ss << "m" << std::hex << thread_idx.val; - out_buf = ss.str(); + out_buf = fmt::format("m{:x}", thread_idx.val); } else { out_buf = "l"; } @@ -348,8 +347,8 @@ template status riscv_target_adapter::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, std::function stop_callback) { auto *reg_base = core->get_regs_base_ptr(); - auto reg_width = arch::traits::reg_bit_width(arch::traits::PC) / 8; - auto offset = traits::reg_byte_offset(arch::traits::PC); + auto reg_width = arch::traits::reg_bit_widths[arch::traits::PC] / 8; + auto offset = traits::reg_byte_offsets[arch::traits::PC]; const uint8_t *iter = reinterpret_cast(&addr); std::copy(iter, iter + reg_width, reg_base); return resume_from_current(step, sig, thread, stop_callback); diff --git a/riscv/src/internal/vm_rv32gc.cpp b/riscv/src/internal/vm_rv32gc.cpp index e6d195d..67c44ef 100644 --- a/riscv/src/internal/vm_rv32gc.cpp +++ b/riscv/src/internal/vm_rv32gc.cpp @@ -1,38 +1,34 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2017, MINRES Technologies GmbH -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -// Contributors: -// eyck@minres.com - initial API and implementation -// -// -//////////////////////////////////////////////////////////////////////////////// +/******************************************************************************* + * Copyright (C) 2017, 2018 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ #include #include @@ -42,14 +38,14 @@ #include #include -#include +#include -#include #include +#include namespace iss { namespace vm { -namespace fp_impl{ +namespace fp_impl { void add_fp_functions_2_module(llvm::Module *, unsigned); } } @@ -74,7 +70,7 @@ public: void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } - target_adapter_if *accquire_target_adapter(server_if *srv) { + target_adapter_if *accquire_target_adapter(server_if *srv) override { debugger_if::dbg_enabled = true; if (vm_base::tgt_adapter == nullptr) vm_base::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); @@ -84,6 +80,8 @@ public: protected: using vm_base::get_reg_ptr; + inline const char *name(size_t index){return traits::reg_aliases.at(index);} + template inline ConstantInt *size(T type) { return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits())); } @@ -97,8 +95,7 @@ protected: return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size)); } - std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, - BasicBlock *) override; + std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override; void gen_leave_behavior(BasicBlock *leave_blk) override; @@ -118,7 +115,7 @@ protected: inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) { Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), - this->get_type(traits::XLEN)); + this->get_type(traits::XLEN)); this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true); } @@ -130,16 +127,16 @@ protected: using this_class = vm_impl; using compile_func = std::tuple (this_class::*)(virt_addr_t &pc, - code_word_t instr, - BasicBlock *bb); + code_word_t instr, + BasicBlock *bb); std::array lut; std::array lut_00, lut_01, lut_10; std::array lut_11; - std::array qlut; + std::array qlut; - std::array lutmasks = { { EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32 } }; + std::array lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}}; void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[], compile_func f) { @@ -516,18 +513,19 @@ private: std::tuple __lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LUI"); - this->gen_sync(iss::PRE_SYNC, 0); + this->gen_sync(PRE_SYNC, 0); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - int32_t fld_imm_val = signextend((bit_sub<12,20>(instr) << 12)); + uint8_t rd = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LUI x%1$d, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -535,12 +533,12 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ - Value* Xtmp0_val = this->gen_const(32U, fld_imm_val); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + if(rd != 0){ + Value* Xtmp0_val = this->gen_const(32U, imm); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 0); + this->gen_sync(POST_SYNC, 0); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -550,18 +548,19 @@ private: std::tuple __auipc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AUIPC"); - this->gen_sync(iss::PRE_SYNC, 1); + this->gen_sync(PRE_SYNC, 1); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - int32_t fld_imm_val = signextend((bit_sub<12,20>(instr) << 12)); + uint8_t rd = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AUIPC x%1%, 0x%2$08x"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -569,16 +568,16 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 1); + this->gen_sync(POST_SYNC, 1); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -588,18 +587,19 @@ private: std::tuple __jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("JAL"); - this->gen_sync(iss::PRE_SYNC, 2); + this->gen_sync(PRE_SYNC, 2); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - int32_t fld_imm_val = signextend((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + uint8_t rd = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("JAL x%1$d, 0x%2$x"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -607,21 +607,21 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* PC_val = this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 2); + this->gen_sync(POST_SYNC, 2); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -630,19 +630,20 @@ private: std::tuple __jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("JALR"); - this->gen_sync(iss::PRE_SYNC, 3); + this->gen_sync(PRE_SYNC, 3); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("JALR x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -652,9 +653,9 @@ private: Value* new_pc_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); Value* align_val = this->builder.CreateAnd( new_pc_val, this->gen_const(32U, 0x1)); @@ -676,11 +677,11 @@ private: this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* PC_val = this->builder.CreateAnd( new_pc_val, @@ -692,7 +693,7 @@ private: bb=bbnext; } this->builder.SetInsertPoint(bb); - this->gen_sync(iss::POST_SYNC, 3); + this->gen_sync(POST_SYNC, 3); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -701,19 +702,20 @@ private: std::tuple __beq(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BEQ"); - this->gen_sync(iss::PRE_SYNC, 4); + this->gen_sync(PRE_SYNC, 4); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BEQ x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -724,13 +726,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_EQ, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)), @@ -738,7 +740,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 4); + this->gen_sync(POST_SYNC, 4); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -747,19 +749,20 @@ private: std::tuple __bne(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BNE"); - this->gen_sync(iss::PRE_SYNC, 5); + this->gen_sync(PRE_SYNC, 5); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BNE x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -770,13 +773,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)), @@ -784,7 +787,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 5); + this->gen_sync(POST_SYNC, 5); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -793,19 +796,20 @@ private: std::tuple __blt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BLT"); - this->gen_sync(iss::PRE_SYNC, 6); + this->gen_sync(PRE_SYNC, 6); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BLT x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -817,16 +821,16 @@ private: this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 32, true)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)), @@ -834,7 +838,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 6); + this->gen_sync(POST_SYNC, 6); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -843,19 +847,20 @@ private: std::tuple __bge(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BGE"); - this->gen_sync(iss::PRE_SYNC, 7); + this->gen_sync(PRE_SYNC, 7); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BGE x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -867,16 +872,16 @@ private: this->builder.CreateICmp( ICmpInst::ICMP_SGE, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 32, true)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)), @@ -884,7 +889,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 7); + this->gen_sync(POST_SYNC, 7); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -893,19 +898,20 @@ private: std::tuple __bltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BLTU"); - this->gen_sync(iss::PRE_SYNC, 8); + this->gen_sync(PRE_SYNC, 8); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BLTU x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -916,13 +922,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)), @@ -930,7 +936,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 8); + this->gen_sync(POST_SYNC, 8); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -939,19 +945,20 @@ private: std::tuple __bgeu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BGEU"); - this->gen_sync(iss::PRE_SYNC, 9); + this->gen_sync(PRE_SYNC, 9); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BGEU x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -962,13 +969,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_UGE, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)), @@ -976,7 +983,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 9); + this->gen_sync(POST_SYNC, 9); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -985,19 +992,20 @@ private: std::tuple __lb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LB"); - this->gen_sync(iss::PRE_SYNC, 10); + this->gen_sync(PRE_SYNC, 10); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LB x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1007,18 +1015,18 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(32U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 8/8), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 10); + this->gen_sync(POST_SYNC, 10); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1028,19 +1036,20 @@ private: std::tuple __lh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LH"); - this->gen_sync(iss::PRE_SYNC, 11); + this->gen_sync(PRE_SYNC, 11); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LH x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1050,18 +1059,18 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(32U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 16/8), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 11); + this->gen_sync(POST_SYNC, 11); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1071,19 +1080,20 @@ private: std::tuple __lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LW"); - this->gen_sync(iss::PRE_SYNC, 12); + this->gen_sync(PRE_SYNC, 12); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LW x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1093,18 +1103,18 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(32U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 12); + this->gen_sync(POST_SYNC, 12); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1114,19 +1124,20 @@ private: std::tuple __lbu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LBU"); - this->gen_sync(iss::PRE_SYNC, 13); + this->gen_sync(PRE_SYNC, 13); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LBU x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1136,18 +1147,18 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(32U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 8/8), 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 13); + this->gen_sync(POST_SYNC, 13); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1157,19 +1168,20 @@ private: std::tuple __lhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LHU"); - this->gen_sync(iss::PRE_SYNC, 14); + this->gen_sync(PRE_SYNC, 14); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LHU x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1179,18 +1191,18 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(32U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 16/8), 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 14); + this->gen_sync(POST_SYNC, 14); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1200,19 +1212,20 @@ private: std::tuple __sb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SB"); - this->gen_sync(iss::PRE_SYNC, 15); + this->gen_sync(PRE_SYNC, 15); - int16_t fld_imm_val = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SB x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1222,16 +1235,16 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->gen_const(32U, imm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(8))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 15); + this->gen_sync(POST_SYNC, 15); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1241,19 +1254,20 @@ private: std::tuple __sh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SH"); - this->gen_sync(iss::PRE_SYNC, 16); + this->gen_sync(PRE_SYNC, 16); - int16_t fld_imm_val = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SH x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1263,16 +1277,16 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->gen_const(32U, imm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(16))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 16); + this->gen_sync(POST_SYNC, 16); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1282,19 +1296,20 @@ private: std::tuple __sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SW"); - this->gen_sync(iss::PRE_SYNC, 17); + this->gen_sync(PRE_SYNC, 17); - int16_t fld_imm_val = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SW x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1304,16 +1319,16 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->gen_const(32U, imm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 17); + this->gen_sync(POST_SYNC, 17); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1323,19 +1338,20 @@ private: std::tuple __addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ADDI"); - this->gen_sync(iss::PRE_SYNC, 18); + this->gen_sync(PRE_SYNC, 18); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ADDI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1343,16 +1359,16 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 18); + this->gen_sync(POST_SYNC, 18); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1362,19 +1378,20 @@ private: std::tuple __slti(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLTI"); - this->gen_sync(iss::PRE_SYNC, 19); + this->gen_sync(PRE_SYNC, 19); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLTI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1382,21 +1399,21 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 19); + this->gen_sync(POST_SYNC, 19); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1406,19 +1423,20 @@ private: std::tuple __sltiu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLTIU"); - this->gen_sync(iss::PRE_SYNC, 20); + this->gen_sync(PRE_SYNC, 20); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLTIU x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1426,20 +1444,20 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - int32_t full_imm_val = fld_imm_val; - if(fld_rd_val != 0){ + int32_t full_imm_val = imm; + if(rd != 0){ Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this->gen_const(32U, full_imm_val)), this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 20); + this->gen_sync(POST_SYNC, 20); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1449,19 +1467,20 @@ private: std::tuple __xori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("XORI"); - this->gen_sync(iss::PRE_SYNC, 21); + this->gen_sync(PRE_SYNC, 21); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("XORI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1469,14 +1488,16 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateXor( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_ext( + this->gen_reg_load(rs1 + traits::X0, 0), + 32, true), + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 21); + this->gen_sync(POST_SYNC, 21); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1486,19 +1507,20 @@ private: std::tuple __ori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ORI"); - this->gen_sync(iss::PRE_SYNC, 22); + this->gen_sync(PRE_SYNC, 22); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ORI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1506,14 +1528,16 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateOr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_ext( + this->gen_reg_load(rs1 + traits::X0, 0), + 32, true), + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 22); + this->gen_sync(POST_SYNC, 22); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1523,19 +1547,20 @@ private: std::tuple __andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ANDI"); - this->gen_sync(iss::PRE_SYNC, 23); + this->gen_sync(PRE_SYNC, 23); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1543,14 +1568,16 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAnd( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_ext( + this->gen_reg_load(rs1 + traits::X0, 0), + 32, true), + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 23); + this->gen_sync(POST_SYNC, 23); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1560,19 +1587,20 @@ private: std::tuple __slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLLI"); - this->gen_sync(iss::PRE_SYNC, 24); + this->gen_sync(PRE_SYNC, 24); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_shamt_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLLI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1580,18 +1608,18 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_shamt_val > 31){ + if(shamt > 31){ this->gen_raise_trap(0, 0); } else { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateShl( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_const(32U, shamt)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 24); + this->gen_sync(POST_SYNC, 24); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1601,19 +1629,20 @@ private: std::tuple __srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRLI"); - this->gen_sync(iss::PRE_SYNC, 25); + this->gen_sync(PRE_SYNC, 25); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_shamt_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRLI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1621,18 +1650,18 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_shamt_val > 31){ + if(shamt > 31){ this->gen_raise_trap(0, 0); } else { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateLShr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_const(32U, shamt)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 25); + this->gen_sync(POST_SYNC, 25); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1642,19 +1671,20 @@ private: std::tuple __srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRAI"); - this->gen_sync(iss::PRE_SYNC, 26); + this->gen_sync(PRE_SYNC, 26); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_shamt_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRAI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1662,18 +1692,18 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_shamt_val > 31){ + if(shamt > 31){ this->gen_raise_trap(0, 0); } else { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAShr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_const(32U, shamt)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 26); + this->gen_sync(POST_SYNC, 26); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1683,19 +1713,20 @@ private: std::tuple __add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ADD"); - this->gen_sync(iss::PRE_SYNC, 27); + this->gen_sync(PRE_SYNC, 27); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ADD x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1703,14 +1734,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 27); + this->gen_sync(POST_SYNC, 27); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1720,19 +1751,20 @@ private: std::tuple __sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SUB"); - this->gen_sync(iss::PRE_SYNC, 28); + this->gen_sync(PRE_SYNC, 28); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SUB x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1740,14 +1772,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateSub( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 28); + this->gen_sync(POST_SYNC, 28); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1757,19 +1789,20 @@ private: std::tuple __sll(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLL"); - this->gen_sync(iss::PRE_SYNC, 29); + this->gen_sync(PRE_SYNC, 29); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLL x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1777,16 +1810,18 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateShl( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this->builder.CreateAnd( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0x1f))); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs2 + traits::X0, 0), + this->builder.CreateSub( + this->gen_const(32U, 32), + this->gen_const(32U, 1)))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 29); + this->gen_sync(POST_SYNC, 29); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1796,19 +1831,20 @@ private: std::tuple __slt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLT"); - this->gen_sync(iss::PRE_SYNC, 30); + this->gen_sync(PRE_SYNC, 30); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLT x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1816,23 +1852,23 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 32, true)), this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 30); + this->gen_sync(POST_SYNC, 30); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1842,19 +1878,20 @@ private: std::tuple __sltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLTU"); - this->gen_sync(iss::PRE_SYNC, 31); + this->gen_sync(PRE_SYNC, 31); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLTU x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1862,25 +1899,25 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, false), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 32, false)), this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 31); + this->gen_sync(POST_SYNC, 31); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1890,19 +1927,20 @@ private: std::tuple __xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("XOR"); - this->gen_sync(iss::PRE_SYNC, 32); + this->gen_sync(PRE_SYNC, 32); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("XOR x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1910,14 +1948,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateXor( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 32); + this->gen_sync(POST_SYNC, 32); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1927,19 +1965,20 @@ private: std::tuple __srl(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRL"); - this->gen_sync(iss::PRE_SYNC, 33); + this->gen_sync(PRE_SYNC, 33); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRL x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1947,16 +1986,18 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateLShr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this->builder.CreateAnd( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0x1f))); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs2 + traits::X0, 0), + this->builder.CreateSub( + this->gen_const(32U, 32), + this->gen_const(32U, 1)))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 33); + this->gen_sync(POST_SYNC, 33); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1966,19 +2007,20 @@ private: std::tuple __sra(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRA"); - this->gen_sync(iss::PRE_SYNC, 34); + this->gen_sync(PRE_SYNC, 34); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRA x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1986,16 +2028,18 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAShr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this->builder.CreateAnd( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0x1f))); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs2 + traits::X0, 0), + this->builder.CreateSub( + this->gen_const(32U, 32), + this->gen_const(32U, 1)))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 34); + this->gen_sync(POST_SYNC, 34); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2005,19 +2049,20 @@ private: std::tuple __or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("OR"); - this->gen_sync(iss::PRE_SYNC, 35); + this->gen_sync(PRE_SYNC, 35); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("OR x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2025,14 +2070,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateOr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 35); + this->gen_sync(POST_SYNC, 35); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2042,19 +2087,20 @@ private: std::tuple __and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AND"); - this->gen_sync(iss::PRE_SYNC, 36); + this->gen_sync(PRE_SYNC, 36); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AND x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2062,14 +2108,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAnd( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 36); + this->gen_sync(POST_SYNC, 36); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2079,18 +2125,18 @@ private: std::tuple __fence(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FENCE"); - this->gen_sync(iss::PRE_SYNC, 37); + this->gen_sync(PRE_SYNC, 37); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_succ_val = ((bit_sub<20,4>(instr))); - uint8_t fld_pred_val = ((bit_sub<24,4>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("FENCE"), + this->builder.CreateGlobalStringPtr("fence"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2100,15 +2146,15 @@ private: Value* FENCEtmp0_val = this->builder.CreateOr( this->builder.CreateShl( - this->gen_const(32U, fld_pred_val), + this->gen_const(32U, pred), this->gen_const(32U, 4)), - this->gen_const(32U, fld_succ_val)); + this->gen_const(32U, succ)); this->gen_write_mem( traits::FENCE, this->gen_const(64U, 0), this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 37); + this->gen_sync(POST_SYNC, 37); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2118,17 +2164,17 @@ private: std::tuple __fence_i(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FENCE_I"); - this->gen_sync(iss::PRE_SYNC, 38); + this->gen_sync(PRE_SYNC, 38); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint16_t fld_imm_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("FENCE_I"), + this->builder.CreateGlobalStringPtr("fence_i"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2136,14 +2182,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* FENCEtmp0_val = this->gen_const(32U, fld_imm_val); + Value* FENCEtmp0_val = this->gen_const(32U, imm); this->gen_write_mem( traits::FENCE, this->gen_const(64U, 1), this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32))); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 38); + this->gen_sync(POST_SYNC, 38); this->gen_trap_check(this->leave_blk); return std::make_tuple(FLUSH, nullptr); } @@ -2152,14 +2198,14 @@ private: std::tuple __ecall(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ECALL"); - this->gen_sync(iss::PRE_SYNC, 39); + this->gen_sync(PRE_SYNC, 39); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("ECALL"), + this->builder.CreateGlobalStringPtr("ecall"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2168,7 +2214,7 @@ private: pc=pc+4; this->gen_raise_trap(0, 11); - this->gen_sync(iss::POST_SYNC, 39); + this->gen_sync(POST_SYNC, 39); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -2177,14 +2223,14 @@ private: std::tuple __ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("EBREAK"); - this->gen_sync(iss::PRE_SYNC, 40); + this->gen_sync(PRE_SYNC, 40); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("EBREAK"), + this->builder.CreateGlobalStringPtr("ebreak"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2193,7 +2239,7 @@ private: pc=pc+4; this->gen_raise_trap(0, 3); - this->gen_sync(iss::POST_SYNC, 40); + this->gen_sync(POST_SYNC, 40); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -2202,14 +2248,14 @@ private: std::tuple __uret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("URET"); - this->gen_sync(iss::PRE_SYNC, 41); + this->gen_sync(PRE_SYNC, 41); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("URET"), + this->builder.CreateGlobalStringPtr("uret"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2218,7 +2264,7 @@ private: pc=pc+4; this->gen_leave_trap(0); - this->gen_sync(iss::POST_SYNC, 41); + this->gen_sync(POST_SYNC, 41); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -2227,14 +2273,14 @@ private: std::tuple __sret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRET"); - this->gen_sync(iss::PRE_SYNC, 42); + this->gen_sync(PRE_SYNC, 42); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("SRET"), + this->builder.CreateGlobalStringPtr("sret"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2243,7 +2289,7 @@ private: pc=pc+4; this->gen_leave_trap(1); - this->gen_sync(iss::POST_SYNC, 42); + this->gen_sync(POST_SYNC, 42); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -2252,14 +2298,14 @@ private: std::tuple __mret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("MRET"); - this->gen_sync(iss::PRE_SYNC, 43); + this->gen_sync(PRE_SYNC, 43); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("MRET"), + this->builder.CreateGlobalStringPtr("mret"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2268,7 +2314,7 @@ private: pc=pc+4; this->gen_leave_trap(3); - this->gen_sync(iss::POST_SYNC, 43); + this->gen_sync(POST_SYNC, 43); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -2277,14 +2323,14 @@ private: std::tuple __wfi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("WFI"); - this->gen_sync(iss::PRE_SYNC, 44); + this->gen_sync(PRE_SYNC, 44); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("WFI"), + this->builder.CreateGlobalStringPtr("wfi"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2294,7 +2340,7 @@ private: this->gen_wait(1); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 44); + this->gen_sync(POST_SYNC, 44); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2304,16 +2350,16 @@ private: std::tuple __sfence_vma(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SFENCE.VMA"); - this->gen_sync(iss::PRE_SYNC, 45); + this->gen_sync(PRE_SYNC, 45); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("SFENCE.VMA"), + this->builder.CreateGlobalStringPtr("sfence.vma"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2321,18 +2367,18 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* FENCEtmp0_val = this->gen_const(32U, fld_rs1_val); + Value* FENCEtmp0_val = this->gen_const(32U, rs1); this->gen_write_mem( traits::FENCE, this->gen_const(64U, 2), this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32))); - Value* FENCEtmp1_val = this->gen_const(32U, fld_rs2_val); + Value* FENCEtmp1_val = this->gen_const(32U, rs2); this->gen_write_mem( traits::FENCE, this->gen_const(64U, 3), this->builder.CreateZExtOrTrunc(FENCEtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 45); + this->gen_sync(POST_SYNC, 45); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2342,19 +2388,20 @@ private: std::tuple __csrrw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRW"); - this->gen_sync(iss::PRE_SYNC, 46); + this->gen_sync(PRE_SYNC, 46); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRW x%1$d, %2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2362,25 +2409,25 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* rs_val_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ - Value* csr_val_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); + Value* rs_val_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ + Value* csr_val_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 32/8); Value* CSRtmp0_val = rs_val_val; this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp0_val,this->get_type(32))); Value* Xtmp1_val = csr_val_val; - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } else { Value* CSRtmp2_val = rs_val_val; this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp2_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 46); + this->gen_sync(POST_SYNC, 46); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2390,19 +2437,20 @@ private: std::tuple __csrrs(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRS"); - this->gen_sync(iss::PRE_SYNC, 47); + this->gen_sync(PRE_SYNC, 47); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRS x%1$d, %2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2410,23 +2458,23 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); - Value* xrs1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ + Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 32/8); + Value* xrs1_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ Value* Xtmp0_val = xrd_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - if(fld_rs1_val != 0){ + if(rs1 != 0){ Value* CSRtmp1_val = this->builder.CreateOr( xrd_val, xrs1_val); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 47); + this->gen_sync(POST_SYNC, 47); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2436,19 +2484,20 @@ private: std::tuple __csrrc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRC"); - this->gen_sync(iss::PRE_SYNC, 48); + this->gen_sync(PRE_SYNC, 48); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRC x%1$d, %2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2456,23 +2505,23 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); - Value* xrs1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ + Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 32/8); + Value* xrs1_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ Value* Xtmp0_val = xrd_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - if(fld_rs1_val != 0){ + if(rs1 != 0){ Value* CSRtmp1_val = this->builder.CreateAnd( xrd_val, this->builder.CreateNot(xrs1_val)); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 48); + this->gen_sync(POST_SYNC, 48); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2482,19 +2531,20 @@ private: std::tuple __csrrwi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRWI"); - this->gen_sync(iss::PRE_SYNC, 49); + this->gen_sync(PRE_SYNC, 49); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_zimm_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRWI x%1$d, %2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2502,20 +2552,20 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ - Value* Xtmp0_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + if(rd != 0){ + Value* Xtmp0_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 32/8); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* CSRtmp1_val = this->gen_ext( - this->gen_const(32U, fld_zimm_val), + this->gen_const(32U, zimm), 32, false); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 49); + this->gen_sync(POST_SYNC, 49); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2525,19 +2575,20 @@ private: std::tuple __csrrsi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRSI"); - this->gen_sync(iss::PRE_SYNC, 50); + this->gen_sync(PRE_SYNC, 50); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_zimm_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRSI x%1$d, %2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2545,25 +2596,25 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); - if(fld_zimm_val != 0){ + Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 32/8); + if(zimm != 0){ Value* CSRtmp0_val = this->builder.CreateOr( res_val, this->gen_ext( - this->gen_const(32U, fld_zimm_val), + this->gen_const(32U, zimm), 32, false)); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp0_val,this->get_type(32))); } - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp1_val = res_val; - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 50); + this->gen_sync(POST_SYNC, 50); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2573,19 +2624,20 @@ private: std::tuple __csrrci(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRCI"); - this->gen_sync(iss::PRE_SYNC, 51); + this->gen_sync(PRE_SYNC, 51); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_zimm_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRCI x%1$d, %2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2593,25 +2645,25 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); - if(fld_rd_val != 0){ + Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 32/8); + if(rd != 0){ Value* Xtmp0_val = res_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - if(fld_zimm_val != 0){ + if(zimm != 0){ Value* CSRtmp1_val = this->builder.CreateAnd( res_val, this->builder.CreateNot(this->gen_ext( - this->gen_const(32U, fld_zimm_val), + this->gen_const(32U, zimm), 32, false))); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 51); + this->gen_sync(POST_SYNC, 51); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2621,19 +2673,20 @@ private: std::tuple __mul(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("MUL"); - this->gen_sync(iss::PRE_SYNC, 52); + this->gen_sync(PRE_SYNC, 52); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("MUL x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2641,24 +2694,24 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* res_val = this->builder.CreateMul( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 128, false), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 128, false)); Value* Xtmp0_val = this->gen_ext( res_val, 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 52); + this->gen_sync(POST_SYNC, 52); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2668,19 +2721,20 @@ private: std::tuple __mulh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("MULH"); - this->gen_sync(iss::PRE_SYNC, 53); + this->gen_sync(PRE_SYNC, 53); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("MULH x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2688,14 +2742,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* res_val = this->builder.CreateMul( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 128, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 128, true)); Value* Xtmp0_val = this->gen_ext( @@ -2704,10 +2758,10 @@ private: this->gen_const(32U, 32)), 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 53); + this->gen_sync(POST_SYNC, 53); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2717,19 +2771,20 @@ private: std::tuple __mulhsu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("MULHSU"); - this->gen_sync(iss::PRE_SYNC, 54); + this->gen_sync(PRE_SYNC, 54); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("MULHSU x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2737,14 +2792,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* res_val = this->builder.CreateMul( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 128, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 128, false)); Value* Xtmp0_val = this->gen_ext( @@ -2753,10 +2808,10 @@ private: this->gen_const(32U, 32)), 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 54); + this->gen_sync(POST_SYNC, 54); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2766,19 +2821,20 @@ private: std::tuple __mulhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("MULHU"); - this->gen_sync(iss::PRE_SYNC, 55); + this->gen_sync(PRE_SYNC, 55); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("MULHU x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2786,14 +2842,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* res_val = this->builder.CreateMul( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 128, false), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 128, false)); Value* Xtmp0_val = this->gen_ext( @@ -2802,10 +2858,10 @@ private: this->gen_const(32U, 32)), 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 55); + this->gen_sync(POST_SYNC, 55); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2815,19 +2871,20 @@ private: std::tuple __div(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("DIV"); - this->gen_sync(iss::PRE_SYNC, 56); + this->gen_sync(PRE_SYNC, 56); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("DIV x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2835,7 +2892,7 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ { BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); @@ -2843,7 +2900,7 @@ private: // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this->gen_const(32U, 0)), bb_then, bb_else); @@ -2859,7 +2916,7 @@ private: this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_EQ, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), + this->gen_reg_load(rs1 + traits::X0, 1), 32, true), this->gen_ext( this->gen_const(32U, MMIN_val), @@ -2876,7 +2933,7 @@ private: this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_EQ, this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), + this->gen_reg_load(rs2 + traits::X0, 2), 32, true), this->gen_ext( this->gen_const(32U, M1_val), @@ -2886,19 +2943,19 @@ private: this->builder.SetInsertPoint(bb_then); { Value* Xtmp0_val = this->gen_const(32U, MMIN_val); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { Value* Xtmp1_val = this->builder.CreateSDiv( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 3), + this->gen_reg_load(rs1 + traits::X0, 3), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 3), + this->gen_reg_load(rs2 + traits::X0, 3), 32, true)); - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -2910,12 +2967,12 @@ private: { Value* Xtmp2_val = this->builder.CreateSDiv( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 2), + this->gen_reg_load(rs1 + traits::X0, 2), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), + this->gen_reg_load(rs2 + traits::X0, 2), 32, true)); - this->builder.CreateStore(Xtmp2_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp2_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -2926,7 +2983,7 @@ private: this->builder.SetInsertPoint(bb_else); { Value* Xtmp3_val = this->builder.CreateNeg(this->gen_const(32U, 1)); - this->builder.CreateStore(Xtmp3_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp3_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -2934,7 +2991,7 @@ private: this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 56); + this->gen_sync(POST_SYNC, 56); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2944,19 +3001,20 @@ private: std::tuple __divu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("DIVU"); - this->gen_sync(iss::PRE_SYNC, 57); + this->gen_sync(PRE_SYNC, 57); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("DIVU x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2964,7 +3022,7 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ { BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); @@ -2972,7 +3030,7 @@ private: // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this->gen_const(32U, 0)), bb_then, bb_else); @@ -2980,20 +3038,20 @@ private: { Value* Xtmp0_val = this->builder.CreateUDiv( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), + this->gen_reg_load(rs1 + traits::X0, 1), 32, false), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 1), + this->gen_reg_load(rs2 + traits::X0, 1), 32, false)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { Value* Xtmp1_val = this->builder.CreateNeg(this->gen_const(32U, 1)); - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -3001,7 +3059,7 @@ private: this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 57); + this->gen_sync(POST_SYNC, 57); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3011,19 +3069,20 @@ private: std::tuple __rem(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("REM"); - this->gen_sync(iss::PRE_SYNC, 58); + this->gen_sync(PRE_SYNC, 58); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("REM x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3031,7 +3090,7 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ { BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); @@ -3039,7 +3098,7 @@ private: // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this->gen_const(32U, 0)), bb_then, bb_else); @@ -3055,7 +3114,7 @@ private: this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_EQ, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), + this->gen_reg_load(rs1 + traits::X0, 1), 32, true), this->gen_ext( this->gen_const(32U, MMIN_val), @@ -3072,7 +3131,7 @@ private: this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_EQ, this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), + this->gen_reg_load(rs2 + traits::X0, 2), 32, true), this->gen_ext( this->gen_const(32U, M1_val), @@ -3082,21 +3141,21 @@ private: this->builder.SetInsertPoint(bb_then); { Value* Xtmp0_val = this->gen_const(32U, 0); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { Value* Xtmp1_val = this->builder.CreateURem( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 3), + this->gen_reg_load(rs1 + traits::X0, 3), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 3), + this->gen_reg_load(rs2 + traits::X0, 3), 32, true)); - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -3108,14 +3167,14 @@ private: { Value* Xtmp2_val = this->builder.CreateURem( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 2), + this->gen_reg_load(rs1 + traits::X0, 2), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), + this->gen_reg_load(rs2 + traits::X0, 2), 32, true)); - this->builder.CreateStore(Xtmp2_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp2_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -3125,8 +3184,8 @@ private: this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { - Value* Xtmp3_val = this->gen_reg_load(fld_rs1_val + traits::X0, 1); - this->builder.CreateStore(Xtmp3_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp3_val = this->gen_reg_load(rs1 + traits::X0, 1); + this->builder.CreateStore(Xtmp3_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -3134,7 +3193,7 @@ private: this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 58); + this->gen_sync(POST_SYNC, 58); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3144,19 +3203,20 @@ private: std::tuple __remu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("REMU"); - this->gen_sync(iss::PRE_SYNC, 59); + this->gen_sync(PRE_SYNC, 59); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("REMU x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3164,7 +3224,7 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ { BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); @@ -3172,7 +3232,7 @@ private: // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this->gen_const(32U, 0)), bb_then, bb_else); @@ -3180,20 +3240,20 @@ private: { Value* Xtmp0_val = this->builder.CreateURem( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), + this->gen_reg_load(rs1 + traits::X0, 1), 32, false), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 1), + this->gen_reg_load(rs2 + traits::X0, 1), 32, false)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { - Value* Xtmp1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 1); - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp1_val = this->gen_reg_load(rs1 + traits::X0, 1); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -3201,7 +3261,7 @@ private: this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 59); + this->gen_sync(POST_SYNC, 59); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3211,20 +3271,21 @@ private: std::tuple __lr_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LR.W"); - this->gen_sync(iss::PRE_SYNC, 60); + this->gen_sync(PRE_SYNC, 60); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LR.W x%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "lr.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3232,13 +3293,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + if(rd != 0){ + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* REStmp1_val = this->gen_ext( this->builder.CreateNeg(this->gen_const(8U, 1)), 32, @@ -3249,7 +3310,7 @@ private: this->builder.CreateZExtOrTrunc(REStmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 60); + this->gen_sync(POST_SYNC, 60); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3259,21 +3320,22 @@ private: std::tuple __sc_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SC.W"); - this->gen_sync(iss::PRE_SYNC, 61); + this->gen_sync(PRE_SYNC, 61); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SC.W x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sc.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3281,7 +3343,7 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_read_mem(traits::RES, offs_val, 32/8); { BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); @@ -3295,7 +3357,7 @@ private: bbnext); this->builder.SetInsertPoint(bb_then); { - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 1); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 1); this->gen_write_mem( traits::MEM, offs_val, @@ -3305,7 +3367,7 @@ private: bb=bbnext; } this->builder.SetInsertPoint(bb); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp1_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, @@ -3314,10 +3376,10 @@ private: this->gen_const(32U, 0), this->gen_const(32U, 1), 32); - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 61); + this->gen_sync(POST_SYNC, 61); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3327,21 +3389,22 @@ private: std::tuple __amoswap_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOSWAP.W"); - this->gen_sync(iss::PRE_SYNC, 62); + this->gen_sync(PRE_SYNC, 62); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOSWAP.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoswap.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3349,21 +3412,21 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - Value* MEMtmp1_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp1_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 62); + this->gen_sync(POST_SYNC, 62); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3373,21 +3436,22 @@ private: std::tuple __amoadd_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOADD.W"); - this->gen_sync(iss::PRE_SYNC, 63); + this->gen_sync(PRE_SYNC, 63); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOADD.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoadd.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3395,25 +3459,25 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateAdd( res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 63); + this->gen_sync(POST_SYNC, 63); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3423,21 +3487,22 @@ private: std::tuple __amoxor_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOXOR.W"); - this->gen_sync(iss::PRE_SYNC, 64); + this->gen_sync(PRE_SYNC, 64); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOXOR.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoxor.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3445,25 +3510,25 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateXor( res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 64); + this->gen_sync(POST_SYNC, 64); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3473,21 +3538,22 @@ private: std::tuple __amoand_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOAND.W"); - this->gen_sync(iss::PRE_SYNC, 65); + this->gen_sync(PRE_SYNC, 65); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOAND.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoand.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3495,25 +3561,25 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateAnd( res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 65); + this->gen_sync(POST_SYNC, 65); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3523,21 +3589,22 @@ private: std::tuple __amoor_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOOR.W"); - this->gen_sync(iss::PRE_SYNC, 66); + this->gen_sync(PRE_SYNC, 66); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOOR.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoor.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3545,25 +3612,25 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateOr( res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 66); + this->gen_sync(POST_SYNC, 66); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3573,21 +3640,22 @@ private: std::tuple __amomin_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMIN.W"); - this->gen_sync(iss::PRE_SYNC, 67); + this->gen_sync(PRE_SYNC, 67); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMIN.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amomin.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3595,14 +3663,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3611,9 +3679,9 @@ private: res1_val, 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 32, true)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), res1_val, 32); Value* MEMtmp1_val = res2_val; @@ -3622,7 +3690,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 67); + this->gen_sync(POST_SYNC, 67); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3632,21 +3700,22 @@ private: std::tuple __amomax_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMAX.W"); - this->gen_sync(iss::PRE_SYNC, 68); + this->gen_sync(PRE_SYNC, 68); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMAX.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amomax.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3654,14 +3723,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3670,9 +3739,9 @@ private: res1_val, 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 32, true)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), res1_val, 32); Value* MEMtmp1_val = res2_val; @@ -3681,7 +3750,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 68); + this->gen_sync(POST_SYNC, 68); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3691,21 +3760,22 @@ private: std::tuple __amominu_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMINU.W"); - this->gen_sync(iss::PRE_SYNC, 69); + this->gen_sync(PRE_SYNC, 69); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMINU.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amominu.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3713,21 +3783,21 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, false); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_UGT, res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), + this->gen_reg_load(rs2 + traits::X0, 0), res1_val, 32); Value* MEMtmp1_val = res2_val; @@ -3736,7 +3806,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 69); + this->gen_sync(POST_SYNC, 69); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3746,21 +3816,22 @@ private: std::tuple __amomaxu_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMAXU.W"); - this->gen_sync(iss::PRE_SYNC, 70); + this->gen_sync(PRE_SYNC, 70); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMAXU.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amomaxu.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3768,21 +3839,21 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, false); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), + this->gen_reg_load(rs2 + traits::X0, 0), res1_val, 32); Value* MEMtmp1_val = res2_val; @@ -3791,7 +3862,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 70); + this->gen_sync(POST_SYNC, 70); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3801,18 +3872,19 @@ private: std::tuple __c_addi4spn(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.ADDI4SPN"); - this->gen_sync(iss::PRE_SYNC, 71); + this->gen_sync(PRE_SYNC, 71); - uint8_t fld_rd_val = ((bit_sub<2,3>(instr))); - uint16_t fld_imm_val = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); + uint8_t rd = ((bit_sub<2,3>(instr))); + uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.ADDI4SPN x%1$d, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3820,15 +3892,15 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - if(fld_imm_val == 0){ + if(imm == 0){ this->gen_raise_trap(0, 2); } Value* Xtmp0_val = this->builder.CreateAdd( this->gen_reg_load(2 + traits::X0, 0), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + 8 + traits::X0), false); + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + 8 + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 71); + this->gen_sync(POST_SYNC, 71); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3838,19 +3910,20 @@ private: std::tuple __c_lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.LW"); - this->gen_sync(iss::PRE_SYNC, 72); + this->gen_sync(PRE_SYNC, 72); - uint8_t fld_rd_val = ((bit_sub<2,3>(instr))); - uint8_t fld_uimm_val = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.LW x(8+%1$d), x(8+%2$d), 0x%3$05x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_uimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {uimm:#05x}", fmt::arg("mnemonic", "c.lw"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs1", name(8+rs1)), fmt::arg("uimm", uimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3859,12 +3932,12 @@ private: pc=pc+2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rs1_val + 8 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); + this->gen_reg_load(rs1 + 8 + traits::X0, 0), + this->gen_const(32U, uimm)); Value* Xtmp0_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + 8 + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + 8 + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 72); + this->gen_sync(POST_SYNC, 72); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3874,19 +3947,20 @@ private: std::tuple __c_sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.SW"); - this->gen_sync(iss::PRE_SYNC, 73); + this->gen_sync(PRE_SYNC, 73); - uint8_t fld_rs2_val = ((bit_sub<2,3>(instr))); - uint8_t fld_uimm_val = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.SW x(8+%1$d), x(8+%2$d), 0x%3$05x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_uimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {uimm:#05x}", fmt::arg("mnemonic", "c.sw"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3895,15 +3969,15 @@ private: pc=pc+2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rs1_val + 8 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + 8 + traits::X0, 0); + this->gen_reg_load(rs1 + 8 + traits::X0, 0), + this->gen_const(32U, uimm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + 8 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 73); + this->gen_sync(POST_SYNC, 73); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3913,18 +3987,19 @@ private: std::tuple __c_addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.ADDI"); - this->gen_sync(iss::PRE_SYNC, 74); + this->gen_sync(PRE_SYNC, 74); - int8_t fld_imm_val = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<7,5>(instr))); + int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.ADDI x%1$d, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3934,12 +4009,12 @@ private: Value* Xtmp0_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rs1_val + traits::X0), false); + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1 + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 74); + this->gen_sync(POST_SYNC, 74); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3949,14 +4024,14 @@ private: std::tuple __c_nop(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.NOP"); - this->gen_sync(iss::PRE_SYNC, 75); + this->gen_sync(PRE_SYNC, 75); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("C.NOP"), + this->builder.CreateGlobalStringPtr("c.nop"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3966,7 +4041,7 @@ private: /* TODO: describe operations for C.NOP ! */ this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 75); + this->gen_sync(POST_SYNC, 75); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3976,17 +4051,18 @@ private: std::tuple __c_jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.JAL"); - this->gen_sync(iss::PRE_SYNC, 76); + this->gen_sync(PRE_SYNC, 76); - int16_t fld_imm_val = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.JAL 0x%1$05x"); - ins_fmter % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"), + fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4002,11 +4078,11 @@ private: this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 76); + this->gen_sync(POST_SYNC, 76); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -4015,18 +4091,19 @@ private: std::tuple __c_li(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.LI"); - this->gen_sync(iss::PRE_SYNC, 77); + this->gen_sync(PRE_SYNC, 77); - int8_t fld_imm_val = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); + int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.LI x%1$d, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4034,13 +4111,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - if(fld_rd_val == 0){ + if(rd == 0){ this->gen_raise_trap(0, 2); } - Value* Xtmp0_val = this->gen_const(32U, fld_imm_val); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_const(32U, imm); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 77); + this->gen_sync(POST_SYNC, 77); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4050,18 +4127,19 @@ private: std::tuple __c_lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.LUI"); - this->gen_sync(iss::PRE_SYNC, 78); + this->gen_sync(PRE_SYNC, 78); - int32_t fld_imm_val = signextend((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); + uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.LUI x%1$d, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4069,16 +4147,16 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - if(fld_rd_val == 0){ + if(rd == 0){ this->gen_raise_trap(0, 2); } - if(fld_imm_val == 0){ + if(imm == 0){ this->gen_raise_trap(0, 2); } - Value* Xtmp0_val = this->gen_const(32U, fld_imm_val); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_const(32U, imm); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 78); + this->gen_sync(POST_SYNC, 78); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4088,17 +4166,18 @@ private: std::tuple __c_addi16sp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.ADDI16SP"); - this->gen_sync(iss::PRE_SYNC, 79); + this->gen_sync(PRE_SYNC, 79); - int16_t fld_imm_val = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.ADDI16SP 0x%1$05x"); - ins_fmter % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.addi16sp"), + fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4110,10 +4189,10 @@ private: this->gen_ext( this->gen_reg_load(2 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(2 + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 79); + this->gen_sync(POST_SYNC, 79); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4123,18 +4202,19 @@ private: std::tuple __c_srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.SRLI"); - this->gen_sync(iss::PRE_SYNC, 80); + this->gen_sync(PRE_SYNC, 80); - uint8_t fld_shamt_val = ((bit_sub<2,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.SRLI x(8+%1$d), %2$d"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4142,13 +4222,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = fld_rs1_val + 8; + uint8_t rs1_idx_val = rs1 + 8; Value* Xtmp0_val = this->builder.CreateLShr( this->gen_reg_load(rs1_idx_val + traits::X0, 0), - this->gen_const(32U, fld_shamt_val)); + this->gen_const(32U, shamt)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 80); + this->gen_sync(POST_SYNC, 80); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4158,18 +4238,19 @@ private: std::tuple __c_srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.SRAI"); - this->gen_sync(iss::PRE_SYNC, 81); + this->gen_sync(PRE_SYNC, 81); - uint8_t fld_shamt_val = ((bit_sub<2,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.SRAI x(8+%1$d), %2$d"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4177,13 +4258,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = fld_rs1_val + 8; + uint8_t rs1_idx_val = rs1 + 8; Value* Xtmp0_val = this->builder.CreateAShr( this->gen_reg_load(rs1_idx_val + traits::X0, 0), - this->gen_const(32U, fld_shamt_val)); + this->gen_const(32U, shamt)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 81); + this->gen_sync(POST_SYNC, 81); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4193,18 +4274,19 @@ private: std::tuple __c_andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.ANDI"); - this->gen_sync(iss::PRE_SYNC, 82); + this->gen_sync(PRE_SYNC, 82); - uint8_t fld_imm_val = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.ANDI x(8+%1$d), 0x%2$05x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4212,13 +4294,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = fld_rs1_val + 8; + uint8_t rs1_idx_val = rs1 + 8; Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(rs1_idx_val + traits::X0, 0), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 82); + this->gen_sync(POST_SYNC, 82); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4228,18 +4310,19 @@ private: std::tuple __c_sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.SUB"); - this->gen_sync(iss::PRE_SYNC, 83); + this->gen_sync(PRE_SYNC, 83); - uint8_t fld_rs2_val = ((bit_sub<2,3>(instr))); - uint8_t fld_rd_val = ((bit_sub<7,3>(instr))); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.SUB x(8+%1$d), x(8+%2$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4247,13 +4330,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rd_idx_val = fld_rd_val + 8; + uint8_t rd_idx_val = rd + 8; Value* Xtmp0_val = this->builder.CreateSub( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + 8 + traits::X0, 0)); + this->gen_reg_load(rs2 + 8 + traits::X0, 0)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 83); + this->gen_sync(POST_SYNC, 83); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4263,18 +4346,19 @@ private: std::tuple __c_xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.XOR"); - this->gen_sync(iss::PRE_SYNC, 84); + this->gen_sync(PRE_SYNC, 84); - uint8_t fld_rs2_val = ((bit_sub<2,3>(instr))); - uint8_t fld_rd_val = ((bit_sub<7,3>(instr))); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.XOR x(8+%1$d), x(8+%2$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4282,13 +4366,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rd_idx_val = fld_rd_val + 8; + uint8_t rd_idx_val = rd + 8; Value* Xtmp0_val = this->builder.CreateXor( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + 8 + traits::X0, 0)); + this->gen_reg_load(rs2 + 8 + traits::X0, 0)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 84); + this->gen_sync(POST_SYNC, 84); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4298,18 +4382,19 @@ private: std::tuple __c_or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.OR"); - this->gen_sync(iss::PRE_SYNC, 85); + this->gen_sync(PRE_SYNC, 85); - uint8_t fld_rs2_val = ((bit_sub<2,3>(instr))); - uint8_t fld_rd_val = ((bit_sub<7,3>(instr))); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.OR x(8+%1$d), x(8+%2$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4317,13 +4402,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rd_idx_val = fld_rd_val + 8; + uint8_t rd_idx_val = rd + 8; Value* Xtmp0_val = this->builder.CreateOr( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + 8 + traits::X0, 0)); + this->gen_reg_load(rs2 + 8 + traits::X0, 0)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 85); + this->gen_sync(POST_SYNC, 85); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4333,18 +4418,19 @@ private: std::tuple __c_and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.AND"); - this->gen_sync(iss::PRE_SYNC, 86); + this->gen_sync(PRE_SYNC, 86); - uint8_t fld_rs2_val = ((bit_sub<2,3>(instr))); - uint8_t fld_rd_val = ((bit_sub<7,3>(instr))); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.AND x(8+%1$d), x(8+%2$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4352,13 +4438,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rd_idx_val = fld_rd_val + 8; + uint8_t rd_idx_val = rd + 8; Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + 8 + traits::X0, 0)); + this->gen_reg_load(rs2 + 8 + traits::X0, 0)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 86); + this->gen_sync(POST_SYNC, 86); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4368,17 +4454,18 @@ private: std::tuple __c_j(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.J"); - this->gen_sync(iss::PRE_SYNC, 87); + this->gen_sync(PRE_SYNC, 87); - int16_t fld_imm_val = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.J 0x%1$05x"); - ins_fmter % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"), + fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4390,11 +4477,11 @@ private: this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 87); + this->gen_sync(POST_SYNC, 87); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -4403,18 +4490,19 @@ private: std::tuple __c_beqz(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.BEQZ"); - this->gen_sync(iss::PRE_SYNC, 88); + this->gen_sync(PRE_SYNC, 88); - int16_t fld_imm_val = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.BEQZ x(8+%1$d), 0x%2$05x"); - ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4425,13 +4513,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_EQ, - this->gen_reg_load(fld_rs1_val + 8 + traits::X0, 0), + this->gen_reg_load(rs1 + 8 + traits::X0, 0), this->gen_const(32U, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 2)), @@ -4439,7 +4527,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 88); + this->gen_sync(POST_SYNC, 88); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -4448,18 +4536,19 @@ private: std::tuple __c_bnez(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.BNEZ"); - this->gen_sync(iss::PRE_SYNC, 89); + this->gen_sync(PRE_SYNC, 89); - int16_t fld_imm_val = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.BNEZ x(8+%1$d), 0x%2$05x"); - ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4470,13 +4559,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs1_val + 8 + traits::X0, 0), + this->gen_reg_load(rs1 + 8 + traits::X0, 0), this->gen_const(32U, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 2)), @@ -4484,7 +4573,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 89); + this->gen_sync(POST_SYNC, 89); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -4493,18 +4582,19 @@ private: std::tuple __c_slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.SLLI"); - this->gen_sync(iss::PRE_SYNC, 90); + this->gen_sync(PRE_SYNC, 90); - uint8_t fld_shamt_val = ((bit_sub<2,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<7,5>(instr))); + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.SLLI x%1$d, %2$d"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4512,15 +4602,15 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - if(fld_rs1_val == 0){ + if(rs1 == 0){ this->gen_raise_trap(0, 2); } Value* Xtmp0_val = this->builder.CreateShl( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rs1_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_const(32U, shamt)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1 + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 90); + this->gen_sync(POST_SYNC, 90); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4530,18 +4620,19 @@ private: std::tuple __c_lwsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.LWSP"); - this->gen_sync(iss::PRE_SYNC, 91); + this->gen_sync(PRE_SYNC, 91); - uint8_t fld_uimm_val = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.LWSP x%1$d, sp, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_uimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4551,11 +4642,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(2 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); + this->gen_const(32U, uimm)); Value* Xtmp0_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 91); + this->gen_sync(POST_SYNC, 91); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4565,18 +4656,19 @@ private: std::tuple __c_mv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.MV"); - this->gen_sync(iss::PRE_SYNC, 92); + this->gen_sync(PRE_SYNC, 92); - uint8_t fld_rs2_val = ((bit_sub<2,5>(instr))); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.MV x%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4584,10 +4676,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - Value* Xtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 92); + this->gen_sync(POST_SYNC, 92); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4597,17 +4689,18 @@ private: std::tuple __c_jr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.JR"); - this->gen_sync(iss::PRE_SYNC, 93); + this->gen_sync(PRE_SYNC, 93); - uint8_t fld_rs1_val = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.JR x%1$d"); - ins_fmter % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"), + fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4615,10 +4708,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - Value* PC_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* PC_val = this->gen_reg_load(rs1 + traits::X0, 0); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 93); + this->gen_sync(POST_SYNC, 93); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -4627,18 +4720,19 @@ private: std::tuple __c_add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.ADD"); - this->gen_sync(iss::PRE_SYNC, 94); + this->gen_sync(PRE_SYNC, 94); - uint8_t fld_rs2_val = ((bit_sub<2,5>(instr))); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.ADD x%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4647,11 +4741,11 @@ private: pc=pc+2; Value* Xtmp0_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rd_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rd + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 94); + this->gen_sync(POST_SYNC, 94); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4661,17 +4755,18 @@ private: std::tuple __c_jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.JALR"); - this->gen_sync(iss::PRE_SYNC, 95); + this->gen_sync(PRE_SYNC, 95); - uint8_t fld_rs1_val = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.JALR x%1$d"); - ins_fmter % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"), + fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4683,10 +4778,10 @@ private: cur_pc_val, this->gen_const(32U, 2)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(1 + traits::X0), false); - Value* PC_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* PC_val = this->gen_reg_load(rs1 + traits::X0, 0); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 95); + this->gen_sync(POST_SYNC, 95); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -4695,14 +4790,14 @@ private: std::tuple __c_ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.EBREAK"); - this->gen_sync(iss::PRE_SYNC, 96); + this->gen_sync(PRE_SYNC, 96); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("C.EBREAK"), + this->builder.CreateGlobalStringPtr("c.ebreak"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4711,7 +4806,7 @@ private: pc=pc+2; this->gen_raise_trap(0, 3); - this->gen_sync(iss::POST_SYNC, 96); + this->gen_sync(POST_SYNC, 96); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -4720,18 +4815,19 @@ private: std::tuple __c_swsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.SWSP"); - this->gen_sync(iss::PRE_SYNC, 97); + this->gen_sync(PRE_SYNC, 97); - uint8_t fld_rs2_val = ((bit_sub<2,5>(instr))); - uint8_t fld_uimm_val = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.SWSP x2+0x%1$05x, x%2$d"); - ins_fmter % (uint64_t)fld_uimm_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} x2+{uimm:#05x}, {rs2}", fmt::arg("mnemonic", "c.swsp"), + fmt::arg("uimm", uimm), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4741,14 +4837,14 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(2 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->gen_const(32U, uimm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 97); + this->gen_sync(POST_SYNC, 97); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4758,14 +4854,14 @@ private: std::tuple __dii(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("DII"); - this->gen_sync(iss::PRE_SYNC, 98); + this->gen_sync(PRE_SYNC, 98); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("DII"), + this->builder.CreateGlobalStringPtr("dii"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4775,7 +4871,7 @@ private: this->gen_raise_trap(0, 2); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 98); + this->gen_sync(POST_SYNC, 98); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4785,19 +4881,20 @@ private: std::tuple __flw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FLW"); - this->gen_sync(iss::PRE_SYNC, 99); + this->gen_sync(PRE_SYNC, 99); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FLW f%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, {imm}(x{rs1})", fmt::arg("mnemonic", "flw"), + fmt::arg("rd", rd), fmt::arg("imm", imm), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4807,13 +4904,13 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); Value* res_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -4824,10 +4921,10 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 99); + this->gen_sync(POST_SYNC, 99); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4837,19 +4934,20 @@ private: std::tuple __fsw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FSW"); - this->gen_sync(iss::PRE_SYNC, 100); + this->gen_sync(PRE_SYNC, 100); - int16_t fld_imm_val = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FSW f%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rs2}, {imm}(x{rs1})", fmt::arg("mnemonic", "fsw"), + fmt::arg("rs2", rs2), fmt::arg("imm", imm), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4859,11 +4957,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); Value* MEMtmp0_val = this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ); this->gen_write_mem( @@ -4871,7 +4969,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 100); + this->gen_sync(POST_SYNC, 100); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4881,21 +4979,22 @@ private: std::tuple __fmadd_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FMADD.S"); - this->gen_sync(iss::PRE_SYNC, 101); + this->gen_sync(PRE_SYNC, 101); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rs3_val = ((bit_sub<27,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FMADD.S x%1$d, f%2$d, f%3$d, f%4$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_rs3_val; + auto mnemonic = fmt::format( + "{mnemonic:10} x{rd}, f{rs1}, f{rs2}, f{rs3}", fmt::arg("mnemonic", "fmadd.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2), fmt::arg("rs3", rs3)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4905,15 +5004,15 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this->gen_reg_load(rs3 + traits::F0, 0), this-> get_type(32) ), this->gen_ext( @@ -4923,9 +5022,9 @@ private: this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -4934,7 +5033,7 @@ private: }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -4945,7 +5044,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -4956,7 +5055,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 101); + this->gen_sync(POST_SYNC, 101); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4966,21 +5065,22 @@ private: std::tuple __fmsub_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FMSUB.S"); - this->gen_sync(iss::PRE_SYNC, 102); + this->gen_sync(PRE_SYNC, 102); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rs3_val = ((bit_sub<27,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FMSUB.S x%1$d, f%2$d, f%3$d, f%4$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_rs3_val; + auto mnemonic = fmt::format( + "{mnemonic:10} x{rd}, f{rs1}, f{rs2}, f{rs3}", fmt::arg("mnemonic", "fmsub.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2), fmt::arg("rs3", rs3)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4990,15 +5090,15 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this->gen_reg_load(rs3 + traits::F0, 0), this-> get_type(32) ), this->gen_ext( @@ -5008,9 +5108,9 @@ private: this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -5019,7 +5119,7 @@ private: }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5030,7 +5130,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -5041,7 +5141,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 102); + this->gen_sync(POST_SYNC, 102); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5051,21 +5151,22 @@ private: std::tuple __fnmadd_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FNMADD.S"); - this->gen_sync(iss::PRE_SYNC, 103); + this->gen_sync(PRE_SYNC, 103); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rs3_val = ((bit_sub<27,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FNMADD.S x%1$d, f%2$d, f%3$d, f%4$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_rs3_val; + auto mnemonic = fmt::format( + "{mnemonic:10} x{rd}, f{rs1}, f{rs2}, f{rs3}", fmt::arg("mnemonic", "fnmadd.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2), fmt::arg("rs3", rs3)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5075,15 +5176,15 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this->gen_reg_load(rs3 + traits::F0, 0), this-> get_type(32) ), this->gen_ext( @@ -5093,9 +5194,9 @@ private: this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -5104,7 +5205,7 @@ private: }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5115,7 +5216,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -5126,7 +5227,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 103); + this->gen_sync(POST_SYNC, 103); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5136,21 +5237,22 @@ private: std::tuple __fnmsub_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FNMSUB.S"); - this->gen_sync(iss::PRE_SYNC, 104); + this->gen_sync(PRE_SYNC, 104); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rs3_val = ((bit_sub<27,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FNMSUB.S x%1$d, f%2$d, f%3$d, f%4$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_rs3_val; + auto mnemonic = fmt::format( + "{mnemonic:10} x{rd}, f{rs1}, f{rs2}, f{rs3}", fmt::arg("mnemonic", "fnmsub.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2), fmt::arg("rs3", rs3)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5160,15 +5262,15 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this->gen_reg_load(rs3 + traits::F0, 0), this-> get_type(32) ), this->gen_ext( @@ -5178,9 +5280,9 @@ private: this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -5189,7 +5291,7 @@ private: }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5200,7 +5302,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -5211,7 +5313,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 104); + this->gen_sync(POST_SYNC, 104); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5221,20 +5323,21 @@ private: std::tuple __fadd_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FADD.S"); - this->gen_sync(iss::PRE_SYNC, 105); + this->gen_sync(PRE_SYNC, 105); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FADD.S f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fadd.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5244,19 +5347,19 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fadd_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -5265,7 +5368,7 @@ private: }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5276,7 +5379,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -5287,7 +5390,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 105); + this->gen_sync(POST_SYNC, 105); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5297,20 +5400,21 @@ private: std::tuple __fsub_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FSUB.S"); - this->gen_sync(iss::PRE_SYNC, 106); + this->gen_sync(PRE_SYNC, 106); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FSUB.S f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fsub.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5320,19 +5424,19 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsub_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -5341,7 +5445,7 @@ private: }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5352,7 +5456,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -5363,7 +5467,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 106); + this->gen_sync(POST_SYNC, 106); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5373,20 +5477,21 @@ private: std::tuple __fmul_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FMUL.S"); - this->gen_sync(iss::PRE_SYNC, 107); + this->gen_sync(PRE_SYNC, 107); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FMUL.S f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fmul.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5396,19 +5501,19 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmul_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -5417,7 +5522,7 @@ private: }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5428,7 +5533,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -5439,7 +5544,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 107); + this->gen_sync(POST_SYNC, 107); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5449,20 +5554,21 @@ private: std::tuple __fdiv_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FDIV.S"); - this->gen_sync(iss::PRE_SYNC, 108); + this->gen_sync(PRE_SYNC, 108); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FDIV.S f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fdiv.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5472,19 +5578,19 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fdiv_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -5493,7 +5599,7 @@ private: }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5504,7 +5610,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -5515,7 +5621,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 108); + this->gen_sync(POST_SYNC, 108); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5525,19 +5631,20 @@ private: std::tuple __fsqrt_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FSQRT.S"); - this->gen_sync(iss::PRE_SYNC, 109); + this->gen_sync(PRE_SYNC, 109); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FSQRT.S f%1$d, f%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}", fmt::arg("mnemonic", "fsqrt.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5547,15 +5654,15 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsqrt_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -5564,7 +5671,7 @@ private: }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5575,7 +5682,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -5586,7 +5693,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 109); + this->gen_sync(POST_SYNC, 109); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5596,19 +5703,20 @@ private: std::tuple __fsgnj_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FSGNJ.S"); - this->gen_sync(iss::PRE_SYNC, 110); + this->gen_sync(PRE_SYNC, 110); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FSGNJ.S f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fsgnj.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5619,19 +5727,19 @@ private: Value* res_val = this->builder.CreateOr( this->builder.CreateAnd( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->gen_const(32U, 0x7fffffff)), this->builder.CreateAnd( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->gen_const(32U, 0x80000000))); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5642,10 +5750,10 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 110); + this->gen_sync(POST_SYNC, 110); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5655,19 +5763,20 @@ private: std::tuple __fsgnjn_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FSGNJN.S"); - this->gen_sync(iss::PRE_SYNC, 111); + this->gen_sync(PRE_SYNC, 111); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FSGNJN.S f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fsgnjn.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5678,19 +5787,19 @@ private: Value* res_val = this->builder.CreateOr( this->builder.CreateAnd( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->gen_const(32U, 0x7fffffff)), this->builder.CreateAnd( this->builder.CreateNot(this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) )), this->gen_const(32U, 0x80000000))); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5701,10 +5810,10 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 111); + this->gen_sync(POST_SYNC, 111); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5714,19 +5823,20 @@ private: std::tuple __fsgnjx_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FSGNJX.S"); - this->gen_sync(iss::PRE_SYNC, 112); + this->gen_sync(PRE_SYNC, 112); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FSGNJX.S f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fsgnjx.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5736,18 +5846,18 @@ private: Value* res_val = this->builder.CreateXor( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateAnd( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->gen_const(32U, 0x80000000))); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5758,10 +5868,10 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 112); + this->gen_sync(POST_SYNC, 112); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5771,19 +5881,20 @@ private: std::tuple __fmin_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FMIN.S"); - this->gen_sync(iss::PRE_SYNC, 113); + this->gen_sync(PRE_SYNC, 113); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FMIN.S f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fmin.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5793,11 +5904,11 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsel_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->gen_ext( @@ -5807,7 +5918,7 @@ private: }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5818,7 +5929,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -5829,7 +5940,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 113); + this->gen_sync(POST_SYNC, 113); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5839,19 +5950,20 @@ private: std::tuple __fmax_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FMAX.S"); - this->gen_sync(iss::PRE_SYNC, 114); + this->gen_sync(PRE_SYNC, 114); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FMAX.S f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fmax.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5861,11 +5973,11 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsel_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->gen_ext( @@ -5875,7 +5987,7 @@ private: }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -5886,7 +5998,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -5897,7 +6009,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 114); + this->gen_sync(POST_SYNC, 114); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5907,19 +6019,20 @@ private: std::tuple __fcvt_w_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FCVT.W.S"); - this->gen_sync(iss::PRE_SYNC, 115); + this->gen_sync(PRE_SYNC, 115); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FCVT.W.S x%1$d, f%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} x{rd}, f{rs1}", fmt::arg("mnemonic", "fcvt.w.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5930,18 +6043,18 @@ private: Value* Xtmp0_val = this->gen_ext( this->builder.CreateCall(this->mod->getFunction("fcvt_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->gen_ext( this->gen_const(64U, 0LL), 32, false), - this->gen_const(8U, fld_rm_val) + this->gen_const(8U, rm) }), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( @@ -5951,7 +6064,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 115); + this->gen_sync(POST_SYNC, 115); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -5961,19 +6074,20 @@ private: std::tuple __fcvt_wu_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FCVT.WU.S"); - this->gen_sync(iss::PRE_SYNC, 116); + this->gen_sync(PRE_SYNC, 116); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FCVT.WU.S x%1$d, f%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} x{rd}, f{rs1}", fmt::arg("mnemonic", "fcvt.wu.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -5984,18 +6098,18 @@ private: Value* Xtmp0_val = this->gen_ext( this->builder.CreateCall(this->mod->getFunction("fcvt_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->gen_ext( this->gen_const(64U, 1LL), 32, false), - this->gen_const(8U, fld_rm_val) + this->gen_const(8U, rm) }), 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( @@ -6005,7 +6119,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 116); + this->gen_sync(POST_SYNC, 116); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6015,19 +6129,20 @@ private: std::tuple __feq_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FEQ.S"); - this->gen_sync(iss::PRE_SYNC, 117); + this->gen_sync(PRE_SYNC, 117); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FEQ.S x%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} x{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "feq.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6037,11 +6152,11 @@ private: Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fcmp_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->gen_ext( @@ -6049,7 +6164,7 @@ private: 32, false) }); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( @@ -6059,7 +6174,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 117); + this->gen_sync(POST_SYNC, 117); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6069,19 +6184,20 @@ private: std::tuple __flt_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FLT.S"); - this->gen_sync(iss::PRE_SYNC, 118); + this->gen_sync(PRE_SYNC, 118); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FLT.S x%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} x{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "flt.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6091,11 +6207,11 @@ private: Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fcmp_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->gen_ext( @@ -6103,7 +6219,7 @@ private: 32, false) }); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( @@ -6113,7 +6229,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 118); + this->gen_sync(POST_SYNC, 118); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6123,19 +6239,20 @@ private: std::tuple __fle_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FLE.S"); - this->gen_sync(iss::PRE_SYNC, 119); + this->gen_sync(PRE_SYNC, 119); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FLE.S x%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} x{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fle.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6145,11 +6262,11 @@ private: Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fcmp_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ), this->gen_ext( @@ -6157,7 +6274,7 @@ private: 32, false) }); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( @@ -6167,7 +6284,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 119); + this->gen_sync(POST_SYNC, 119); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6177,18 +6294,19 @@ private: std::tuple __fclass_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FCLASS.S"); - this->gen_sync(iss::PRE_SYNC, 120); + this->gen_sync(PRE_SYNC, 120); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FCLASS.S x%1$d, f%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} x{rd}, f{rs1}", fmt::arg("mnemonic", "fclass.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6198,13 +6316,13 @@ private: Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fclass_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ) }); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 120); + this->gen_sync(POST_SYNC, 120); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6214,19 +6332,20 @@ private: std::tuple __fcvt_s_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FCVT.S.W"); - this->gen_sync(iss::PRE_SYNC, 121); + this->gen_sync(PRE_SYNC, 121); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FCVT.S.W f%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, x{rs1}", fmt::arg("mnemonic", "fcvt.s.w"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6236,18 +6355,18 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fcvt_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this-> get_type(32) ), this->gen_ext( this->gen_const(64U, 2LL), 32, false), - this->gen_const(8U, fld_rm_val) + this->gen_const(8U, rm) }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -6258,10 +6377,10 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 121); + this->gen_sync(POST_SYNC, 121); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6271,19 +6390,20 @@ private: std::tuple __fcvt_s_wu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FCVT.S.WU"); - this->gen_sync(iss::PRE_SYNC, 122); + this->gen_sync(PRE_SYNC, 122); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FCVT.S.WU f%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, x{rs1}", fmt::arg("mnemonic", "fcvt.s.wu"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6293,18 +6413,18 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fcvt_s"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this-> get_type(32) ), this->gen_ext( this->gen_const(64U, 3LL), 32, false), - this->gen_const(8U, fld_rm_val) + this->gen_const(8U, rm) }); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -6315,10 +6435,10 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 122); + this->gen_sync(POST_SYNC, 122); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6328,18 +6448,19 @@ private: std::tuple __fmv_x_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FMV.X.W"); - this->gen_sync(iss::PRE_SYNC, 123); + this->gen_sync(PRE_SYNC, 123); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FMV.X.W x%1$d, f%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} x{rd}, f{rs1}", fmt::arg("mnemonic", "fmv.x.w"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6349,14 +6470,14 @@ private: Value* Xtmp0_val = this->gen_ext( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 123); + this->gen_sync(POST_SYNC, 123); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6366,18 +6487,19 @@ private: std::tuple __fmv_w_x(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FMV.W.X"); - this->gen_sync(iss::PRE_SYNC, 124); + this->gen_sync(PRE_SYNC, 124); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FMV.W.X f%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, x{rs1}", fmt::arg("mnemonic", "fmv.w.x"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6386,8 +6508,8 @@ private: pc=pc+4; if(64 == 32){ - Value* Ftmp0_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = this->gen_reg_load(rs1 + traits::X0, 0); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -6395,13 +6517,13 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 32)), this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 124); + this->gen_sync(POST_SYNC, 124); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6411,19 +6533,20 @@ private: std::tuple __c_flw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.FLW"); - this->gen_sync(iss::PRE_SYNC, 125); + this->gen_sync(PRE_SYNC, 125); - uint8_t fld_rd_val = ((bit_sub<2,3>(instr))); - uint8_t fld_uimm_val = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.FLW f(8+%1$d), %2%(x(8+%3$d))"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_uimm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rd}), {uimm}({rs1})", fmt::arg("mnemonic", "c.flw"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6432,12 +6555,12 @@ private: pc=pc+2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rs1_val + 8 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); + this->gen_reg_load(rs1 + 8 + traits::X0, 0), + this->gen_const(32U, uimm)); Value* res_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + 8 + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + 8 + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -6448,10 +6571,10 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + 8 + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + 8 + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 125); + this->gen_sync(POST_SYNC, 125); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6461,19 +6584,20 @@ private: std::tuple __c_fsw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.FSW"); - this->gen_sync(iss::PRE_SYNC, 126); + this->gen_sync(PRE_SYNC, 126); - uint8_t fld_rs2_val = ((bit_sub<2,3>(instr))); - uint8_t fld_uimm_val = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.FSW f(8+%1$d), %2%(x(8+%3$d))"); - ins_fmter % (uint64_t)fld_rs2_val % (uint64_t)fld_uimm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rs2}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fsw"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6482,10 +6606,10 @@ private: pc=pc+2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rs1_val + 8 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); + this->gen_reg_load(rs1 + 8 + traits::X0, 0), + this->gen_const(32U, uimm)); Value* MEMtmp0_val = this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + 8 + traits::F0, 0), + this->gen_reg_load(rs2 + 8 + traits::F0, 0), this-> get_type(32) ); this->gen_write_mem( @@ -6493,7 +6617,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 126); + this->gen_sync(POST_SYNC, 126); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6503,18 +6627,19 @@ private: std::tuple __c_flwsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.FLWSP"); - this->gen_sync(iss::PRE_SYNC, 127); + this->gen_sync(PRE_SYNC, 127); - uint8_t fld_uimm_val = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.FLWSP f%1$d, %2%(x2)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_uimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, {uimm}(x2)", fmt::arg("mnemonic", "c.flwsp"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6524,11 +6649,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(2 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); + this->gen_const(32U, uimm)); Value* res_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); if(64 == 32){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -6539,10 +6664,10 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 127); + this->gen_sync(POST_SYNC, 127); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6552,18 +6677,19 @@ private: std::tuple __c_fswsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.FSWSP"); - this->gen_sync(iss::PRE_SYNC, 128); + this->gen_sync(PRE_SYNC, 128); - uint8_t fld_rs2_val = ((bit_sub<2,5>(instr))); - uint8_t fld_uimm_val = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.FSWSP f%1$d, %2%(x2), "); - ins_fmter % (uint64_t)fld_rs2_val % (uint64_t)fld_uimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rs2}, {uimm}(x2), ", fmt::arg("mnemonic", "c.fswsp"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6573,9 +6699,9 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(2 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); + this->gen_const(32U, uimm)); Value* MEMtmp0_val = this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(32) ); this->gen_write_mem( @@ -6583,7 +6709,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 128); + this->gen_sync(POST_SYNC, 128); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6593,19 +6719,20 @@ private: std::tuple __fld(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FLD"); - this->gen_sync(iss::PRE_SYNC, 129); + this->gen_sync(PRE_SYNC, 129); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FLD f%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, {imm}({rs1})", fmt::arg("mnemonic", "fld"), + fmt::arg("rd", rd), fmt::arg("imm", imm), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6615,13 +6742,13 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); Value* res_val = this->gen_read_mem(traits::MEM, offs_val, 64/8); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -6629,10 +6756,10 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 129); + this->gen_sync(POST_SYNC, 129); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6642,19 +6769,20 @@ private: std::tuple __fsd(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FSD"); - this->gen_sync(iss::PRE_SYNC, 130); + this->gen_sync(PRE_SYNC, 130); - int16_t fld_imm_val = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FSD f%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rs2}, {imm}({rs1})", fmt::arg("mnemonic", "fsd"), + fmt::arg("rs2", rs2), fmt::arg("imm", imm), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6664,11 +6792,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); Value* MEMtmp0_val = this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ); this->gen_write_mem( @@ -6676,7 +6804,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 130); + this->gen_sync(POST_SYNC, 130); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6686,21 +6814,22 @@ private: std::tuple __fmadd_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FMADD.D"); - this->gen_sync(iss::PRE_SYNC, 131); + this->gen_sync(PRE_SYNC, 131); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rs3_val = ((bit_sub<27,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FMADD.D x%1$d, f%2$d, f%3$d, f%4$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_rs3_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}, f{rs2}, f{rs3}", fmt::arg("mnemonic", "fmadd.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2), fmt::arg("rs3", rs3)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6710,15 +6839,15 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this->gen_reg_load(rs3 + traits::F0, 0), this-> get_type(64) ), this->gen_ext( @@ -6728,9 +6857,9 @@ private: this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -6739,7 +6868,7 @@ private: }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -6747,7 +6876,7 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -6758,7 +6887,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 131); + this->gen_sync(POST_SYNC, 131); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6768,21 +6897,22 @@ private: std::tuple __fmsub_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FMSUB.D"); - this->gen_sync(iss::PRE_SYNC, 132); + this->gen_sync(PRE_SYNC, 132); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rs3_val = ((bit_sub<27,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FMSUB.D x%1$d, f%2$d, f%3$d, f%4$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_rs3_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}, f{rs2}, f{rs3}", fmt::arg("mnemonic", "fmsub.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2), fmt::arg("rs3", rs3)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6792,15 +6922,15 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this->gen_reg_load(rs3 + traits::F0, 0), this-> get_type(64) ), this->gen_ext( @@ -6810,9 +6940,9 @@ private: this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -6821,7 +6951,7 @@ private: }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -6829,7 +6959,7 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -6840,7 +6970,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 132); + this->gen_sync(POST_SYNC, 132); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6850,21 +6980,22 @@ private: std::tuple __fnmadd_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FNMADD.D"); - this->gen_sync(iss::PRE_SYNC, 133); + this->gen_sync(PRE_SYNC, 133); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rs3_val = ((bit_sub<27,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FNMADD.D x%1$d, f%2$d, f%3$d, f%4$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_rs3_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}, f{rs2}, f{rs3}", fmt::arg("mnemonic", "fnmadd.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2), fmt::arg("rs3", rs3)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6874,15 +7005,15 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this->gen_reg_load(rs3 + traits::F0, 0), this-> get_type(64) ), this->gen_ext( @@ -6892,9 +7023,9 @@ private: this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -6903,7 +7034,7 @@ private: }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -6911,7 +7042,7 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -6922,7 +7053,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 133); + this->gen_sync(POST_SYNC, 133); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -6932,21 +7063,22 @@ private: std::tuple __fnmsub_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FNMSUB.D"); - this->gen_sync(iss::PRE_SYNC, 134); + this->gen_sync(PRE_SYNC, 134); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rs3_val = ((bit_sub<27,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rs3 = ((bit_sub<27,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FNMSUB.D x%1$d, f%2$d, f%3$d, f%4$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_rs3_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}, f{rs2}, f{rs3}", fmt::arg("mnemonic", "fnmsub.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2), fmt::arg("rs3", rs3)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -6956,15 +7088,15 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this->gen_reg_load(rs3 + traits::F0, 0), this-> get_type(64) ), this->gen_ext( @@ -6974,9 +7106,9 @@ private: this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -6985,7 +7117,7 @@ private: }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -6993,7 +7125,7 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -7004,7 +7136,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 134); + this->gen_sync(POST_SYNC, 134); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7014,20 +7146,21 @@ private: std::tuple __fadd_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FADD.D"); - this->gen_sync(iss::PRE_SYNC, 135); + this->gen_sync(PRE_SYNC, 135); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FADD.D x%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fadd.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7037,19 +7170,19 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fadd_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -7058,7 +7191,7 @@ private: }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -7066,7 +7199,7 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -7077,7 +7210,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 135); + this->gen_sync(POST_SYNC, 135); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7087,20 +7220,21 @@ private: std::tuple __fsub_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FSUB.D"); - this->gen_sync(iss::PRE_SYNC, 136); + this->gen_sync(PRE_SYNC, 136); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FSUB.D x%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fsub.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7110,19 +7244,19 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsub_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -7131,7 +7265,7 @@ private: }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -7139,7 +7273,7 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -7150,7 +7284,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 136); + this->gen_sync(POST_SYNC, 136); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7160,20 +7294,21 @@ private: std::tuple __fmul_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FMUL.D"); - this->gen_sync(iss::PRE_SYNC, 137); + this->gen_sync(PRE_SYNC, 137); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FMUL.D x%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fmul.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7183,19 +7318,19 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmul_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -7204,7 +7339,7 @@ private: }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -7212,7 +7347,7 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -7223,7 +7358,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 137); + this->gen_sync(POST_SYNC, 137); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7233,20 +7368,21 @@ private: std::tuple __fdiv_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FDIV.D"); - this->gen_sync(iss::PRE_SYNC, 138); + this->gen_sync(PRE_SYNC, 138); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FDIV.D x%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fdiv.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7256,19 +7392,19 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fdiv_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -7277,7 +7413,7 @@ private: }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -7285,7 +7421,7 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -7296,7 +7432,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 138); + this->gen_sync(POST_SYNC, 138); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7306,19 +7442,20 @@ private: std::tuple __fsqrt_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FSQRT.D"); - this->gen_sync(iss::PRE_SYNC, 139); + this->gen_sync(PRE_SYNC, 139); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FSQRT.D x%1$d, f%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}", fmt::arg("mnemonic", "fsqrt.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7328,15 +7465,15 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsqrt_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->gen_const(8U, 7)), - this->gen_const(8U, fld_rm_val), + this->gen_const(8U, rm), this->builder.CreateTrunc( this->gen_reg_load(traits::FCSR, 0), this-> get_type(8) @@ -7345,7 +7482,7 @@ private: }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -7353,7 +7490,7 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -7364,7 +7501,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 139); + this->gen_sync(POST_SYNC, 139); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7374,19 +7511,20 @@ private: std::tuple __fsgnj_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FSGNJ.D"); - this->gen_sync(iss::PRE_SYNC, 140); + this->gen_sync(PRE_SYNC, 140); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FSGNJ.D f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fsgnj.d"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7397,19 +7535,19 @@ private: Value* res_val = this->builder.CreateOr( this->builder.CreateAnd( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->gen_const(64U, 0x7fffffff)), this->builder.CreateAnd( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->gen_const(64U, 0x80000000))); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -7417,10 +7555,10 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 140); + this->gen_sync(POST_SYNC, 140); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7430,19 +7568,20 @@ private: std::tuple __fsgnjn_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FSGNJN.D"); - this->gen_sync(iss::PRE_SYNC, 141); + this->gen_sync(PRE_SYNC, 141); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FSGNJN.D f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fsgnjn.d"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7453,19 +7592,19 @@ private: Value* res_val = this->builder.CreateOr( this->builder.CreateAnd( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->gen_const(64U, 0x7fffffff)), this->builder.CreateAnd( this->builder.CreateNot(this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) )), this->gen_const(64U, 0x80000000))); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -7473,10 +7612,10 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 141); + this->gen_sync(POST_SYNC, 141); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7486,19 +7625,20 @@ private: std::tuple __fsgnjx_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FSGNJX.D"); - this->gen_sync(iss::PRE_SYNC, 142); + this->gen_sync(PRE_SYNC, 142); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FSGNJX.D f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fsgnjx.d"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7508,18 +7648,18 @@ private: Value* res_val = this->builder.CreateXor( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateAnd( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->gen_const(64U, 0x80000000))); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -7527,10 +7667,10 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 142); + this->gen_sync(POST_SYNC, 142); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7540,19 +7680,20 @@ private: std::tuple __fmin_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FMIN.D"); - this->gen_sync(iss::PRE_SYNC, 143); + this->gen_sync(PRE_SYNC, 143); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FMIN.D f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fmin.d"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7562,11 +7703,11 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsel_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->gen_ext( @@ -7576,7 +7717,7 @@ private: }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -7584,7 +7725,7 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -7595,7 +7736,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 143); + this->gen_sync(POST_SYNC, 143); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7605,19 +7746,20 @@ private: std::tuple __fmax_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FMAX.D"); - this->gen_sync(iss::PRE_SYNC, 144); + this->gen_sync(PRE_SYNC, 144); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FMAX.D f%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fmax.d"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7627,11 +7769,11 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsel_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->gen_ext( @@ -7641,7 +7783,7 @@ private: }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -7649,7 +7791,7 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); @@ -7660,7 +7802,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 144); + this->gen_sync(POST_SYNC, 144); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7670,19 +7812,20 @@ private: std::tuple __fcvt_s_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FCVT.S.D"); - this->gen_sync(iss::PRE_SYNC, 145); + this->gen_sync(PRE_SYNC, 145); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FCVT.S.D f%1$d, f%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}", fmt::arg("mnemonic", "fcvt.s.d"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7691,8 +7834,8 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fconv_d2f"), std::vector{ - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this->gen_const(8U, fld_rm_val) + this->gen_reg_load(rs1 + traits::F0, 0), + this->gen_const(8U, rm) }); uint64_t upper_val = - 1; Value* Ftmp0_val = this->builder.CreateOr( @@ -7703,9 +7846,9 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 145); + this->gen_sync(POST_SYNC, 145); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7715,19 +7858,20 @@ private: std::tuple __fcvt_d_s(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FCVT.D.S"); - this->gen_sync(iss::PRE_SYNC, 146); + this->gen_sync(PRE_SYNC, 146); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FCVT.D.S f%1$d, f%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, f{rs1}", fmt::arg("mnemonic", "fcvt.d.s"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7737,14 +7881,14 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fconv_f2d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(32) ), - this->gen_const(8U, fld_rm_val) + this->gen_const(8U, rm) }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -7752,10 +7896,10 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 146); + this->gen_sync(POST_SYNC, 146); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7765,19 +7909,20 @@ private: std::tuple __feq_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FEQ.D"); - this->gen_sync(iss::PRE_SYNC, 147); + this->gen_sync(PRE_SYNC, 147); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FEQ.D x%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "feq.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7787,11 +7932,11 @@ private: Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fcmp_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->gen_ext( @@ -7799,7 +7944,7 @@ private: 32, false) }); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( @@ -7809,7 +7954,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 147); + this->gen_sync(POST_SYNC, 147); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7819,19 +7964,20 @@ private: std::tuple __flt_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FLT.D"); - this->gen_sync(iss::PRE_SYNC, 148); + this->gen_sync(PRE_SYNC, 148); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FLT.D x%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "flt.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7841,11 +7987,11 @@ private: Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fcmp_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->gen_ext( @@ -7853,7 +7999,7 @@ private: 32, false) }); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( @@ -7863,7 +8009,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 148); + this->gen_sync(POST_SYNC, 148); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7873,19 +8019,20 @@ private: std::tuple __fle_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FLE.D"); - this->gen_sync(iss::PRE_SYNC, 149); + this->gen_sync(PRE_SYNC, 149); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FLE.D x%1$d, f%2$d, f%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}, f{rs2}", fmt::arg("mnemonic", "fle.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1), fmt::arg("rs2", rs2)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7895,11 +8042,11 @@ private: Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fcmp_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ), this->gen_ext( @@ -7907,7 +8054,7 @@ private: 32, false) }); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( @@ -7917,7 +8064,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 149); + this->gen_sync(POST_SYNC, 149); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7927,18 +8074,19 @@ private: std::tuple __fclass_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FCLASS.D"); - this->gen_sync(iss::PRE_SYNC, 150); + this->gen_sync(PRE_SYNC, 150); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FCLASS.D x%1$d, f%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}", fmt::arg("mnemonic", "fclass.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7948,13 +8096,13 @@ private: Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fclass_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ) }); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 150); + this->gen_sync(POST_SYNC, 150); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -7964,19 +8112,20 @@ private: std::tuple __fcvt_w_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FCVT.W.D"); - this->gen_sync(iss::PRE_SYNC, 151); + this->gen_sync(PRE_SYNC, 151); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FCVT.W.D x%1$d, f%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}", fmt::arg("mnemonic", "fcvt.w.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -7987,18 +8136,18 @@ private: Value* Xtmp0_val = this->gen_ext( this->builder.CreateCall(this->mod->getFunction("fcvt_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->gen_ext( this->gen_const(64U, 0LL), 32, false), - this->gen_const(8U, fld_rm_val) + this->gen_const(8U, rm) }), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( @@ -8008,7 +8157,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 151); + this->gen_sync(POST_SYNC, 151); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -8018,19 +8167,20 @@ private: std::tuple __fcvt_wu_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FCVT.WU.D"); - this->gen_sync(iss::PRE_SYNC, 152); + this->gen_sync(PRE_SYNC, 152); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FCVT.WU.D x%1$d, f%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, f{rs1}", fmt::arg("mnemonic", "fcvt.wu.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -8041,18 +8191,18 @@ private: Value* Xtmp0_val = this->gen_ext( this->builder.CreateCall(this->mod->getFunction("fcvt_d"), std::vector{ this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_reg_load(rs1 + traits::F0, 0), this-> get_type(64) ), this->gen_ext( this->gen_const(64U, 1LL), 32, false), - this->gen_const(8U, fld_rm_val) + this->gen_const(8U, rm) }), 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( @@ -8062,7 +8212,7 @@ private: flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 152); + this->gen_sync(POST_SYNC, 152); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -8072,19 +8222,20 @@ private: std::tuple __fcvt_d_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FCVT.D.W"); - this->gen_sync(iss::PRE_SYNC, 153); + this->gen_sync(PRE_SYNC, 153); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FCVT.D.W f%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, {rs1}", fmt::arg("mnemonic", "fcvt.d.w"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -8094,18 +8245,18 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fcvt_d"), std::vector{ this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), this->gen_ext( this->gen_const(64U, 2LL), 32, false), - this->gen_const(8U, fld_rm_val) + this->gen_const(8U, rm) }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -8113,10 +8264,10 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 153); + this->gen_sync(POST_SYNC, 153); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -8126,19 +8277,20 @@ private: std::tuple __fcvt_d_wu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FCVT.D.WU"); - this->gen_sync(iss::PRE_SYNC, 154); + this->gen_sync(PRE_SYNC, 154); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rm_val = ((bit_sub<12,3>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rm = ((bit_sub<12,3>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("FCVT.D.WU f%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, {rs1}", fmt::arg("mnemonic", "fcvt.d.wu"), + fmt::arg("rd", rd), fmt::arg("rs1", rs1)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -8148,18 +8300,18 @@ private: Value* res_val = this->builder.CreateCall(this->mod->getFunction("fcvt_d"), std::vector{ this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, false), this->gen_ext( this->gen_const(64U, 3LL), 32, false), - this->gen_const(8U, fld_rm_val) + this->gen_const(8U, rm) }); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -8167,10 +8319,10 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 154); + this->gen_sync(POST_SYNC, 154); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -8180,19 +8332,20 @@ private: std::tuple __c_fld(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.FLD"); - this->gen_sync(iss::PRE_SYNC, 155); + this->gen_sync(PRE_SYNC, 155); - uint8_t fld_rd_val = ((bit_sub<2,3>(instr))); - uint8_t fld_uimm_val = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.FLD f(8+%1$d), %2%(x(8+%3$d))"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_uimm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rd}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fld"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -8201,12 +8354,12 @@ private: pc=pc+2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rs1_val + 8 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); + this->gen_reg_load(rs1 + 8 + traits::X0, 0), + this->gen_const(32U, uimm)); Value* res_val = this->gen_read_mem(traits::MEM, offs_val, 64/8); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + 8 + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + 8 + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -8214,10 +8367,10 @@ private: this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + 8 + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + 8 + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 155); + this->gen_sync(POST_SYNC, 155); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -8227,19 +8380,20 @@ private: std::tuple __c_fsd(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.FSD"); - this->gen_sync(iss::PRE_SYNC, 156); + this->gen_sync(PRE_SYNC, 156); - uint8_t fld_rs2_val = ((bit_sub<2,3>(instr))); - uint8_t fld_uimm_val = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.FSD f(8+%1$d), %2%(x(8+%3$d))"); - ins_fmter % (uint64_t)fld_rs2_val % (uint64_t)fld_uimm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f(8+{rs2}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fsd"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -8248,10 +8402,10 @@ private: pc=pc+2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rs1_val + 8 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); + this->gen_reg_load(rs1 + 8 + traits::X0, 0), + this->gen_const(32U, uimm)); Value* MEMtmp0_val = this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + 8 + traits::F0, 0), + this->gen_reg_load(rs2 + 8 + traits::F0, 0), this-> get_type(64) ); this->gen_write_mem( @@ -8259,7 +8413,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 156); + this->gen_sync(POST_SYNC, 156); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -8269,18 +8423,19 @@ private: std::tuple __c_fldsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.FLDSP"); - this->gen_sync(iss::PRE_SYNC, 157); + this->gen_sync(PRE_SYNC, 157); - uint16_t fld_uimm_val = ((bit_sub<2,3>(instr) << 6) | (bit_sub<5,2>(instr) << 3) | (bit_sub<12,1>(instr) << 5)); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); + uint16_t uimm = ((bit_sub<2,3>(instr) << 6) | (bit_sub<5,2>(instr) << 3) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.FLDSP f%1$d, %2%(x2)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_uimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rd}, {uimm}(x2)", fmt::arg("mnemonic", "c.fldsp"), + fmt::arg("rd", rd), fmt::arg("uimm", uimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -8290,11 +8445,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(2 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); + this->gen_const(32U, uimm)); Value* res_val = this->gen_read_mem(traits::MEM, offs_val, 64/8); if(64 == 64){ Value* Ftmp0_val = res_val; - this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(rd + traits::F0), false); } else { uint64_t upper_val = - 1; Value* Ftmp1_val = this->builder.CreateOr( @@ -8305,10 +8460,10 @@ private: res_val, 64, false)); - this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(rd + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 157); + this->gen_sync(POST_SYNC, 157); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -8318,18 +8473,19 @@ private: std::tuple __c_fsdsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.FSDSP"); - this->gen_sync(iss::PRE_SYNC, 158); + this->gen_sync(PRE_SYNC, 158); - uint8_t fld_rs2_val = ((bit_sub<2,5>(instr))); - uint16_t fld_uimm_val = ((bit_sub<7,3>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint16_t uimm = ((bit_sub<7,3>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.FSDSP f%1$d, %2%(x2), "); - ins_fmter % (uint64_t)fld_rs2_val % (uint64_t)fld_uimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} f{rs2}, {uimm}(x2), ", fmt::arg("mnemonic", "c.fsdsp"), + fmt::arg("rs2", rs2), fmt::arg("uimm", uimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -8339,9 +8495,9 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(2 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); + this->gen_const(32U, uimm)); Value* MEMtmp0_val = this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this->gen_reg_load(rs2 + traits::F0, 0), this-> get_type(64) ); this->gen_write_mem( @@ -8349,7 +8505,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 158); + this->gen_sync(POST_SYNC, 158); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -8358,8 +8514,7 @@ private: /**************************************************************************** * end opcode definitions ****************************************************************************/ - std::tuple illegal_intruction(virt_addr_t &pc, code_word_t instr, - BasicBlock *bb) { + std::tuple illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) { this->gen_sync(iss::PRE_SYNC, instr_descr.size()); this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits::NEXT_PC), true), get_reg_ptr(traits::PC), true); @@ -8403,7 +8558,7 @@ vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, const typename traits::addr_t upper_bits = ~traits::PGMASK; phys_addr_t paddr(pc); try { - uint8_t *const data = (uint8_t *)&insn; + auto *const data = (uint8_t *)&insn; paddr = this->core.v2p(pc); if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary auto res = this->core.read(paddr, 2, data); @@ -8441,9 +8596,7 @@ template void vm_impl::gen_raise_trap(uint16_t trap_id, ui } template void vm_impl::gen_leave_trap(unsigned lvl) { - std::vector args{ - this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)), - }; + std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) }; this->builder.CreateCall(this->mod->getFunction("leave_trap"), args); auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); @@ -8451,20 +8604,17 @@ template void vm_impl::gen_leave_trap(unsigned lvl) { } template void vm_impl::gen_wait(unsigned type) { - std::vector args{ - this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)), - }; + std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) }; this->builder.CreateCall(this->mod->getFunction("wait"), args); } template void vm_impl::gen_trap_behavior(BasicBlock *trap_blk) { this->builder.SetInsertPoint(trap_blk); auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits::TRAP_STATE), true); - this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); - std::vector args{ - this->core_ptr, - this->adj_to64(trap_state_val), - this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits::PC), false))}; + this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), + get_reg_ptr(traits::LAST_BRANCH), false); + std::vector args{this->core_ptr, this->adj_to64(trap_state_val), + this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits::PC), false))}; this->builder.CreateCall(this->mod->getFunction("enter_trap"), args); auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateRet(trap_addr_val); @@ -8482,10 +8632,9 @@ template inline void vm_impl::gen_trap_check(BasicBlock *b template <> std::unique_ptr create(arch::rv32gc *core, unsigned short port, bool dump) { - std::unique_ptr> ret = - std::make_unique>(*core, dump); - if (port != 0) debugger::server::run_server(ret.get(), port); - return ret; + auto ret = new rv32gc::vm_impl(*core, dump); + if (port != 0) debugger::server::run_server(ret, port); + return std::unique_ptr(ret); } } // namespace iss diff --git a/riscv/src/internal/vm_rv32imac.cpp b/riscv/src/internal/vm_rv32imac.cpp index c8efdc1..c867a5e 100644 --- a/riscv/src/internal/vm_rv32imac.cpp +++ b/riscv/src/internal/vm_rv32imac.cpp @@ -30,15 +30,15 @@ * *******************************************************************************/ -#include #include +#include #include #include #include #include #include -#include +#include #include #include @@ -80,23 +80,24 @@ public: protected: using vm_base::get_reg_ptr; - template inline llvm::ConstantInt *size(T type) { - return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits())); + inline const char *name(size_t index){return traits::reg_aliases.at(index);} + + template inline ConstantInt *size(T type) { + return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits())); } - void setup_module(llvm::Module *m) override { + void setup_module(Module* m) override { super::setup_module(m); - vm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE); + iss::vm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE); } - inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal, unsigned size) { + inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) { return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size)); } - std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, - llvm::BasicBlock *) override; + std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override; - void gen_leave_behavior(llvm::BasicBlock *leave_blk) override; + void gen_leave_behavior(BasicBlock *leave_blk) override; void gen_raise_trap(uint16_t trap_id, uint16_t cause); @@ -104,17 +105,17 @@ protected: void gen_wait(unsigned type); - void gen_trap_behavior(llvm::BasicBlock *) override; + void gen_trap_behavior(BasicBlock *) override; - void gen_trap_check(llvm::BasicBlock *bb); + void gen_trap_check(BasicBlock *bb); - inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) { + inline Value *gen_reg_load(unsigned i, unsigned level = 0) { return this->builder.CreateLoad(get_reg_ptr(i), false); } inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) { - llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), - this->get_type(traits::XLEN)); + Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), + this->get_type(traits::XLEN)); this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true); } @@ -125,17 +126,17 @@ protected: enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) }; using this_class = vm_impl; - using compile_func = std::tuple (this_class::*)(virt_addr_t &pc, - code_word_t instr, - llvm::BasicBlock *bb); + using compile_func = std::tuple (this_class::*)(virt_addr_t &pc, + code_word_t instr, + BasicBlock *bb); std::array lut; std::array lut_00, lut_01, lut_10; std::array lut_11; - std::array qlut; + std::array qlut; - std::array lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}}; + std::array lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}}; void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[], compile_func f) { @@ -186,7 +187,7 @@ private: }; const std::array instr_descr = {{ - /* entries are: size, valid value, valid mask, function ptr */ + /* entries are: size, valid value, valid mask, function ptr */ /* instruction LUI */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, /* instruction AUIPC */ @@ -389,21 +390,22 @@ private: /* instruction definitions */ /* instruction 0: LUI */ - std::tuple __lui(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LUI"); - this->gen_sync(iss::PRE_SYNC, 0); + this->gen_sync(PRE_SYNC, 0); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - int32_t fld_imm_val = signextend((bit_sub<12,20>(instr) << 12)); + uint8_t rd = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LUI x%1$d, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -411,33 +413,34 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ - Value* Xtmp0_val = this->gen_const(32U, fld_imm_val); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + if(rd != 0){ + Value* Xtmp0_val = this->gen_const(32U, imm); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 0); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 0); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 1: AUIPC */ - std::tuple __auipc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __auipc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AUIPC"); - this->gen_sync(iss::PRE_SYNC, 1); + this->gen_sync(PRE_SYNC, 1); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - int32_t fld_imm_val = signextend((bit_sub<12,20>(instr) << 12)); + uint8_t rd = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AUIPC x%1%, 0x%2$08x"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -445,37 +448,38 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 1); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 1); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 2: JAL */ - std::tuple __jal(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("JAL"); - this->gen_sync(iss::PRE_SYNC, 2); + this->gen_sync(PRE_SYNC, 2); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - int32_t fld_imm_val = signextend((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + uint8_t rd = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("JAL x%1$d, 0x%2$x"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -483,42 +487,43 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* PC_val = this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 2); + this->gen_sync(POST_SYNC, 2); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 3: JALR */ - std::tuple __jalr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("JALR"); - this->gen_sync(iss::PRE_SYNC, 3); + this->gen_sync(PRE_SYNC, 3); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("JALR x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -528,16 +533,16 @@ private: Value* new_pc_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); Value* align_val = this->builder.CreateAnd( new_pc_val, this->gen_const(32U, 0x1)); { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + BasicBlock* bb_else = BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_NE, @@ -552,11 +557,11 @@ private: this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* PC_val = this->builder.CreateAnd( new_pc_val, @@ -568,28 +573,29 @@ private: bb=bbnext; } this->builder.SetInsertPoint(bb); - this->gen_sync(iss::POST_SYNC, 3); + this->gen_sync(POST_SYNC, 3); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 4: BEQ */ - std::tuple __beq(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __beq(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BEQ"); - this->gen_sync(iss::PRE_SYNC, 4); + this->gen_sync(PRE_SYNC, 4); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BEQ x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -600,13 +606,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_EQ, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)), @@ -614,28 +620,29 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 4); + this->gen_sync(POST_SYNC, 4); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 5: BNE */ - std::tuple __bne(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __bne(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BNE"); - this->gen_sync(iss::PRE_SYNC, 5); + this->gen_sync(PRE_SYNC, 5); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BNE x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -646,13 +653,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)), @@ -660,28 +667,29 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 5); + this->gen_sync(POST_SYNC, 5); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 6: BLT */ - std::tuple __blt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __blt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BLT"); - this->gen_sync(iss::PRE_SYNC, 6); + this->gen_sync(PRE_SYNC, 6); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BLT x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -693,16 +701,16 @@ private: this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 32, true)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)), @@ -710,28 +718,29 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 6); + this->gen_sync(POST_SYNC, 6); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 7: BGE */ - std::tuple __bge(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __bge(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BGE"); - this->gen_sync(iss::PRE_SYNC, 7); + this->gen_sync(PRE_SYNC, 7); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BGE x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -743,16 +752,16 @@ private: this->builder.CreateICmp( ICmpInst::ICMP_SGE, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 32, true)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)), @@ -760,28 +769,29 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 7); + this->gen_sync(POST_SYNC, 7); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 8: BLTU */ - std::tuple __bltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __bltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BLTU"); - this->gen_sync(iss::PRE_SYNC, 8); + this->gen_sync(PRE_SYNC, 8); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BLTU x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -792,13 +802,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)), @@ -806,28 +816,29 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 8); + this->gen_sync(POST_SYNC, 8); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 9: BGEU */ - std::tuple __bgeu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __bgeu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BGEU"); - this->gen_sync(iss::PRE_SYNC, 9); + this->gen_sync(PRE_SYNC, 9); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BGEU x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -838,13 +849,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_UGE, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)), @@ -852,28 +863,29 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 9); + this->gen_sync(POST_SYNC, 9); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 10: LB */ - std::tuple __lb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __lb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LB"); - this->gen_sync(iss::PRE_SYNC, 10); + this->gen_sync(PRE_SYNC, 10); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LB x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -883,40 +895,41 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(32U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 8/8), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 10); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 10); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 11: LH */ - std::tuple __lh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __lh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LH"); - this->gen_sync(iss::PRE_SYNC, 11); + this->gen_sync(PRE_SYNC, 11); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LH x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -926,40 +939,41 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(32U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 16/8), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 11); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 11); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 12: LW */ - std::tuple __lw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LW"); - this->gen_sync(iss::PRE_SYNC, 12); + this->gen_sync(PRE_SYNC, 12); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LW x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -969,40 +983,41 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(32U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 12); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 12); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 13: LBU */ - std::tuple __lbu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __lbu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LBU"); - this->gen_sync(iss::PRE_SYNC, 13); + this->gen_sync(PRE_SYNC, 13); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LBU x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1012,40 +1027,41 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(32U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 8/8), 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 13); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 13); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 14: LHU */ - std::tuple __lhu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __lhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LHU"); - this->gen_sync(iss::PRE_SYNC, 14); + this->gen_sync(PRE_SYNC, 14); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LHU x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1055,40 +1071,41 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(32U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 16/8), 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 14); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 14); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 15: SB */ - std::tuple __sb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __sb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SB"); - this->gen_sync(iss::PRE_SYNC, 15); + this->gen_sync(PRE_SYNC, 15); - int16_t fld_imm_val = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SB x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1098,38 +1115,39 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->gen_const(32U, imm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(8))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 15); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 15); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 16: SH */ - std::tuple __sh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __sh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SH"); - this->gen_sync(iss::PRE_SYNC, 16); + this->gen_sync(PRE_SYNC, 16); - int16_t fld_imm_val = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SH x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1139,38 +1157,39 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->gen_const(32U, imm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(16))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 16); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 16); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 17: SW */ - std::tuple __sw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SW"); - this->gen_sync(iss::PRE_SYNC, 17); + this->gen_sync(PRE_SYNC, 17); - int16_t fld_imm_val = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SW x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1180,38 +1199,39 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->gen_const(32U, imm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 17); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 17); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 18: ADDI */ - std::tuple __addi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ADDI"); - this->gen_sync(iss::PRE_SYNC, 18); + this->gen_sync(PRE_SYNC, 18); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ADDI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1219,38 +1239,39 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 18); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 18); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 19: SLTI */ - std::tuple __slti(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __slti(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLTI"); - this->gen_sync(iss::PRE_SYNC, 19); + this->gen_sync(PRE_SYNC, 19); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLTI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1258,43 +1279,44 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 19); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 19); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 20: SLTIU */ - std::tuple __sltiu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __sltiu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLTIU"); - this->gen_sync(iss::PRE_SYNC, 20); + this->gen_sync(PRE_SYNC, 20); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLTIU x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1302,42 +1324,43 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - int32_t full_imm_val = fld_imm_val; - if(fld_rd_val != 0){ + int32_t full_imm_val = imm; + if(rd != 0){ Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this->gen_const(32U, full_imm_val)), this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 20); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 20); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 21: XORI */ - std::tuple __xori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __xori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("XORI"); - this->gen_sync(iss::PRE_SYNC, 21); + this->gen_sync(PRE_SYNC, 21); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("XORI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1345,36 +1368,39 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateXor( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_ext( + this->gen_reg_load(rs1 + traits::X0, 0), + 32, true), + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 21); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 21); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 22: ORI */ - std::tuple __ori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __ori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ORI"); - this->gen_sync(iss::PRE_SYNC, 22); + this->gen_sync(PRE_SYNC, 22); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ORI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1382,36 +1408,39 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateOr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_ext( + this->gen_reg_load(rs1 + traits::X0, 0), + 32, true), + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 22); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 22); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 23: ANDI */ - std::tuple __andi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ANDI"); - this->gen_sync(iss::PRE_SYNC, 23); + this->gen_sync(PRE_SYNC, 23); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1419,36 +1448,39 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAnd( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_ext( + this->gen_reg_load(rs1 + traits::X0, 0), + 32, true), + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 23); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 23); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 24: SLLI */ - std::tuple __slli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLLI"); - this->gen_sync(iss::PRE_SYNC, 24); + this->gen_sync(PRE_SYNC, 24); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_shamt_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLLI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1456,40 +1488,41 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_shamt_val > 31){ + if(shamt > 31){ this->gen_raise_trap(0, 0); } else { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateShl( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_const(32U, shamt)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 24); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 24); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 25: SRLI */ - std::tuple __srli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRLI"); - this->gen_sync(iss::PRE_SYNC, 25); + this->gen_sync(PRE_SYNC, 25); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_shamt_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRLI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1497,40 +1530,41 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_shamt_val > 31){ + if(shamt > 31){ this->gen_raise_trap(0, 0); } else { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateLShr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_const(32U, shamt)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 25); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 25); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 26: SRAI */ - std::tuple __srai(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRAI"); - this->gen_sync(iss::PRE_SYNC, 26); + this->gen_sync(PRE_SYNC, 26); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_shamt_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRAI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1538,40 +1572,41 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_shamt_val > 31){ + if(shamt > 31){ this->gen_raise_trap(0, 0); } else { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAShr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_const(32U, shamt)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 26); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 26); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 27: ADD */ - std::tuple __add(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ADD"); - this->gen_sync(iss::PRE_SYNC, 27); + this->gen_sync(PRE_SYNC, 27); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ADD x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1579,36 +1614,37 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 27); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 27); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 28: SUB */ - std::tuple __sub(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SUB"); - this->gen_sync(iss::PRE_SYNC, 28); + this->gen_sync(PRE_SYNC, 28); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SUB x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1616,36 +1652,37 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateSub( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 28); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 28); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 29: SLL */ - std::tuple __sll(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __sll(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLL"); - this->gen_sync(iss::PRE_SYNC, 29); + this->gen_sync(PRE_SYNC, 29); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLL x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1653,38 +1690,41 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateShl( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this->builder.CreateAnd( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0x1f))); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs2 + traits::X0, 0), + this->builder.CreateSub( + this->gen_const(32U, 32), + this->gen_const(32U, 1)))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 29); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 29); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 30: SLT */ - std::tuple __slt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __slt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLT"); - this->gen_sync(iss::PRE_SYNC, 30); + this->gen_sync(PRE_SYNC, 30); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLT x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1692,45 +1732,46 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 32, true)), this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 30); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 30); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 31: SLTU */ - std::tuple __sltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __sltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLTU"); - this->gen_sync(iss::PRE_SYNC, 31); + this->gen_sync(PRE_SYNC, 31); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLTU x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1738,47 +1779,48 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, false), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 32, false)), this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 31); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 31); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 32: XOR */ - std::tuple __xor(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("XOR"); - this->gen_sync(iss::PRE_SYNC, 32); + this->gen_sync(PRE_SYNC, 32); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("XOR x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1786,36 +1828,37 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateXor( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 32); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 32); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 33: SRL */ - std::tuple __srl(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __srl(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRL"); - this->gen_sync(iss::PRE_SYNC, 33); + this->gen_sync(PRE_SYNC, 33); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRL x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1823,38 +1866,41 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateLShr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this->builder.CreateAnd( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0x1f))); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs2 + traits::X0, 0), + this->builder.CreateSub( + this->gen_const(32U, 32), + this->gen_const(32U, 1)))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 33); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 33); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 34: SRA */ - std::tuple __sra(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __sra(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRA"); - this->gen_sync(iss::PRE_SYNC, 34); + this->gen_sync(PRE_SYNC, 34); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRA x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1862,38 +1908,41 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAShr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this->builder.CreateAnd( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0x1f))); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs2 + traits::X0, 0), + this->builder.CreateSub( + this->gen_const(32U, 32), + this->gen_const(32U, 1)))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 34); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 34); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 35: OR */ - std::tuple __or(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("OR"); - this->gen_sync(iss::PRE_SYNC, 35); + this->gen_sync(PRE_SYNC, 35); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("OR x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1901,36 +1950,37 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateOr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 35); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 35); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 36: AND */ - std::tuple __and(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AND"); - this->gen_sync(iss::PRE_SYNC, 36); + this->gen_sync(PRE_SYNC, 36); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AND x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1938,35 +1988,35 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAnd( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 36); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 36); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 37: FENCE */ - std::tuple __fence(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __fence(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FENCE"); - this->gen_sync(iss::PRE_SYNC, 37); + this->gen_sync(PRE_SYNC, 37); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_succ_val = ((bit_sub<20,4>(instr))); - uint8_t fld_pred_val = ((bit_sub<24,4>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - std::vector args { + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("FENCE"), + this->builder.CreateGlobalStringPtr("fence"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1976,35 +2026,35 @@ private: Value* FENCEtmp0_val = this->builder.CreateOr( this->builder.CreateShl( - this->gen_const(32U, fld_pred_val), + this->gen_const(32U, pred), this->gen_const(32U, 4)), - this->gen_const(32U, fld_succ_val)); + this->gen_const(32U, succ)); this->gen_write_mem( traits::FENCE, this->gen_const(64U, 0), this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 37); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 37); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 38: FENCE_I */ - std::tuple __fence_i(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __fence_i(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FENCE_I"); - this->gen_sync(iss::PRE_SYNC, 38); + this->gen_sync(PRE_SYNC, 38); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint16_t fld_imm_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - std::vector args { + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("FENCE_I"), + this->builder.CreateGlobalStringPtr("fence_i"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2012,30 +2062,30 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* FENCEtmp0_val = this->gen_const(32U, fld_imm_val); + Value* FENCEtmp0_val = this->gen_const(32U, imm); this->gen_write_mem( traits::FENCE, this->gen_const(64U, 1), this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32))); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 38); + this->gen_sync(POST_SYNC, 38); this->gen_trap_check(this->leave_blk); return std::make_tuple(FLUSH, nullptr); } /* instruction 39: ECALL */ - std::tuple __ecall(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __ecall(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ECALL"); - this->gen_sync(iss::PRE_SYNC, 39); + this->gen_sync(PRE_SYNC, 39); if(this->disass_enabled){ /* generate console output when executing the command */ - std::vector args { + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("ECALL"), + this->builder.CreateGlobalStringPtr("ecall"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2044,23 +2094,23 @@ private: pc=pc+4; this->gen_raise_trap(0, 11); - this->gen_sync(iss::POST_SYNC, 39); + this->gen_sync(POST_SYNC, 39); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 40: EBREAK */ - std::tuple __ebreak(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("EBREAK"); - this->gen_sync(iss::PRE_SYNC, 40); + this->gen_sync(PRE_SYNC, 40); if(this->disass_enabled){ /* generate console output when executing the command */ - std::vector args { + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("EBREAK"), + this->builder.CreateGlobalStringPtr("ebreak"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2069,23 +2119,23 @@ private: pc=pc+4; this->gen_raise_trap(0, 3); - this->gen_sync(iss::POST_SYNC, 40); + this->gen_sync(POST_SYNC, 40); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 41: URET */ - std::tuple __uret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __uret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("URET"); - this->gen_sync(iss::PRE_SYNC, 41); + this->gen_sync(PRE_SYNC, 41); if(this->disass_enabled){ /* generate console output when executing the command */ - std::vector args { + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("URET"), + this->builder.CreateGlobalStringPtr("uret"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2094,23 +2144,23 @@ private: pc=pc+4; this->gen_leave_trap(0); - this->gen_sync(iss::POST_SYNC, 41); + this->gen_sync(POST_SYNC, 41); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 42: SRET */ - std::tuple __sret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __sret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRET"); - this->gen_sync(iss::PRE_SYNC, 42); + this->gen_sync(PRE_SYNC, 42); if(this->disass_enabled){ /* generate console output when executing the command */ - std::vector args { + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("SRET"), + this->builder.CreateGlobalStringPtr("sret"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2119,23 +2169,23 @@ private: pc=pc+4; this->gen_leave_trap(1); - this->gen_sync(iss::POST_SYNC, 42); + this->gen_sync(POST_SYNC, 42); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 43: MRET */ - std::tuple __mret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __mret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("MRET"); - this->gen_sync(iss::PRE_SYNC, 43); + this->gen_sync(PRE_SYNC, 43); if(this->disass_enabled){ /* generate console output when executing the command */ - std::vector args { + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("MRET"), + this->builder.CreateGlobalStringPtr("mret"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2144,23 +2194,23 @@ private: pc=pc+4; this->gen_leave_trap(3); - this->gen_sync(iss::POST_SYNC, 43); + this->gen_sync(POST_SYNC, 43); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 44: WFI */ - std::tuple __wfi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __wfi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("WFI"); - this->gen_sync(iss::PRE_SYNC, 44); + this->gen_sync(PRE_SYNC, 44); if(this->disass_enabled){ /* generate console output when executing the command */ - std::vector args { + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("WFI"), + this->builder.CreateGlobalStringPtr("wfi"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2170,26 +2220,26 @@ private: this->gen_wait(1); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 44); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 44); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 45: SFENCE.VMA */ - std::tuple __sfence_vma(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __sfence_vma(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SFENCE.VMA"); - this->gen_sync(iss::PRE_SYNC, 45); + this->gen_sync(PRE_SYNC, 45); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - std::vector args { + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("SFENCE.VMA"), + this->builder.CreateGlobalStringPtr("sfence.vma"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2197,40 +2247,41 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* FENCEtmp0_val = this->gen_const(32U, fld_rs1_val); + Value* FENCEtmp0_val = this->gen_const(32U, rs1); this->gen_write_mem( traits::FENCE, this->gen_const(64U, 2), this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32))); - Value* FENCEtmp1_val = this->gen_const(32U, fld_rs2_val); + Value* FENCEtmp1_val = this->gen_const(32U, rs2); this->gen_write_mem( traits::FENCE, this->gen_const(64U, 3), this->builder.CreateZExtOrTrunc(FENCEtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 45); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 45); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 46: CSRRW */ - std::tuple __csrrw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __csrrw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRW"); - this->gen_sync(iss::PRE_SYNC, 46); + this->gen_sync(PRE_SYNC, 46); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRW x%1$d, %2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2238,47 +2289,48 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* rs_val_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ - Value* csr_val_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); + Value* rs_val_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ + Value* csr_val_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 32/8); Value* CSRtmp0_val = rs_val_val; this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp0_val,this->get_type(32))); Value* Xtmp1_val = csr_val_val; - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } else { Value* CSRtmp2_val = rs_val_val; this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp2_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 46); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 46); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 47: CSRRS */ - std::tuple __csrrs(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __csrrs(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRS"); - this->gen_sync(iss::PRE_SYNC, 47); + this->gen_sync(PRE_SYNC, 47); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRS x%1$d, %2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2286,45 +2338,46 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); - Value* xrs1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ + Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 32/8); + Value* xrs1_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ Value* Xtmp0_val = xrd_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - if(fld_rs1_val != 0){ + if(rs1 != 0){ Value* CSRtmp1_val = this->builder.CreateOr( xrd_val, xrs1_val); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 47); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 47); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 48: CSRRC */ - std::tuple __csrrc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __csrrc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRC"); - this->gen_sync(iss::PRE_SYNC, 48); + this->gen_sync(PRE_SYNC, 48); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRC x%1$d, %2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2332,45 +2385,46 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); - Value* xrs1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ + Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 32/8); + Value* xrs1_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ Value* Xtmp0_val = xrd_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - if(fld_rs1_val != 0){ + if(rs1 != 0){ Value* CSRtmp1_val = this->builder.CreateAnd( xrd_val, this->builder.CreateNot(xrs1_val)); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 48); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 48); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 49: CSRRWI */ - std::tuple __csrrwi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __csrrwi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRWI"); - this->gen_sync(iss::PRE_SYNC, 49); + this->gen_sync(PRE_SYNC, 49); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_zimm_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRWI x%1$d, %2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2378,42 +2432,43 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ - Value* Xtmp0_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + if(rd != 0){ + Value* Xtmp0_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 32/8); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* CSRtmp1_val = this->gen_ext( - this->gen_const(32U, fld_zimm_val), + this->gen_const(32U, zimm), 32, false); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 49); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 49); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 50: CSRRSI */ - std::tuple __csrrsi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __csrrsi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRSI"); - this->gen_sync(iss::PRE_SYNC, 50); + this->gen_sync(PRE_SYNC, 50); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_zimm_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRSI x%1$d, %2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2421,47 +2476,48 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); - if(fld_zimm_val != 0){ + Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 32/8); + if(zimm != 0){ Value* CSRtmp0_val = this->builder.CreateOr( res_val, this->gen_ext( - this->gen_const(32U, fld_zimm_val), + this->gen_const(32U, zimm), 32, false)); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp0_val,this->get_type(32))); } - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp1_val = res_val; - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 50); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 50); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 51: CSRRCI */ - std::tuple __csrrci(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __csrrci(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRCI"); - this->gen_sync(iss::PRE_SYNC, 51); + this->gen_sync(PRE_SYNC, 51); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_zimm_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRCI x%1$d, %2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2469,47 +2525,48 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); - if(fld_rd_val != 0){ + Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 32/8); + if(rd != 0){ Value* Xtmp0_val = res_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - if(fld_zimm_val != 0){ + if(zimm != 0){ Value* CSRtmp1_val = this->builder.CreateAnd( res_val, this->builder.CreateNot(this->gen_ext( - this->gen_const(32U, fld_zimm_val), + this->gen_const(32U, zimm), 32, false))); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 51); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 51); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 52: MUL */ - std::tuple __mul(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __mul(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("MUL"); - this->gen_sync(iss::PRE_SYNC, 52); + this->gen_sync(PRE_SYNC, 52); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("MUL x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2517,46 +2574,47 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* res_val = this->builder.CreateMul( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 128, false), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 128, false)); Value* Xtmp0_val = this->gen_ext( res_val, 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 52); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 52); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 53: MULH */ - std::tuple __mulh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __mulh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("MULH"); - this->gen_sync(iss::PRE_SYNC, 53); + this->gen_sync(PRE_SYNC, 53); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("MULH x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2564,14 +2622,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* res_val = this->builder.CreateMul( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 128, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 128, true)); Value* Xtmp0_val = this->gen_ext( @@ -2580,32 +2638,33 @@ private: this->gen_const(32U, 32)), 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 53); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 53); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 54: MULHSU */ - std::tuple __mulhsu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __mulhsu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("MULHSU"); - this->gen_sync(iss::PRE_SYNC, 54); + this->gen_sync(PRE_SYNC, 54); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("MULHSU x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2613,14 +2672,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* res_val = this->builder.CreateMul( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 128, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 128, false)); Value* Xtmp0_val = this->gen_ext( @@ -2629,32 +2688,33 @@ private: this->gen_const(32U, 32)), 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 54); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 54); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 55: MULHU */ - std::tuple __mulhu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __mulhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("MULHU"); - this->gen_sync(iss::PRE_SYNC, 55); + this->gen_sync(PRE_SYNC, 55); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("MULHU x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2662,14 +2722,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* res_val = this->builder.CreateMul( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 128, false), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 128, false)); Value* Xtmp0_val = this->gen_ext( @@ -2678,32 +2738,33 @@ private: this->gen_const(32U, 32)), 32, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 55); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 55); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 56: DIV */ - std::tuple __div(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __div(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("DIV"); - this->gen_sync(iss::PRE_SYNC, 56); + this->gen_sync(PRE_SYNC, 56); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("DIV x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2711,15 +2772,15 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + BasicBlock* bb_else = BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this->gen_const(32U, 0)), bb_then, bb_else); @@ -2728,14 +2789,14 @@ private: uint32_t M1_val = - 1; uint32_t MMIN_val = - 1 << 32 - 1; { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + BasicBlock* bb_else = BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_EQ, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), + this->gen_reg_load(rs1 + traits::X0, 1), 32, true), this->gen_ext( this->gen_const(32U, MMIN_val), @@ -2745,14 +2806,14 @@ private: this->builder.SetInsertPoint(bb_then); { { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + BasicBlock* bb_else = BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_EQ, this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), + this->gen_reg_load(rs2 + traits::X0, 2), 32, true), this->gen_ext( this->gen_const(32U, M1_val), @@ -2762,19 +2823,19 @@ private: this->builder.SetInsertPoint(bb_then); { Value* Xtmp0_val = this->gen_const(32U, MMIN_val); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { Value* Xtmp1_val = this->builder.CreateSDiv( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 3), + this->gen_reg_load(rs1 + traits::X0, 3), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 3), + this->gen_reg_load(rs2 + traits::X0, 3), 32, true)); - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -2786,12 +2847,12 @@ private: { Value* Xtmp2_val = this->builder.CreateSDiv( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 2), + this->gen_reg_load(rs1 + traits::X0, 2), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), + this->gen_reg_load(rs2 + traits::X0, 2), 32, true)); - this->builder.CreateStore(Xtmp2_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp2_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -2802,7 +2863,7 @@ private: this->builder.SetInsertPoint(bb_else); { Value* Xtmp3_val = this->builder.CreateNeg(this->gen_const(32U, 1)); - this->builder.CreateStore(Xtmp3_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp3_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -2810,29 +2871,30 @@ private: this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 56); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 56); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 57: DIVU */ - std::tuple __divu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __divu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("DIVU"); - this->gen_sync(iss::PRE_SYNC, 57); + this->gen_sync(PRE_SYNC, 57); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("DIVU x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2840,15 +2902,15 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + BasicBlock* bb_else = BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this->gen_const(32U, 0)), bb_then, bb_else); @@ -2856,20 +2918,20 @@ private: { Value* Xtmp0_val = this->builder.CreateUDiv( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), + this->gen_reg_load(rs1 + traits::X0, 1), 32, false), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 1), + this->gen_reg_load(rs2 + traits::X0, 1), 32, false)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { Value* Xtmp1_val = this->builder.CreateNeg(this->gen_const(32U, 1)); - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -2877,29 +2939,30 @@ private: this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 57); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 57); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 58: REM */ - std::tuple __rem(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __rem(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("REM"); - this->gen_sync(iss::PRE_SYNC, 58); + this->gen_sync(PRE_SYNC, 58); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("REM x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2907,15 +2970,15 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + BasicBlock* bb_else = BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this->gen_const(32U, 0)), bb_then, bb_else); @@ -2924,14 +2987,14 @@ private: uint32_t M1_val = - 1; uint32_t MMIN_val = - 1 << 32 - 1; { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + BasicBlock* bb_else = BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_EQ, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), + this->gen_reg_load(rs1 + traits::X0, 1), 32, true), this->gen_ext( this->gen_const(32U, MMIN_val), @@ -2941,14 +3004,14 @@ private: this->builder.SetInsertPoint(bb_then); { { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + BasicBlock* bb_else = BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_EQ, this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), + this->gen_reg_load(rs2 + traits::X0, 2), 32, true), this->gen_ext( this->gen_const(32U, M1_val), @@ -2958,21 +3021,21 @@ private: this->builder.SetInsertPoint(bb_then); { Value* Xtmp0_val = this->gen_const(32U, 0); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { Value* Xtmp1_val = this->builder.CreateURem( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 3), + this->gen_reg_load(rs1 + traits::X0, 3), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 3), + this->gen_reg_load(rs2 + traits::X0, 3), 32, true)); - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -2984,14 +3047,14 @@ private: { Value* Xtmp2_val = this->builder.CreateURem( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 2), + this->gen_reg_load(rs1 + traits::X0, 2), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), + this->gen_reg_load(rs2 + traits::X0, 2), 32, true)); - this->builder.CreateStore(Xtmp2_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp2_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -3001,8 +3064,8 @@ private: this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { - Value* Xtmp3_val = this->gen_reg_load(fld_rs1_val + traits::X0, 1); - this->builder.CreateStore(Xtmp3_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp3_val = this->gen_reg_load(rs1 + traits::X0, 1); + this->builder.CreateStore(Xtmp3_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -3010,29 +3073,30 @@ private: this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 58); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 58); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 59: REMU */ - std::tuple __remu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __remu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("REMU"); - this->gen_sync(iss::PRE_SYNC, 59); + this->gen_sync(PRE_SYNC, 59); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("REMU x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3040,15 +3104,15 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + BasicBlock* bb_else = BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this->gen_const(32U, 0)), bb_then, bb_else); @@ -3056,20 +3120,20 @@ private: { Value* Xtmp0_val = this->builder.CreateURem( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), + this->gen_reg_load(rs1 + traits::X0, 1), 32, false), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 1), + this->gen_reg_load(rs2 + traits::X0, 1), 32, false)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { - Value* Xtmp1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 1); - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp1_val = this->gen_reg_load(rs1 + traits::X0, 1); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; @@ -3077,30 +3141,31 @@ private: this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 59); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 59); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 60: LR.W */ - std::tuple __lr_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __lr_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LR.W"); - this->gen_sync(iss::PRE_SYNC, 60); + this->gen_sync(PRE_SYNC, 60); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LR.W x%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "lr.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3108,13 +3173,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - if(fld_rd_val != 0){ - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + if(rd != 0){ + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* REStmp1_val = this->gen_ext( this->builder.CreateNeg(this->gen_const(8U, 1)), 32, @@ -3125,31 +3190,32 @@ private: this->builder.CreateZExtOrTrunc(REStmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 60); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 60); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 61: SC.W */ - std::tuple __sc_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __sc_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SC.W"); - this->gen_sync(iss::PRE_SYNC, 61); + this->gen_sync(PRE_SYNC, 61); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SC.W x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sc.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3157,11 +3223,11 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_read_mem(traits::RES, offs_val, 32/8); { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + BasicBlock* bb_then = BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_NE, @@ -3171,7 +3237,7 @@ private: bbnext); this->builder.SetInsertPoint(bb_then); { - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 1); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 1); this->gen_write_mem( traits::MEM, offs_val, @@ -3181,7 +3247,7 @@ private: bb=bbnext; } this->builder.SetInsertPoint(bb); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp1_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, @@ -3190,34 +3256,35 @@ private: this->gen_const(32U, 0), this->gen_const(32U, 1), 32); - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 61); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 61); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 62: AMOSWAP.W */ - std::tuple __amoswap_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __amoswap_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOSWAP.W"); - this->gen_sync(iss::PRE_SYNC, 62); + this->gen_sync(PRE_SYNC, 62); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOSWAP.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoswap.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3225,45 +3292,46 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - Value* MEMtmp1_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp1_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 62); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 62); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 63: AMOADD.W */ - std::tuple __amoadd_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __amoadd_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOADD.W"); - this->gen_sync(iss::PRE_SYNC, 63); + this->gen_sync(PRE_SYNC, 63); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOADD.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoadd.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3271,49 +3339,50 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateAdd( res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 63); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 63); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 64: AMOXOR.W */ - std::tuple __amoxor_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __amoxor_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOXOR.W"); - this->gen_sync(iss::PRE_SYNC, 64); + this->gen_sync(PRE_SYNC, 64); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOXOR.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoxor.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3321,49 +3390,50 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateXor( res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 64); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 64); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 65: AMOAND.W */ - std::tuple __amoand_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __amoand_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOAND.W"); - this->gen_sync(iss::PRE_SYNC, 65); + this->gen_sync(PRE_SYNC, 65); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOAND.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoand.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3371,49 +3441,50 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateAnd( res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 65); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 65); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 66: AMOOR.W */ - std::tuple __amoor_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __amoor_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOOR.W"); - this->gen_sync(iss::PRE_SYNC, 66); + this->gen_sync(PRE_SYNC, 66); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOOR.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoor.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3421,49 +3492,50 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateOr( res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 66); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 66); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 67: AMOMIN.W */ - std::tuple __amomin_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __amomin_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMIN.W"); - this->gen_sync(iss::PRE_SYNC, 67); + this->gen_sync(PRE_SYNC, 67); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMIN.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amomin.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3471,14 +3543,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3487,9 +3559,9 @@ private: res1_val, 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 32, true)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), res1_val, 32); Value* MEMtmp1_val = res2_val; @@ -3498,31 +3570,32 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 67); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 67); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 68: AMOMAX.W */ - std::tuple __amomax_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __amomax_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMAX.W"); - this->gen_sync(iss::PRE_SYNC, 68); + this->gen_sync(PRE_SYNC, 68); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMAX.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amomax.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3530,14 +3603,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3546,9 +3619,9 @@ private: res1_val, 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 32, true)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), res1_val, 32); Value* MEMtmp1_val = res2_val; @@ -3557,31 +3630,32 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 68); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 68); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 69: AMOMINU.W */ - std::tuple __amominu_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __amominu_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMINU.W"); - this->gen_sync(iss::PRE_SYNC, 69); + this->gen_sync(PRE_SYNC, 69); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMINU.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amominu.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3589,21 +3663,21 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, false); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_UGT, res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), + this->gen_reg_load(rs2 + traits::X0, 0), res1_val, 32); Value* MEMtmp1_val = res2_val; @@ -3612,31 +3686,32 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 69); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 69); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 70: AMOMAXU.W */ - std::tuple __amomaxu_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __amomaxu_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMAXU.W"); - this->gen_sync(iss::PRE_SYNC, 70); + this->gen_sync(PRE_SYNC, 70); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMAXU.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amomaxu.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3644,21 +3719,21 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, false); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), + this->gen_reg_load(rs2 + traits::X0, 0), res1_val, 32); Value* MEMtmp1_val = res2_val; @@ -3667,28 +3742,29 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 70); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 70); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 71: C.ADDI4SPN */ - std::tuple __c_addi4spn(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_addi4spn(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.ADDI4SPN"); - this->gen_sync(iss::PRE_SYNC, 71); + this->gen_sync(PRE_SYNC, 71); - uint8_t fld_rd_val = ((bit_sub<2,3>(instr))); - uint16_t fld_imm_val = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); + uint8_t rd = ((bit_sub<2,3>(instr))); + uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.ADDI4SPN x%1$d, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3696,37 +3772,38 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - if(fld_imm_val == 0){ + if(imm == 0){ this->gen_raise_trap(0, 2); } Value* Xtmp0_val = this->builder.CreateAdd( this->gen_reg_load(2 + traits::X0, 0), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + 8 + traits::X0), false); + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + 8 + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 71); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 71); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 72: C.LW */ - std::tuple __c_lw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.LW"); - this->gen_sync(iss::PRE_SYNC, 72); + this->gen_sync(PRE_SYNC, 72); - uint8_t fld_rd_val = ((bit_sub<2,3>(instr))); - uint8_t fld_uimm_val = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.LW x(8+%1$d), x(8+%2$d), 0x%3$05x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_uimm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {uimm:#05x}", fmt::arg("mnemonic", "c.lw"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs1", name(8+rs1)), fmt::arg("uimm", uimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3735,34 +3812,35 @@ private: pc=pc+2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rs1_val + 8 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); + this->gen_reg_load(rs1 + 8 + traits::X0, 0), + this->gen_const(32U, uimm)); Value* Xtmp0_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + 8 + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + 8 + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 72); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 72); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 73: C.SW */ - std::tuple __c_sw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.SW"); - this->gen_sync(iss::PRE_SYNC, 73); + this->gen_sync(PRE_SYNC, 73); - uint8_t fld_rs2_val = ((bit_sub<2,3>(instr))); - uint8_t fld_uimm_val = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.SW x(8+%1$d), x(8+%2$d), 0x%3$05x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_uimm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {uimm:#05x}", fmt::arg("mnemonic", "c.sw"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3771,36 +3849,37 @@ private: pc=pc+2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rs1_val + 8 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + 8 + traits::X0, 0); + this->gen_reg_load(rs1 + 8 + traits::X0, 0), + this->gen_const(32U, uimm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + 8 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 73); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 73); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 74: C.ADDI */ - std::tuple __c_addi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.ADDI"); - this->gen_sync(iss::PRE_SYNC, 74); + this->gen_sync(PRE_SYNC, 74); - int8_t fld_imm_val = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<7,5>(instr))); + int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.ADDI x%1$d, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3810,29 +3889,29 @@ private: Value* Xtmp0_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rs1_val + traits::X0), false); + this->gen_const(32U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1 + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 74); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 74); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 75: C.NOP */ - std::tuple __c_nop(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_nop(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.NOP"); - this->gen_sync(iss::PRE_SYNC, 75); + this->gen_sync(PRE_SYNC, 75); if(this->disass_enabled){ /* generate console output when executing the command */ - std::vector args { + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("C.NOP"), + this->builder.CreateGlobalStringPtr("c.nop"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3842,27 +3921,28 @@ private: /* TODO: describe operations for C.NOP ! */ this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 75); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 75); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 76: C.JAL */ - std::tuple __c_jal(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.JAL"); - this->gen_sync(iss::PRE_SYNC, 76); + this->gen_sync(PRE_SYNC, 76); - int16_t fld_imm_val = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.JAL 0x%1$05x"); - ins_fmter % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"), + fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3878,31 +3958,32 @@ private: this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 76); + this->gen_sync(POST_SYNC, 76); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 77: C.LI */ - std::tuple __c_li(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_li(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.LI"); - this->gen_sync(iss::PRE_SYNC, 77); + this->gen_sync(PRE_SYNC, 77); - int8_t fld_imm_val = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); + int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.LI x%1$d, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3910,34 +3991,35 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - if(fld_rd_val == 0){ + if(rd == 0){ this->gen_raise_trap(0, 2); } - Value* Xtmp0_val = this->gen_const(32U, fld_imm_val); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_const(32U, imm); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 77); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 77); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 78: C.LUI */ - std::tuple __c_lui(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.LUI"); - this->gen_sync(iss::PRE_SYNC, 78); + this->gen_sync(PRE_SYNC, 78); - int32_t fld_imm_val = signextend((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); + uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.LUI x%1$d, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3945,36 +4027,37 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - if(fld_rd_val == 0){ + if(rd == 0){ this->gen_raise_trap(0, 2); } - if(fld_imm_val == 0){ + if(imm == 0){ this->gen_raise_trap(0, 2); } - Value* Xtmp0_val = this->gen_const(32U, fld_imm_val); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_const(32U, imm); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 78); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 78); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 79: C.ADDI16SP */ - std::tuple __c_addi16sp(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_addi16sp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.ADDI16SP"); - this->gen_sync(iss::PRE_SYNC, 79); + this->gen_sync(PRE_SYNC, 79); - int16_t fld_imm_val = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.ADDI16SP 0x%1$05x"); - ins_fmter % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.addi16sp"), + fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3986,31 +4069,32 @@ private: this->gen_ext( this->gen_reg_load(2 + traits::X0, 0), 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(2 + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 79); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 79); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 80: C.SRLI */ - std::tuple __c_srli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.SRLI"); - this->gen_sync(iss::PRE_SYNC, 80); + this->gen_sync(PRE_SYNC, 80); - uint8_t fld_shamt_val = ((bit_sub<2,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.SRLI x(8+%1$d), %2$d"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4018,34 +4102,35 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = fld_rs1_val + 8; + uint8_t rs1_idx_val = rs1 + 8; Value* Xtmp0_val = this->builder.CreateLShr( this->gen_reg_load(rs1_idx_val + traits::X0, 0), - this->gen_const(32U, fld_shamt_val)); + this->gen_const(32U, shamt)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 80); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 80); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 81: C.SRAI */ - std::tuple __c_srai(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.SRAI"); - this->gen_sync(iss::PRE_SYNC, 81); + this->gen_sync(PRE_SYNC, 81); - uint8_t fld_shamt_val = ((bit_sub<2,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.SRAI x(8+%1$d), %2$d"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4053,34 +4138,35 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = fld_rs1_val + 8; + uint8_t rs1_idx_val = rs1 + 8; Value* Xtmp0_val = this->builder.CreateAShr( this->gen_reg_load(rs1_idx_val + traits::X0, 0), - this->gen_const(32U, fld_shamt_val)); + this->gen_const(32U, shamt)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 81); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 81); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 82: C.ANDI */ - std::tuple __c_andi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.ANDI"); - this->gen_sync(iss::PRE_SYNC, 82); + this->gen_sync(PRE_SYNC, 82); - uint8_t fld_imm_val = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.ANDI x(8+%1$d), 0x%2$05x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4088,34 +4174,35 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = fld_rs1_val + 8; + uint8_t rs1_idx_val = rs1 + 8; Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(rs1_idx_val + traits::X0, 0), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 82); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 82); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 83: C.SUB */ - std::tuple __c_sub(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.SUB"); - this->gen_sync(iss::PRE_SYNC, 83); + this->gen_sync(PRE_SYNC, 83); - uint8_t fld_rs2_val = ((bit_sub<2,3>(instr))); - uint8_t fld_rd_val = ((bit_sub<7,3>(instr))); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.SUB x(8+%1$d), x(8+%2$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4123,34 +4210,35 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rd_idx_val = fld_rd_val + 8; + uint8_t rd_idx_val = rd + 8; Value* Xtmp0_val = this->builder.CreateSub( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + 8 + traits::X0, 0)); + this->gen_reg_load(rs2 + 8 + traits::X0, 0)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 83); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 83); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 84: C.XOR */ - std::tuple __c_xor(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.XOR"); - this->gen_sync(iss::PRE_SYNC, 84); + this->gen_sync(PRE_SYNC, 84); - uint8_t fld_rs2_val = ((bit_sub<2,3>(instr))); - uint8_t fld_rd_val = ((bit_sub<7,3>(instr))); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.XOR x(8+%1$d), x(8+%2$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4158,34 +4246,35 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rd_idx_val = fld_rd_val + 8; + uint8_t rd_idx_val = rd + 8; Value* Xtmp0_val = this->builder.CreateXor( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + 8 + traits::X0, 0)); + this->gen_reg_load(rs2 + 8 + traits::X0, 0)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 84); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 84); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 85: C.OR */ - std::tuple __c_or(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.OR"); - this->gen_sync(iss::PRE_SYNC, 85); + this->gen_sync(PRE_SYNC, 85); - uint8_t fld_rs2_val = ((bit_sub<2,3>(instr))); - uint8_t fld_rd_val = ((bit_sub<7,3>(instr))); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.OR x(8+%1$d), x(8+%2$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4193,34 +4282,35 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rd_idx_val = fld_rd_val + 8; + uint8_t rd_idx_val = rd + 8; Value* Xtmp0_val = this->builder.CreateOr( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + 8 + traits::X0, 0)); + this->gen_reg_load(rs2 + 8 + traits::X0, 0)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 85); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 85); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 86: C.AND */ - std::tuple __c_and(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.AND"); - this->gen_sync(iss::PRE_SYNC, 86); + this->gen_sync(PRE_SYNC, 86); - uint8_t fld_rs2_val = ((bit_sub<2,3>(instr))); - uint8_t fld_rd_val = ((bit_sub<7,3>(instr))); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.AND x(8+%1$d), x(8+%2$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4228,33 +4318,34 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rd_idx_val = fld_rd_val + 8; + uint8_t rd_idx_val = rd + 8; Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + 8 + traits::X0, 0)); + this->gen_reg_load(rs2 + 8 + traits::X0, 0)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 86); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 86); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 87: C.J */ - std::tuple __c_j(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_j(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.J"); - this->gen_sync(iss::PRE_SYNC, 87); + this->gen_sync(PRE_SYNC, 87); - int16_t fld_imm_val = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.J 0x%1$05x"); - ins_fmter % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"), + fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4266,31 +4357,32 @@ private: this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 87); + this->gen_sync(POST_SYNC, 87); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 88: C.BEQZ */ - std::tuple __c_beqz(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_beqz(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.BEQZ"); - this->gen_sync(iss::PRE_SYNC, 88); + this->gen_sync(PRE_SYNC, 88); - int16_t fld_imm_val = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.BEQZ x(8+%1$d), 0x%2$05x"); - ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4301,13 +4393,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_EQ, - this->gen_reg_load(fld_rs1_val + 8 + traits::X0, 0), + this->gen_reg_load(rs1 + 8 + traits::X0, 0), this->gen_const(32U, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 2)), @@ -4315,27 +4407,28 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 88); + this->gen_sync(POST_SYNC, 88); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 89: C.BNEZ */ - std::tuple __c_bnez(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_bnez(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.BNEZ"); - this->gen_sync(iss::PRE_SYNC, 89); + this->gen_sync(PRE_SYNC, 89); - int16_t fld_imm_val = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); - uint8_t fld_rs1_val = ((bit_sub<7,3>(instr))); + int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.BNEZ x(8+%1$d), 0x%2$05x"); - ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4346,13 +4439,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs1_val + 8 + traits::X0, 0), + this->gen_reg_load(rs1 + 8 + traits::X0, 0), this->gen_const(32U, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 32, true), - this->gen_const(32U, fld_imm_val)), + this->gen_const(32U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 2)), @@ -4360,27 +4453,28 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 89); + this->gen_sync(POST_SYNC, 89); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 90: C.SLLI */ - std::tuple __c_slli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.SLLI"); - this->gen_sync(iss::PRE_SYNC, 90); + this->gen_sync(PRE_SYNC, 90); - uint8_t fld_shamt_val = ((bit_sub<2,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<7,5>(instr))); + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.SLLI x%1$d, %2$d"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4388,36 +4482,37 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - if(fld_rs1_val == 0){ + if(rs1 == 0){ this->gen_raise_trap(0, 2); } Value* Xtmp0_val = this->builder.CreateShl( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rs1_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_const(32U, shamt)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1 + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 90); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 90); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 91: C.LWSP */ - std::tuple __c_lwsp(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_lwsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.LWSP"); - this->gen_sync(iss::PRE_SYNC, 91); + this->gen_sync(PRE_SYNC, 91); - uint8_t fld_uimm_val = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.LWSP x%1$d, sp, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_uimm_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4427,32 +4522,33 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(2 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); + this->gen_const(32U, uimm)); Value* Xtmp0_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 91); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 91); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 92: C.MV */ - std::tuple __c_mv(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_mv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.MV"); - this->gen_sync(iss::PRE_SYNC, 92); + this->gen_sync(PRE_SYNC, 92); - uint8_t fld_rs2_val = ((bit_sub<2,5>(instr))); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.MV x%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4460,30 +4556,31 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - Value* Xtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 92); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 92); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 93: C.JR */ - std::tuple __c_jr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_jr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.JR"); - this->gen_sync(iss::PRE_SYNC, 93); + this->gen_sync(PRE_SYNC, 93); - uint8_t fld_rs1_val = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.JR x%1$d"); - ins_fmter % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"), + fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4491,30 +4588,31 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - Value* PC_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* PC_val = this->gen_reg_load(rs1 + traits::X0, 0); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 93); + this->gen_sync(POST_SYNC, 93); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 94: C.ADD */ - std::tuple __c_add(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.ADD"); - this->gen_sync(iss::PRE_SYNC, 94); + this->gen_sync(PRE_SYNC, 94); - uint8_t fld_rs2_val = ((bit_sub<2,5>(instr))); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.ADD x%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4523,31 +4621,32 @@ private: pc=pc+2; Value* Xtmp0_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rd_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rd + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 94); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 94); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 95: C.JALR */ - std::tuple __c_jalr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.JALR"); - this->gen_sync(iss::PRE_SYNC, 95); + this->gen_sync(PRE_SYNC, 95); - uint8_t fld_rs1_val = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.JALR x%1$d"); - ins_fmter % (uint64_t)fld_rs1_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"), + fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4559,26 +4658,26 @@ private: cur_pc_val, this->gen_const(32U, 2)); this->builder.CreateStore(Xtmp0_val, get_reg_ptr(1 + traits::X0), false); - Value* PC_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* PC_val = this->gen_reg_load(rs1 + traits::X0, 0); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 95); + this->gen_sync(POST_SYNC, 95); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 96: C.EBREAK */ - std::tuple __c_ebreak(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.EBREAK"); - this->gen_sync(iss::PRE_SYNC, 96); + this->gen_sync(PRE_SYNC, 96); if(this->disass_enabled){ /* generate console output when executing the command */ - std::vector args { + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("C.EBREAK"), + this->builder.CreateGlobalStringPtr("c.ebreak"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4587,27 +4686,28 @@ private: pc=pc+2; this->gen_raise_trap(0, 3); - this->gen_sync(iss::POST_SYNC, 96); + this->gen_sync(POST_SYNC, 96); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } /* instruction 97: C.SWSP */ - std::tuple __c_swsp(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __c_swsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("C.SWSP"); - this->gen_sync(iss::PRE_SYNC, 97); + this->gen_sync(PRE_SYNC, 97); - uint8_t fld_rs2_val = ((bit_sub<2,5>(instr))); - uint8_t fld_uimm_val = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("C.SWSP x2+0x%1$05x, x%2$d"); - ins_fmter % (uint64_t)fld_uimm_val % (uint64_t)fld_rs2_val; - std::vector args { + auto mnemonic = fmt::format( + "{mnemonic:10} x2+{uimm:#05x}, {rs2}", fmt::arg("mnemonic", "c.swsp"), + fmt::arg("uimm", uimm), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4617,31 +4717,31 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(2 + traits::X0, 0), - this->gen_const(32U, fld_uimm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->gen_const(32U, uimm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 97); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 97); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } /* instruction 98: DII */ - std::tuple __dii(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){ + std::tuple __dii(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("DII"); - this->gen_sync(iss::PRE_SYNC, 98); + this->gen_sync(PRE_SYNC, 98); if(this->disass_enabled){ /* generate console output when executing the command */ - std::vector args { + std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("DII"), + this->builder.CreateGlobalStringPtr("dii"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4651,8 +4751,8 @@ private: this->gen_raise_trap(0, 2); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 98); - bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ + this->gen_sync(POST_SYNC, 98); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); } @@ -4660,18 +4760,17 @@ private: /**************************************************************************** * end opcode definitions ****************************************************************************/ - std::tuple illegal_intruction(virt_addr_t &pc, code_word_t instr, - llvm::BasicBlock *bb) { - this->gen_sync(iss::PRE_SYNC, instr_descr.size()); + std::tuple illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) { + this->gen_sync(iss::PRE_SYNC, instr_descr.size()); this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits::NEXT_PC), true), - get_reg_ptr(traits::PC), true); + get_reg_ptr(traits::PC), true); this->builder.CreateStore( this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits::ICOUNT), true), - this->gen_const(64U, 1)), + this->gen_const(64U, 1)), get_reg_ptr(traits::ICOUNT), true); pc = pc + ((instr & 3) == 3 ? 4 : 2); - this->gen_raise_trap(0, 2); // illegal instruction trap - this->gen_sync(iss::POST_SYNC, instr_descr.size()); + this->gen_raise_trap(0, 2); // illegal instruction trap + this->gen_sync(iss::POST_SYNC, instr_descr.size()); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -4698,8 +4797,8 @@ vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) } template -std::tuple -vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, llvm::BasicBlock *this_block) { +std::tuple +vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) { // we fetch at max 4 byte, alignment is 2 code_word_t insn = 0; const typename traits::addr_t upper_bits = ~traits::PGMASK; @@ -4720,7 +4819,7 @@ vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, } catch (trap_access &ta) { throw trap_access(ta.id, pc.val); } - if (insn == 0x0000006f || (insn & 0xffff) == 0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0' + if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0' // curr pc on stack ++inst_cnt; auto lut_val = extract_fields(insn); @@ -4731,7 +4830,7 @@ vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, return (this->*f)(pc, insn, this_block); } -template void vm_impl::gen_leave_behavior(llvm::BasicBlock *leave_blk) { +template void vm_impl::gen_leave_behavior(BasicBlock *leave_blk) { this->builder.SetInsertPoint(leave_blk); this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits::NEXT_PC), false)); } @@ -4739,51 +4838,46 @@ template void vm_impl::gen_leave_behavior(llvm::BasicBlock template void vm_impl::gen_raise_trap(uint16_t trap_id, uint16_t cause) { auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id); this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true); - this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), - get_reg_ptr(traits::LAST_BRANCH), false); + this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); } template void vm_impl::gen_leave_trap(unsigned lvl) { - std::vector args{ - this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)), - }; + std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) }; this->builder.CreateCall(this->mod->getFunction("leave_trap"), args); auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), - get_reg_ptr(traits::LAST_BRANCH), false); + this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); } template void vm_impl::gen_wait(unsigned type) { - std::vector args{ - this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)), - }; + std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) }; this->builder.CreateCall(this->mod->getFunction("wait"), args); } -template void vm_impl::gen_trap_behavior(llvm::BasicBlock *trap_blk) { +template void vm_impl::gen_trap_behavior(BasicBlock *trap_blk) { this->builder.SetInsertPoint(trap_blk); auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits::TRAP_STATE), true); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); - std::vector args{this->core_ptr, this->adj_to64(trap_state_val), - this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits::PC), false))}; + std::vector args{this->core_ptr, this->adj_to64(trap_state_val), + this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits::PC), false))}; this->builder.CreateCall(this->mod->getFunction("enter_trap"), args); auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateRet(trap_addr_val); } -template inline void vm_impl::gen_trap_check(llvm::BasicBlock *bb) { +template inline void vm_impl::gen_trap_check(BasicBlock *bb) { auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits::TRAP_STATE), true); this->gen_cond_branch(this->builder.CreateICmp( ICmpInst::ICMP_EQ, v, - llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))), + ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))), bb, this->trap_blk, 1); } } // namespace rv32imac -template <> std::unique_ptr create(arch::rv32imac *core, unsigned short port, bool dump) { +template <> +std::unique_ptr create(arch::rv32imac *core, unsigned short port, bool dump) { auto ret = new rv32imac::vm_impl(*core, dump); if (port != 0) debugger::server::run_server(ret, port); return std::unique_ptr(ret); diff --git a/riscv/src/internal/vm_rv64ia.cpp b/riscv/src/internal/vm_rv64ia.cpp index 5e3c2e1..d48e2e6 100644 --- a/riscv/src/internal/vm_rv64ia.cpp +++ b/riscv/src/internal/vm_rv64ia.cpp @@ -1,38 +1,34 @@ -//////////////////////////////////////////////////////////////////////////////// -// Copyright (C) 2017, MINRES Technologies GmbH -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// 3. Neither the name of the copyright holder nor the names of its contributors -// may be used to endorse or promote products derived from this software -// without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. -// -// Contributors: -// eyck@minres.com - initial API and implementation -// -// -//////////////////////////////////////////////////////////////////////////////// +/******************************************************************************* + * Copyright (C) 2017, 2018 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ #include #include @@ -42,14 +38,14 @@ #include #include -#include +#include -#include #include +#include namespace iss { namespace vm { -namespace fp_impl{ +namespace fp_impl { void add_fp_functions_2_module(llvm::Module *, unsigned); } } @@ -74,7 +70,7 @@ public: void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } - target_adapter_if *accquire_target_adapter(server_if *srv) { + target_adapter_if *accquire_target_adapter(server_if *srv) override { debugger_if::dbg_enabled = true; if (vm_base::tgt_adapter == nullptr) vm_base::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); @@ -84,6 +80,8 @@ public: protected: using vm_base::get_reg_ptr; + inline const char *name(size_t index){return traits::reg_aliases.at(index);} + template inline ConstantInt *size(T type) { return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits())); } @@ -97,8 +95,7 @@ protected: return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size)); } - std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, - BasicBlock *) override; + std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override; void gen_leave_behavior(BasicBlock *leave_blk) override; @@ -118,7 +115,7 @@ protected: inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) { Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), - this->get_type(traits::XLEN)); + this->get_type(traits::XLEN)); this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true); } @@ -130,16 +127,16 @@ protected: using this_class = vm_impl; using compile_func = std::tuple (this_class::*)(virt_addr_t &pc, - code_word_t instr, - BasicBlock *bb); + code_word_t instr, + BasicBlock *bb); std::array lut; std::array lut_00, lut_01, lut_10; std::array lut_11; - std::array qlut; + std::array qlut; - std::array lutmasks = { { EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32 } }; + std::array lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}}; void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[], compile_func f) { @@ -370,19 +367,20 @@ private: std::tuple __lwu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LWU"); - this->gen_sync(iss::PRE_SYNC, 0); + this->gen_sync(PRE_SYNC, 0); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LWU x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lwu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -392,18 +390,18 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(64U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 0); + this->gen_sync(POST_SYNC, 0); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -413,19 +411,20 @@ private: std::tuple __ld(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LD"); - this->gen_sync(iss::PRE_SYNC, 1); + this->gen_sync(PRE_SYNC, 1); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LD x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "ld"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -435,18 +434,18 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(64U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 1); + this->gen_sync(POST_SYNC, 1); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -456,19 +455,20 @@ private: std::tuple __sd(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SD"); - this->gen_sync(iss::PRE_SYNC, 2); + this->gen_sync(PRE_SYNC, 2); - int16_t fld_imm_val = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SD x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sd"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -478,16 +478,16 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->gen_const(64U, imm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 2); + this->gen_sync(POST_SYNC, 2); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -497,19 +497,20 @@ private: std::tuple __slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLLI"); - this->gen_sync(iss::PRE_SYNC, 3); + this->gen_sync(PRE_SYNC, 3); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_shamt_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLLI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -517,18 +518,18 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_shamt_val > 31){ + if(shamt > 31){ this->gen_raise_trap(0, 0); } else { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateShl( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(64U, fld_shamt_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_const(64U, shamt)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 3); + this->gen_sync(POST_SYNC, 3); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -538,19 +539,20 @@ private: std::tuple __srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRLI"); - this->gen_sync(iss::PRE_SYNC, 4); + this->gen_sync(PRE_SYNC, 4); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_shamt_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRLI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -558,18 +560,18 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_shamt_val > 31){ + if(shamt > 31){ this->gen_raise_trap(0, 0); } else { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateLShr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(64U, fld_shamt_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_const(64U, shamt)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 4); + this->gen_sync(POST_SYNC, 4); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -579,19 +581,20 @@ private: std::tuple __srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRAI"); - this->gen_sync(iss::PRE_SYNC, 5); + this->gen_sync(PRE_SYNC, 5); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_shamt_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRAI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -599,18 +602,18 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_shamt_val > 31){ + if(shamt > 31){ this->gen_raise_trap(0, 0); } else { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAShr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(64U, fld_shamt_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_const(64U, shamt)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 5); + this->gen_sync(POST_SYNC, 5); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -620,19 +623,20 @@ private: std::tuple __addiw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ADDIW"); - this->gen_sync(iss::PRE_SYNC, 6); + this->gen_sync(PRE_SYNC, 6); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ADDIW x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addiw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -640,23 +644,23 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* res_val = this->builder.CreateAdd( this->gen_ext( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this-> get_type(32) ), 32, true), - this->gen_const(32U, fld_imm_val)); + this->gen_const(32U, imm)); Value* Xtmp0_val = this->gen_ext( res_val, 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 6); + this->gen_sync(POST_SYNC, 6); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -666,19 +670,20 @@ private: std::tuple __slliw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLLIW"); - this->gen_sync(iss::PRE_SYNC, 7); + this->gen_sync(PRE_SYNC, 7); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_shamt_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLLIW x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slliw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -686,21 +691,21 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* sh_val_val = this->builder.CreateShl( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this-> get_type(32) ), - this->gen_const(32U, fld_shamt_val)); + this->gen_const(32U, shamt)); Value* Xtmp0_val = this->gen_ext( sh_val_val, 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 7); + this->gen_sync(POST_SYNC, 7); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -710,19 +715,20 @@ private: std::tuple __srliw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRLIW"); - this->gen_sync(iss::PRE_SYNC, 8); + this->gen_sync(PRE_SYNC, 8); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_shamt_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRLIW x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srliw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -730,21 +736,21 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* sh_val_val = this->builder.CreateLShr( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this-> get_type(32) ), - this->gen_const(32U, fld_shamt_val)); + this->gen_const(32U, shamt)); Value* Xtmp0_val = this->gen_ext( sh_val_val, 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 8); + this->gen_sync(POST_SYNC, 8); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -754,19 +760,20 @@ private: std::tuple __sraiw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRAIW"); - this->gen_sync(iss::PRE_SYNC, 9); + this->gen_sync(PRE_SYNC, 9); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_shamt_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRAIW x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "sraiw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -774,21 +781,21 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* sh_val_val = this->builder.CreateAShr( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this-> get_type(32) ), - this->gen_const(32U, fld_shamt_val)); + this->gen_const(32U, shamt)); Value* Xtmp0_val = this->gen_ext( sh_val_val, 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 9); + this->gen_sync(POST_SYNC, 9); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -798,17 +805,17 @@ private: std::tuple __addw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ADDW"); - this->gen_sync(iss::PRE_SYNC, 10); + this->gen_sync(PRE_SYNC, 10); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("ADDW"), + this->builder.CreateGlobalStringPtr("addw"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -816,24 +823,24 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* res_val = this->builder.CreateAdd( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this-> get_type(32) )); Value* Xtmp0_val = this->gen_ext( res_val, 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 10); + this->gen_sync(POST_SYNC, 10); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -843,17 +850,17 @@ private: std::tuple __subw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SUBW"); - this->gen_sync(iss::PRE_SYNC, 11); + this->gen_sync(PRE_SYNC, 11); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("SUBW"), + this->builder.CreateGlobalStringPtr("subw"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -861,24 +868,24 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* res_val = this->builder.CreateSub( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this-> get_type(32) ), this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this-> get_type(32) )); Value* Xtmp0_val = this->gen_ext( res_val, 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 11); + this->gen_sync(POST_SYNC, 11); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -888,19 +895,20 @@ private: std::tuple __sllw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLLW"); - this->gen_sync(iss::PRE_SYNC, 12); + this->gen_sync(PRE_SYNC, 12); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLLW x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sllw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -908,17 +916,17 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ uint32_t mask_val = 0x1f; Value* count_val = this->builder.CreateAnd( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this-> get_type(32) ), this->gen_const(32U, mask_val)); Value* sh_val_val = this->builder.CreateShl( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this-> get_type(32) ), count_val); @@ -926,10 +934,10 @@ private: sh_val_val, 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 12); + this->gen_sync(POST_SYNC, 12); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -939,19 +947,20 @@ private: std::tuple __srlw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRLW"); - this->gen_sync(iss::PRE_SYNC, 13); + this->gen_sync(PRE_SYNC, 13); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRLW x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srlw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -959,17 +968,17 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ uint32_t mask_val = 0x1f; Value* count_val = this->builder.CreateAnd( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this-> get_type(32) ), this->gen_const(32U, mask_val)); Value* sh_val_val = this->builder.CreateLShr( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this-> get_type(32) ), count_val); @@ -977,10 +986,10 @@ private: sh_val_val, 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 13); + this->gen_sync(POST_SYNC, 13); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -990,19 +999,20 @@ private: std::tuple __sraw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRAW"); - this->gen_sync(iss::PRE_SYNC, 14); + this->gen_sync(PRE_SYNC, 14); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRAW x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sraw"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1010,17 +1020,17 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ uint32_t mask_val = 0x1f; Value* count_val = this->builder.CreateAnd( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), this-> get_type(32) ), this->gen_const(32U, mask_val)); Value* sh_val_val = this->builder.CreateAShr( this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this-> get_type(32) ), count_val); @@ -1028,10 +1038,10 @@ private: sh_val_val, 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 14); + this->gen_sync(POST_SYNC, 14); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1041,18 +1051,19 @@ private: std::tuple __lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LUI"); - this->gen_sync(iss::PRE_SYNC, 15); + this->gen_sync(PRE_SYNC, 15); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - int32_t fld_imm_val = signextend((bit_sub<12,20>(instr) << 12)); + uint8_t rd = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LUI x%1$d, 0x%2$05x"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1060,12 +1071,12 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ - Value* Xtmp0_val = this->gen_const(64U, fld_imm_val); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + if(rd != 0){ + Value* Xtmp0_val = this->gen_const(64U, imm); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 15); + this->gen_sync(POST_SYNC, 15); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1075,18 +1086,19 @@ private: std::tuple __auipc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AUIPC"); - this->gen_sync(iss::PRE_SYNC, 16); + this->gen_sync(PRE_SYNC, 16); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - int32_t fld_imm_val = signextend((bit_sub<12,20>(instr) << 12)); + uint8_t rd = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AUIPC x%1%, 0x%2$08x"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1094,16 +1106,16 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( this->gen_ext( cur_pc_val, 64, true), - this->gen_const(64U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(64U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 16); + this->gen_sync(POST_SYNC, 16); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1113,18 +1125,19 @@ private: std::tuple __jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("JAL"); - this->gen_sync(iss::PRE_SYNC, 17); + this->gen_sync(PRE_SYNC, 17); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - int32_t fld_imm_val = signextend((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + uint8_t rd = ((bit_sub<7,5>(instr))); + int32_t imm = signextend((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("JAL x%1$d, 0x%2$x"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1132,21 +1145,21 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(64U, 4)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* PC_val = this->builder.CreateAdd( this->gen_ext( cur_pc_val, 64, true), - this->gen_const(64U, fld_imm_val)); + this->gen_const(64U, imm)); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(64U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 17); + this->gen_sync(POST_SYNC, 17); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -1155,19 +1168,20 @@ private: std::tuple __jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("JALR"); - this->gen_sync(iss::PRE_SYNC, 18); + this->gen_sync(PRE_SYNC, 18); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("JALR x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1177,9 +1191,9 @@ private: Value* new_pc_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); + this->gen_const(64U, imm)); Value* align_val = this->builder.CreateAnd( new_pc_val, this->gen_const(64U, 0x2)); @@ -1201,11 +1215,11 @@ private: this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(64U, 4)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* PC_val = this->builder.CreateAnd( new_pc_val, @@ -1217,7 +1231,7 @@ private: bb=bbnext; } this->builder.SetInsertPoint(bb); - this->gen_sync(iss::POST_SYNC, 18); + this->gen_sync(POST_SYNC, 18); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -1226,19 +1240,20 @@ private: std::tuple __beq(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BEQ"); - this->gen_sync(iss::PRE_SYNC, 19); + this->gen_sync(PRE_SYNC, 19); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BEQ x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1249,13 +1264,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_EQ, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 64, true), - this->gen_const(64U, fld_imm_val)), + this->gen_const(64U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(64U, 4)), @@ -1263,7 +1278,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(64U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 19); + this->gen_sync(POST_SYNC, 19); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -1272,19 +1287,20 @@ private: std::tuple __bne(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BNE"); - this->gen_sync(iss::PRE_SYNC, 20); + this->gen_sync(PRE_SYNC, 20); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BNE x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1295,13 +1311,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 64, true), - this->gen_const(64U, fld_imm_val)), + this->gen_const(64U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(64U, 4)), @@ -1309,7 +1325,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(64U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 20); + this->gen_sync(POST_SYNC, 20); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -1318,19 +1334,20 @@ private: std::tuple __blt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BLT"); - this->gen_sync(iss::PRE_SYNC, 21); + this->gen_sync(PRE_SYNC, 21); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BLT x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1342,16 +1359,16 @@ private: this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 64, true)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 64, true), - this->gen_const(64U, fld_imm_val)), + this->gen_const(64U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(64U, 4)), @@ -1359,7 +1376,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(64U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 21); + this->gen_sync(POST_SYNC, 21); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -1368,19 +1385,20 @@ private: std::tuple __bge(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BGE"); - this->gen_sync(iss::PRE_SYNC, 22); + this->gen_sync(PRE_SYNC, 22); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BGE x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1392,16 +1410,16 @@ private: this->builder.CreateICmp( ICmpInst::ICMP_SGE, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 64, true)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 64, true), - this->gen_const(64U, fld_imm_val)), + this->gen_const(64U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(64U, 4)), @@ -1409,7 +1427,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(64U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 22); + this->gen_sync(POST_SYNC, 22); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -1418,19 +1436,20 @@ private: std::tuple __bltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BLTU"); - this->gen_sync(iss::PRE_SYNC, 23); + this->gen_sync(PRE_SYNC, 23); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BLTU x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1441,13 +1460,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 64, true), - this->gen_const(64U, fld_imm_val)), + this->gen_const(64U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(64U, 4)), @@ -1455,7 +1474,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(64U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 23); + this->gen_sync(POST_SYNC, 23); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -1464,19 +1483,20 @@ private: std::tuple __bgeu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("BGEU"); - this->gen_sync(iss::PRE_SYNC, 24); + this->gen_sync(PRE_SYNC, 24); - int16_t fld_imm_val = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("BGEU x%1$d, x%2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1487,13 +1507,13 @@ private: Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_UGE, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), this->builder.CreateAdd( this->gen_ext( cur_pc_val, 64, true), - this->gen_const(64U, fld_imm_val)), + this->gen_const(64U, imm)), this->builder.CreateAdd( cur_pc_val, this->gen_const(64U, 4)), @@ -1501,7 +1521,7 @@ private: this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(64U, pc.val), "is_cont_v"); this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits::LAST_BRANCH), false); - this->gen_sync(iss::POST_SYNC, 24); + this->gen_sync(POST_SYNC, 24); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -1510,19 +1530,20 @@ private: std::tuple __lb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LB"); - this->gen_sync(iss::PRE_SYNC, 25); + this->gen_sync(PRE_SYNC, 25); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LB x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1532,18 +1553,18 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(64U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 8/8), 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 25); + this->gen_sync(POST_SYNC, 25); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1553,19 +1574,20 @@ private: std::tuple __lh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LH"); - this->gen_sync(iss::PRE_SYNC, 26); + this->gen_sync(PRE_SYNC, 26); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LH x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1575,18 +1597,18 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(64U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 16/8), 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 26); + this->gen_sync(POST_SYNC, 26); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1596,19 +1618,20 @@ private: std::tuple __lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LW"); - this->gen_sync(iss::PRE_SYNC, 27); + this->gen_sync(PRE_SYNC, 27); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LW x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1618,18 +1641,18 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(64U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 27); + this->gen_sync(POST_SYNC, 27); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1639,19 +1662,20 @@ private: std::tuple __lbu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LBU"); - this->gen_sync(iss::PRE_SYNC, 28); + this->gen_sync(PRE_SYNC, 28); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LBU x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1661,18 +1685,18 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(64U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 8/8), 64, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 28); + this->gen_sync(POST_SYNC, 28); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1682,19 +1706,20 @@ private: std::tuple __lhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LHU"); - this->gen_sync(iss::PRE_SYNC, 29); + this->gen_sync(PRE_SYNC, 29); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LHU x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1704,18 +1729,18 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); - if(fld_rd_val != 0){ + this->gen_const(64U, imm)); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 16/8), 64, false); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 29); + this->gen_sync(POST_SYNC, 29); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1725,19 +1750,20 @@ private: std::tuple __sb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SB"); - this->gen_sync(iss::PRE_SYNC, 30); + this->gen_sync(PRE_SYNC, 30); - int16_t fld_imm_val = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SB x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1747,16 +1773,16 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->gen_const(64U, imm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(8))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 30); + this->gen_sync(POST_SYNC, 30); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1766,19 +1792,20 @@ private: std::tuple __sh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SH"); - this->gen_sync(iss::PRE_SYNC, 31); + this->gen_sync(PRE_SYNC, 31); - int16_t fld_imm_val = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SH x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1788,16 +1815,16 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->gen_const(64U, imm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(16))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 31); + this->gen_sync(POST_SYNC, 31); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1807,19 +1834,20 @@ private: std::tuple __sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SW"); - this->gen_sync(iss::PRE_SYNC, 32); + this->gen_sync(PRE_SYNC, 32); - int16_t fld_imm_val = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SW x%1$d, %2%(x%3$d)"); - ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1829,16 +1857,16 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->gen_const(64U, imm)); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 32); + this->gen_sync(POST_SYNC, 32); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1848,19 +1876,20 @@ private: std::tuple __addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ADDI"); - this->gen_sync(iss::PRE_SYNC, 33); + this->gen_sync(PRE_SYNC, 33); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ADDI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1868,16 +1897,16 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(64U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 33); + this->gen_sync(POST_SYNC, 33); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1887,19 +1916,20 @@ private: std::tuple __slti(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLTI"); - this->gen_sync(iss::PRE_SYNC, 34); + this->gen_sync(PRE_SYNC, 34); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLTI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1907,21 +1937,21 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), - this->gen_const(64U, fld_imm_val)), + this->gen_const(64U, imm)), this->gen_const(64U, 1), this->gen_const(64U, 0), 64); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 34); + this->gen_sync(POST_SYNC, 34); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1931,19 +1961,20 @@ private: std::tuple __sltiu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLTIU"); - this->gen_sync(iss::PRE_SYNC, 35); + this->gen_sync(PRE_SYNC, 35); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLTIU x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1951,20 +1982,20 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - int64_t full_imm_val = fld_imm_val; - if(fld_rd_val != 0){ + int64_t full_imm_val = imm; + if(rd != 0){ Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this->gen_const(64U, full_imm_val)), this->gen_const(64U, 1), this->gen_const(64U, 0), 64); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 35); + this->gen_sync(POST_SYNC, 35); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -1974,19 +2005,20 @@ private: std::tuple __xori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("XORI"); - this->gen_sync(iss::PRE_SYNC, 36); + this->gen_sync(PRE_SYNC, 36); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("XORI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -1994,14 +2026,16 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateXor( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(64U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_ext( + this->gen_reg_load(rs1 + traits::X0, 0), + 64, true), + this->gen_const(64U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 36); + this->gen_sync(POST_SYNC, 36); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2011,19 +2045,20 @@ private: std::tuple __ori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ORI"); - this->gen_sync(iss::PRE_SYNC, 37); + this->gen_sync(PRE_SYNC, 37); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ORI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2031,14 +2066,16 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateOr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(64U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_ext( + this->gen_reg_load(rs1 + traits::X0, 0), + 64, true), + this->gen_const(64U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 37); + this->gen_sync(POST_SYNC, 37); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2048,19 +2085,20 @@ private: std::tuple __andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ANDI"); - this->gen_sync(iss::PRE_SYNC, 38); + this->gen_sync(PRE_SYNC, 38); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - int16_t fld_imm_val = signextend((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + int16_t imm = signextend((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2068,14 +2106,16 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAnd( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_const(64U, fld_imm_val)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_ext( + this->gen_reg_load(rs1 + traits::X0, 0), + 64, true), + this->gen_const(64U, imm)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 38); + this->gen_sync(POST_SYNC, 38); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2085,19 +2125,20 @@ private: std::tuple __add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ADD"); - this->gen_sync(iss::PRE_SYNC, 39); + this->gen_sync(PRE_SYNC, 39); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("ADD x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2105,14 +2146,14 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAdd( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 39); + this->gen_sync(POST_SYNC, 39); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2122,19 +2163,20 @@ private: std::tuple __sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SUB"); - this->gen_sync(iss::PRE_SYNC, 40); + this->gen_sync(PRE_SYNC, 40); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SUB x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2142,14 +2184,14 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateSub( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 40); + this->gen_sync(POST_SYNC, 40); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2159,19 +2201,20 @@ private: std::tuple __sll(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLL"); - this->gen_sync(iss::PRE_SYNC, 41); + this->gen_sync(PRE_SYNC, 41); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLL x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2179,16 +2222,18 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateShl( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this->builder.CreateAnd( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(64U, 0x1f))); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs2 + traits::X0, 0), + this->builder.CreateSub( + this->gen_const(64U, 64), + this->gen_const(64U, 1)))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 41); + this->gen_sync(POST_SYNC, 41); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2198,19 +2243,20 @@ private: std::tuple __slt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLT"); - this->gen_sync(iss::PRE_SYNC, 42); + this->gen_sync(PRE_SYNC, 42); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLT x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2218,23 +2264,23 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 64, true)), this->gen_const(64U, 1), this->gen_const(64U, 0), 64); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 42); + this->gen_sync(POST_SYNC, 42); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2244,19 +2290,20 @@ private: std::tuple __sltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SLTU"); - this->gen_sync(iss::PRE_SYNC, 43); + this->gen_sync(PRE_SYNC, 43); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SLTU x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2264,25 +2311,25 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), 64, false), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 64, false)), this->gen_const(64U, 1), this->gen_const(64U, 0), 64); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 43); + this->gen_sync(POST_SYNC, 43); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2292,19 +2339,20 @@ private: std::tuple __xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("XOR"); - this->gen_sync(iss::PRE_SYNC, 44); + this->gen_sync(PRE_SYNC, 44); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("XOR x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2312,14 +2360,14 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateXor( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 44); + this->gen_sync(POST_SYNC, 44); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2329,19 +2377,20 @@ private: std::tuple __srl(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRL"); - this->gen_sync(iss::PRE_SYNC, 45); + this->gen_sync(PRE_SYNC, 45); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRL x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2349,16 +2398,18 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateLShr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this->builder.CreateAnd( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(64U, 0x1f))); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs2 + traits::X0, 0), + this->builder.CreateSub( + this->gen_const(64U, 64), + this->gen_const(64U, 1)))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 45); + this->gen_sync(POST_SYNC, 45); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2368,19 +2419,20 @@ private: std::tuple __sra(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRA"); - this->gen_sync(iss::PRE_SYNC, 46); + this->gen_sync(PRE_SYNC, 46); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SRA x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2388,16 +2440,18 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAShr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this->gen_reg_load(rs1 + traits::X0, 0), this->builder.CreateAnd( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(64U, 0x1f))); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs2 + traits::X0, 0), + this->builder.CreateSub( + this->gen_const(64U, 64), + this->gen_const(64U, 1)))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 46); + this->gen_sync(POST_SYNC, 46); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2407,19 +2461,20 @@ private: std::tuple __or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("OR"); - this->gen_sync(iss::PRE_SYNC, 47); + this->gen_sync(PRE_SYNC, 47); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("OR x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2427,14 +2482,14 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateOr( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 47); + this->gen_sync(POST_SYNC, 47); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2444,19 +2499,20 @@ private: std::tuple __and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AND"); - this->gen_sync(iss::PRE_SYNC, 48); + this->gen_sync(PRE_SYNC, 48); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AND x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2464,14 +2520,14 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = this->builder.CreateAnd( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_reg_load(rs1 + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 48); + this->gen_sync(POST_SYNC, 48); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2481,18 +2537,18 @@ private: std::tuple __fence(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FENCE"); - this->gen_sync(iss::PRE_SYNC, 49); + this->gen_sync(PRE_SYNC, 49); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_succ_val = ((bit_sub<20,4>(instr))); - uint8_t fld_pred_val = ((bit_sub<24,4>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("FENCE"), + this->builder.CreateGlobalStringPtr("fence"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2502,15 +2558,15 @@ private: Value* FENCEtmp0_val = this->builder.CreateOr( this->builder.CreateShl( - this->gen_const(64U, fld_pred_val), + this->gen_const(64U, pred), this->gen_const(64U, 4)), - this->gen_const(64U, fld_succ_val)); + this->gen_const(64U, succ)); this->gen_write_mem( traits::FENCE, this->gen_const(64U, 0), this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 49); + this->gen_sync(POST_SYNC, 49); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2520,17 +2576,17 @@ private: std::tuple __fence_i(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("FENCE_I"); - this->gen_sync(iss::PRE_SYNC, 50); + this->gen_sync(PRE_SYNC, 50); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint16_t fld_imm_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("FENCE_I"), + this->builder.CreateGlobalStringPtr("fence_i"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2538,14 +2594,14 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* FENCEtmp0_val = this->gen_const(64U, fld_imm_val); + Value* FENCEtmp0_val = this->gen_const(64U, imm); this->gen_write_mem( traits::FENCE, this->gen_const(64U, 1), this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(64))); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 50); + this->gen_sync(POST_SYNC, 50); this->gen_trap_check(this->leave_blk); return std::make_tuple(FLUSH, nullptr); } @@ -2554,14 +2610,14 @@ private: std::tuple __ecall(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("ECALL"); - this->gen_sync(iss::PRE_SYNC, 51); + this->gen_sync(PRE_SYNC, 51); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("ECALL"), + this->builder.CreateGlobalStringPtr("ecall"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2570,7 +2626,7 @@ private: pc=pc+4; this->gen_raise_trap(0, 11); - this->gen_sync(iss::POST_SYNC, 51); + this->gen_sync(POST_SYNC, 51); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -2579,14 +2635,14 @@ private: std::tuple __ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("EBREAK"); - this->gen_sync(iss::PRE_SYNC, 52); + this->gen_sync(PRE_SYNC, 52); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("EBREAK"), + this->builder.CreateGlobalStringPtr("ebreak"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2595,7 +2651,7 @@ private: pc=pc+4; this->gen_raise_trap(0, 3); - this->gen_sync(iss::POST_SYNC, 52); + this->gen_sync(POST_SYNC, 52); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -2604,14 +2660,14 @@ private: std::tuple __uret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("URET"); - this->gen_sync(iss::PRE_SYNC, 53); + this->gen_sync(PRE_SYNC, 53); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("URET"), + this->builder.CreateGlobalStringPtr("uret"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2620,7 +2676,7 @@ private: pc=pc+4; this->gen_leave_trap(0); - this->gen_sync(iss::POST_SYNC, 53); + this->gen_sync(POST_SYNC, 53); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -2629,14 +2685,14 @@ private: std::tuple __sret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SRET"); - this->gen_sync(iss::PRE_SYNC, 54); + this->gen_sync(PRE_SYNC, 54); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("SRET"), + this->builder.CreateGlobalStringPtr("sret"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2645,7 +2701,7 @@ private: pc=pc+4; this->gen_leave_trap(1); - this->gen_sync(iss::POST_SYNC, 54); + this->gen_sync(POST_SYNC, 54); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -2654,14 +2710,14 @@ private: std::tuple __mret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("MRET"); - this->gen_sync(iss::PRE_SYNC, 55); + this->gen_sync(PRE_SYNC, 55); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("MRET"), + this->builder.CreateGlobalStringPtr("mret"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2670,7 +2726,7 @@ private: pc=pc+4; this->gen_leave_trap(3); - this->gen_sync(iss::POST_SYNC, 55); + this->gen_sync(POST_SYNC, 55); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } @@ -2679,14 +2735,14 @@ private: std::tuple __wfi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("WFI"); - this->gen_sync(iss::PRE_SYNC, 56); + this->gen_sync(PRE_SYNC, 56); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("WFI"), + this->builder.CreateGlobalStringPtr("wfi"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2696,7 +2752,7 @@ private: this->gen_wait(1); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 56); + this->gen_sync(POST_SYNC, 56); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2706,16 +2762,16 @@ private: std::tuple __sfence_vma(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SFENCE.VMA"); - this->gen_sync(iss::PRE_SYNC, 57); + this->gen_sync(PRE_SYNC, 57); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr("SFENCE.VMA"), + this->builder.CreateGlobalStringPtr("sfence.vma"), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2723,18 +2779,18 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* FENCEtmp0_val = this->gen_const(64U, fld_rs1_val); + Value* FENCEtmp0_val = this->gen_const(64U, rs1); this->gen_write_mem( traits::FENCE, this->gen_const(64U, 2), this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(64))); - Value* FENCEtmp1_val = this->gen_const(64U, fld_rs2_val); + Value* FENCEtmp1_val = this->gen_const(64U, rs2); this->gen_write_mem( traits::FENCE, this->gen_const(64U, 3), this->builder.CreateZExtOrTrunc(FENCEtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 57); + this->gen_sync(POST_SYNC, 57); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2744,19 +2800,20 @@ private: std::tuple __csrrw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRW"); - this->gen_sync(iss::PRE_SYNC, 58); + this->gen_sync(PRE_SYNC, 58); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRW x%1$d, %2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2764,25 +2821,25 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* rs_val_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ - Value* csr_val_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 64/8); + Value* rs_val_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ + Value* csr_val_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 64/8); Value* CSRtmp0_val = rs_val_val; this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp0_val,this->get_type(64))); Value* Xtmp1_val = csr_val_val; - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } else { Value* CSRtmp2_val = rs_val_val; this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp2_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 58); + this->gen_sync(POST_SYNC, 58); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2792,19 +2849,20 @@ private: std::tuple __csrrs(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRS"); - this->gen_sync(iss::PRE_SYNC, 59); + this->gen_sync(PRE_SYNC, 59); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRS x%1$d, %2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2812,23 +2870,23 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 64/8); - Value* xrs1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ + Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 64/8); + Value* xrs1_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ Value* Xtmp0_val = xrd_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - if(fld_rs1_val != 0){ + if(rs1 != 0){ Value* CSRtmp1_val = this->builder.CreateOr( xrd_val, xrs1_val); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 59); + this->gen_sync(POST_SYNC, 59); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2838,19 +2896,20 @@ private: std::tuple __csrrc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRC"); - this->gen_sync(iss::PRE_SYNC, 60); + this->gen_sync(PRE_SYNC, 60); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRC x%1$d, %2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2858,23 +2917,23 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 64/8); - Value* xrs1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ + Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 64/8); + Value* xrs1_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ Value* Xtmp0_val = xrd_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - if(fld_rs1_val != 0){ + if(rs1 != 0){ Value* CSRtmp1_val = this->builder.CreateAnd( xrd_val, this->builder.CreateNot(xrs1_val)); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 60); + this->gen_sync(POST_SYNC, 60); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2884,19 +2943,20 @@ private: std::tuple __csrrwi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRWI"); - this->gen_sync(iss::PRE_SYNC, 61); + this->gen_sync(PRE_SYNC, 61); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_zimm_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRWI x%1$d, %2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2904,20 +2964,20 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ - Value* Xtmp0_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 64/8); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + if(rd != 0){ + Value* Xtmp0_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 64/8); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* CSRtmp1_val = this->gen_ext( - this->gen_const(64U, fld_zimm_val), + this->gen_const(64U, zimm), 64, false); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 61); + this->gen_sync(POST_SYNC, 61); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2927,19 +2987,20 @@ private: std::tuple __csrrsi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRSI"); - this->gen_sync(iss::PRE_SYNC, 62); + this->gen_sync(PRE_SYNC, 62); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_zimm_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRSI x%1$d, %2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2947,25 +3008,25 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 64/8); - if(fld_zimm_val != 0){ + Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 64/8); + if(zimm != 0){ Value* CSRtmp0_val = this->builder.CreateOr( res_val, this->gen_ext( - this->gen_const(64U, fld_zimm_val), + this->gen_const(64U, zimm), 64, false)); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp0_val,this->get_type(64))); } - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp1_val = res_val; - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 62); + this->gen_sync(POST_SYNC, 62); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -2975,19 +3036,20 @@ private: std::tuple __csrrci(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("CSRRCI"); - this->gen_sync(iss::PRE_SYNC, 63); + this->gen_sync(PRE_SYNC, 63); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_zimm_val = ((bit_sub<15,5>(instr))); - uint16_t fld_csr_val = ((bit_sub<20,12>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("CSRRCI x%1$d, %2$d, 0x%3$x"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -2995,25 +3057,25 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 64/8); - if(fld_rd_val != 0){ + Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, csr), 64/8); + if(rd != 0){ Value* Xtmp0_val = res_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - if(fld_zimm_val != 0){ + if(zimm != 0){ Value* CSRtmp1_val = this->builder.CreateAnd( res_val, this->builder.CreateNot(this->gen_ext( - this->gen_const(64U, fld_zimm_val), + this->gen_const(64U, zimm), 64, false))); this->gen_write_mem( traits::CSR, - this->gen_const(16U, fld_csr_val), + this->gen_const(16U, csr), this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 63); + this->gen_sync(POST_SYNC, 63); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3023,20 +3085,21 @@ private: std::tuple __lr_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LR.D"); - this->gen_sync(iss::PRE_SYNC, 64); + this->gen_sync(PRE_SYNC, 64); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LR.D x%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "lr.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3044,13 +3107,13 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + if(rd != 0){ + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* REStmp1_val = this->gen_ext( this->builder.CreateNeg(this->gen_const(8U, 1)), 64, @@ -3061,7 +3124,7 @@ private: this->builder.CreateZExtOrTrunc(REStmp1_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 64); + this->gen_sync(POST_SYNC, 64); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3071,21 +3134,22 @@ private: std::tuple __sc_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SC.D"); - this->gen_sync(iss::PRE_SYNC, 65); + this->gen_sync(PRE_SYNC, 65); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SC.D x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sc.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3093,7 +3157,7 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res_val = this->gen_read_mem(traits::RES, offs_val, 8/8); { BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); @@ -3108,21 +3172,21 @@ private: bb_else); this->builder.SetInsertPoint(bb_then); { - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 1); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 1); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(64)));if(fld_rd_val != 0){ + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(64)));if(rd != 0){ Value* Xtmp1_val = this->gen_const(64U, 0); - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp2_val = this->gen_const(64U, 1); - this->builder.CreateStore(Xtmp2_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp2_val, get_reg_ptr(rd + traits::X0), false); } } this->builder.CreateBr(bbnext); @@ -3130,7 +3194,7 @@ private: } this->builder.SetInsertPoint(bb); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 65); + this->gen_sync(POST_SYNC, 65); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3140,21 +3204,22 @@ private: std::tuple __amoswap_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOSWAP.D"); - this->gen_sync(iss::PRE_SYNC, 66); + this->gen_sync(PRE_SYNC, 66); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOSWAP.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoswap.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3162,21 +3227,21 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - Value* MEMtmp1_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp1_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 66); + this->gen_sync(POST_SYNC, 66); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3186,21 +3251,22 @@ private: std::tuple __amoadd_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOADD.D"); - this->gen_sync(iss::PRE_SYNC, 67); + this->gen_sync(PRE_SYNC, 67); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOADD.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoadd.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3208,25 +3274,25 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateAdd( res_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 67); + this->gen_sync(POST_SYNC, 67); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3236,21 +3302,22 @@ private: std::tuple __amoxor_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOXOR.D"); - this->gen_sync(iss::PRE_SYNC, 68); + this->gen_sync(PRE_SYNC, 68); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOXOR.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoxor.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3258,25 +3325,25 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateXor( res_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 68); + this->gen_sync(POST_SYNC, 68); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3286,21 +3353,22 @@ private: std::tuple __amoand_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOAND.D"); - this->gen_sync(iss::PRE_SYNC, 69); + this->gen_sync(PRE_SYNC, 69); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOAND.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoand.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3308,25 +3376,25 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateAnd( res_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 69); + this->gen_sync(POST_SYNC, 69); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3336,21 +3404,22 @@ private: std::tuple __amoor_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOOR.D"); - this->gen_sync(iss::PRE_SYNC, 70); + this->gen_sync(PRE_SYNC, 70); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOOR.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoor.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3358,25 +3427,25 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateOr( res_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 70); + this->gen_sync(POST_SYNC, 70); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3386,21 +3455,22 @@ private: std::tuple __amomin_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMIN.D"); - this->gen_sync(iss::PRE_SYNC, 71); + this->gen_sync(PRE_SYNC, 71); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMIN.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amomin.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3408,14 +3478,14 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3424,9 +3494,9 @@ private: res_val, 64, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 64, true)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), res_val, 64); Value* MEMtmp1_val = res_val; @@ -3435,7 +3505,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 71); + this->gen_sync(POST_SYNC, 71); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3445,21 +3515,22 @@ private: std::tuple __amomax_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMAX.D"); - this->gen_sync(iss::PRE_SYNC, 72); + this->gen_sync(PRE_SYNC, 72); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMAX.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amomax.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3467,14 +3538,14 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3483,9 +3554,9 @@ private: res_val, 64, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 64, true)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), res_val, 64); Value* MEMtmp1_val = res2_val; @@ -3494,7 +3565,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 72); + this->gen_sync(POST_SYNC, 72); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3504,21 +3575,22 @@ private: std::tuple __amominu_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMINU.D"); - this->gen_sync(iss::PRE_SYNC, 73); + this->gen_sync(PRE_SYNC, 73); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMINU.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amominu.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3526,21 +3598,21 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, false); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_UGT, res_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), + this->gen_reg_load(rs2 + traits::X0, 0), res_val, 64); Value* MEMtmp1_val = res2_val; @@ -3549,7 +3621,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 73); + this->gen_sync(POST_SYNC, 73); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3559,21 +3631,22 @@ private: std::tuple __amomaxu_d(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMAXU.D"); - this->gen_sync(iss::PRE_SYNC, 74); + this->gen_sync(PRE_SYNC, 74); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMAXU.D x%1$d, x%2$d, x%3$d (aqu=%a,rel=%rl)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amomaxu.d"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3581,21 +3654,21 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, false); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, res_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), + this->gen_reg_load(rs2 + traits::X0, 0), res_val, 64); Value* MEMtmp1_val = res2_val; @@ -3604,7 +3677,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 74); + this->gen_sync(POST_SYNC, 74); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3614,20 +3687,21 @@ private: std::tuple __lr_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("LR.W"); - this->gen_sync(iss::PRE_SYNC, 75); + this->gen_sync(PRE_SYNC, 75); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("LR.W x%1$d, x%2$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}", fmt::arg("mnemonic", "lr.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3635,13 +3709,13 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - if(fld_rd_val != 0){ - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + if(rd != 0){ + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); Value* REStmp1_val = this->gen_ext( this->builder.CreateNeg(this->gen_const(8U, 1)), 32, @@ -3652,7 +3726,7 @@ private: this->builder.CreateZExtOrTrunc(REStmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 75); + this->gen_sync(POST_SYNC, 75); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3662,21 +3736,22 @@ private: std::tuple __sc_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("SC.W"); - this->gen_sync(iss::PRE_SYNC, 76); + this->gen_sync(PRE_SYNC, 76); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("SC.W x%1$d, x%2$d, x%3$d"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sc.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3684,7 +3759,7 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_read_mem(traits::RES, offs_val, 32/8); { BasicBlock* bbnext = BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); @@ -3698,7 +3773,7 @@ private: bbnext); this->builder.SetInsertPoint(bb_then); { - Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 1); + Value* MEMtmp0_val = this->gen_reg_load(rs2 + traits::X0, 1); this->gen_write_mem( traits::MEM, offs_val, @@ -3708,7 +3783,7 @@ private: bb=bbnext; } this->builder.SetInsertPoint(bb); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp1_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, @@ -3717,10 +3792,10 @@ private: this->gen_const(64U, 0), this->gen_const(64U, 1), 64); - this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(rd + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 76); + this->gen_sync(POST_SYNC, 76); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3730,21 +3805,22 @@ private: std::tuple __amoswap_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOSWAP.W"); - this->gen_sync(iss::PRE_SYNC, 77); + this->gen_sync(PRE_SYNC, 77); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOSWAP.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoswap.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3752,21 +3828,21 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - if(fld_rd_val != 0){ + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); + if(rd != 0){ Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, true); - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } - Value* MEMtmp1_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp1_val = this->gen_reg_load(rs2 + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 77); + this->gen_sync(POST_SYNC, 77); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3776,21 +3852,22 @@ private: std::tuple __amoadd_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOADD.W"); - this->gen_sync(iss::PRE_SYNC, 78); + this->gen_sync(PRE_SYNC, 78); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOADD.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoadd.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3798,25 +3875,25 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateAdd( res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 78); + this->gen_sync(POST_SYNC, 78); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3826,21 +3903,22 @@ private: std::tuple __amoxor_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOXOR.W"); - this->gen_sync(iss::PRE_SYNC, 79); + this->gen_sync(PRE_SYNC, 79); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOXOR.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoxor.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3848,25 +3926,25 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateXor( res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 79); + this->gen_sync(POST_SYNC, 79); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3876,21 +3954,22 @@ private: std::tuple __amoand_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOAND.W"); - this->gen_sync(iss::PRE_SYNC, 80); + this->gen_sync(PRE_SYNC, 80); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOAND.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoand.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3898,25 +3977,25 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateAnd( res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 80); + this->gen_sync(POST_SYNC, 80); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3926,21 +4005,22 @@ private: std::tuple __amoor_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOOR.W"); - this->gen_sync(iss::PRE_SYNC, 81); + this->gen_sync(PRE_SYNC, 81); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOOR.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amoor.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3948,25 +4028,25 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->builder.CreateOr( res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)); + this->gen_reg_load(rs2 + traits::X0, 0)); Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 81); + this->gen_sync(POST_SYNC, 81); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -3976,21 +4056,22 @@ private: std::tuple __amomin_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMIN.W"); - this->gen_sync(iss::PRE_SYNC, 82); + this->gen_sync(PRE_SYNC, 82); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMIN.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amomin.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -3998,14 +4079,14 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -4014,9 +4095,9 @@ private: res1_val, 64, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 64, true)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), res1_val, 64); Value* MEMtmp1_val = res2_val; @@ -4025,7 +4106,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 82); + this->gen_sync(POST_SYNC, 82); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4035,21 +4116,22 @@ private: std::tuple __amomax_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMAX.W"); - this->gen_sync(iss::PRE_SYNC, 83); + this->gen_sync(PRE_SYNC, 83); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMAX.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amomax.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4057,14 +4139,14 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, true); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -4073,9 +4155,9 @@ private: res1_val, 64, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), 64, true)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0), res1_val, 64); Value* MEMtmp1_val = res2_val; @@ -4084,7 +4166,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 83); + this->gen_sync(POST_SYNC, 83); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4094,21 +4176,22 @@ private: std::tuple __amominu_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMINU.W"); - this->gen_sync(iss::PRE_SYNC, 84); + this->gen_sync(PRE_SYNC, 84); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMINU.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amominu.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4116,21 +4199,21 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, false); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_UGT, res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), + this->gen_reg_load(rs2 + traits::X0, 0), res1_val, 64); Value* MEMtmp1_val = res2_val; @@ -4139,7 +4222,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 84); + this->gen_sync(POST_SYNC, 84); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4149,21 +4232,22 @@ private: std::tuple __amomaxu_w(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ bb->setName("AMOMAXU.W"); - this->gen_sync(iss::PRE_SYNC, 85); + this->gen_sync(PRE_SYNC, 85); - uint8_t fld_rd_val = ((bit_sub<7,5>(instr))); - uint8_t fld_rs1_val = ((bit_sub<15,5>(instr))); - uint8_t fld_rs2_val = ((bit_sub<20,5>(instr))); - uint8_t fld_rl_val = ((bit_sub<25,1>(instr))); - uint8_t fld_aq_val = ((bit_sub<26,1>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + uint8_t rl = ((bit_sub<25,1>(instr))); + uint8_t aq = ((bit_sub<26,1>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ - boost::format ins_fmter("AMOMAXU.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)"); - ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val; + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2} (aqu={aq},rel={rl})", fmt::arg("mnemonic", "amomaxu.w"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("aq", aq), fmt::arg("rl", rl)); std::vector args { this->core_ptr, this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(ins_fmter.str()), + this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } @@ -4171,21 +4255,21 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + Value* offs_val = this->gen_reg_load(rs1 + traits::X0, 0); Value* res1_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, false); - if(fld_rd_val != 0){ + if(rd != 0){ Value* Xtmp0_val = res1_val; - this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, res1_val, - this->gen_reg_load(fld_rs2_val + traits::X0, 0)), - this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_reg_load(rs2 + traits::X0, 0)), + this->gen_reg_load(rs2 + traits::X0, 0), res1_val, 64); Value* MEMtmp1_val = res2_val; @@ -4194,7 +4278,7 @@ private: offs_val, this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_sync(iss::POST_SYNC, 85); + this->gen_sync(POST_SYNC, 85); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ this->gen_trap_check(bb); return std::make_tuple(CONT, bb); @@ -4203,8 +4287,7 @@ private: /**************************************************************************** * end opcode definitions ****************************************************************************/ - std::tuple illegal_intruction(virt_addr_t &pc, code_word_t instr, - BasicBlock *bb) { + std::tuple illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) { this->gen_sync(iss::PRE_SYNC, instr_descr.size()); this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits::NEXT_PC), true), get_reg_ptr(traits::PC), true); @@ -4248,7 +4331,7 @@ vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, const typename traits::addr_t upper_bits = ~traits::PGMASK; phys_addr_t paddr(pc); try { - uint8_t *const data = (uint8_t *)&insn; + auto *const data = (uint8_t *)&insn; paddr = this->core.v2p(pc); if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary auto res = this->core.read(paddr, 2, data); @@ -4286,9 +4369,7 @@ template void vm_impl::gen_raise_trap(uint16_t trap_id, ui } template void vm_impl::gen_leave_trap(unsigned lvl) { - std::vector args{ - this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)), - }; + std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) }; this->builder.CreateCall(this->mod->getFunction("leave_trap"), args); auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); @@ -4296,20 +4377,17 @@ template void vm_impl::gen_leave_trap(unsigned lvl) { } template void vm_impl::gen_wait(unsigned type) { - std::vector args{ - this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)), - }; + std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) }; this->builder.CreateCall(this->mod->getFunction("wait"), args); } template void vm_impl::gen_trap_behavior(BasicBlock *trap_blk) { this->builder.SetInsertPoint(trap_blk); auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits::TRAP_STATE), true); - this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); - std::vector args{ - this->core_ptr, - this->adj_to64(trap_state_val), - this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits::PC), false))}; + this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), + get_reg_ptr(traits::LAST_BRANCH), false); + std::vector args{this->core_ptr, this->adj_to64(trap_state_val), + this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits::PC), false))}; this->builder.CreateCall(this->mod->getFunction("enter_trap"), args); auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateRet(trap_addr_val); @@ -4327,10 +4405,9 @@ template inline void vm_impl::gen_trap_check(BasicBlock *b template <> std::unique_ptr create(arch::rv64ia *core, unsigned short port, bool dump) { - std::unique_ptr> ret = - std::make_unique>(*core, dump); - if (port != 0) debugger::server::run_server(ret.get(), port); - return ret; + auto ret = new rv64ia::vm_impl(*core, dump); + if (port != 0) debugger::server::run_server(ret, port); + return std::unique_ptr(ret); } } // namespace iss diff --git a/riscv/src/iss/rv32gc.cpp b/riscv/src/iss/rv32gc.cpp index 0e9bb96..489a56c 100644 --- a/riscv/src/iss/rv32gc.cpp +++ b/riscv/src/iss/rv32gc.cpp @@ -49,6 +49,11 @@ extern "C" { using namespace iss::arch; +constexpr std::array iss::arch::traits::reg_names; +constexpr std::array iss::arch::traits::reg_aliases; +constexpr std::array iss::arch::traits::reg_bit_widths; +constexpr std::array iss::arch::traits::reg_byte_offsets; + rv32gc::rv32gc() { reg.icount=0; } diff --git a/riscv/src/iss/rv32imac.cpp b/riscv/src/iss/rv32imac.cpp index 86500d8..b9e4dd7 100644 --- a/riscv/src/iss/rv32imac.cpp +++ b/riscv/src/iss/rv32imac.cpp @@ -49,8 +49,10 @@ extern "C" { using namespace iss::arch; -constexpr std::array iss::arch::traits::RV32IMAC_reg_size; -constexpr std::array iss::arch::traits::RV32IMAC_reg_byte_offset; +constexpr std::array iss::arch::traits::reg_names; +constexpr std::array iss::arch::traits::reg_aliases; +constexpr std::array iss::arch::traits::reg_bit_widths; +constexpr std::array iss::arch::traits::reg_byte_offsets; rv32imac::rv32imac() { reg.icount = 0; diff --git a/riscv/src/iss/rv64ia.cpp b/riscv/src/iss/rv64ia.cpp index f5f542e..8e71d07 100644 --- a/riscv/src/iss/rv64ia.cpp +++ b/riscv/src/iss/rv64ia.cpp @@ -52,6 +52,11 @@ extern "C" { using namespace iss::arch; +constexpr std::array iss::arch::traits::reg_names; +constexpr std::array iss::arch::traits::reg_aliases; +constexpr std::array iss::arch::traits::reg_bit_widths; +constexpr std::array iss::arch::traits::reg_byte_offsets; + rv64ia::rv64ia() { reg.icount = 0; reg.machine_state = 0x3;} rv64ia::~rv64ia(){} diff --git a/sc-components b/sc-components index 0f5b5f6..a21b2e5 160000 --- a/sc-components +++ b/sc-components @@ -1 +1 @@ -Subproject commit 0f5b5f68e7d5d481b4f8da2620df633495c989d9 +Subproject commit a21b2e57a2f18ff9e683d529a106ae2a8d2639c9