From 759061b56916c8cf55bbc52ab372609d3a7d0258 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sun, 29 Oct 2023 17:06:56 +0100 Subject: [PATCH] applies clang-format changes --- .clang-format | 13 +- softfloat/build/Linux-386-GCC/platform.h | 7 +- softfloat/build/Linux-386-SSE2-GCC/platform.h | 7 +- .../build/Linux-ARM-VFPv2-GCC/platform.h | 7 +- softfloat/build/Linux-x86_64-GCC/platform.h | 7 +- softfloat/build/Win32-MinGW/platform.h | 7 +- softfloat/build/Win32-SSE2-MinGW/platform.h | 7 +- softfloat/build/Win64-MinGW-w64/platform.h | 7 +- .../build/template-FAST_INT64/platform.h | 17 +- .../build/template-not-FAST_INT64/platform.h | 17 +- softfloat/source/8086-SSE/specialize.h | 122 +- softfloat/source/8086/specialize.h | 122 +- .../source/ARM-VFPv2-defaultNaN/specialize.h | 168 +- softfloat/source/ARM-VFPv2/specialize.h | 120 +- softfloat/source/RISCV/specialize.h | 122 +- softfloat/source/include/internals.h | 309 +- softfloat/source/include/opts-GCC.h | 65 +- softfloat/source/include/primitiveTypes.h | 65 +- softfloat/source/include/primitives.h | 384 +- softfloat/source/include/softfloat.h | 479 +- softfloat/source/include/softfloat_types.h | 27 +- src/iss/arch/hwl.h | 71 +- src/iss/arch/riscv_hart_common.h | 67 +- src/iss/arch/riscv_hart_m_p.h | 760 +-- src/iss/arch/riscv_hart_msu_vp.h | 724 +-- src/iss/arch/riscv_hart_mu_p.h | 1014 ++-- src/iss/arch/tgc5c.cpp | 31 +- src/iss/arch/tgc5c.h | 176 +- src/iss/arch/tgc_mapper.h | 21 +- src/iss/arch/wt_cache.h | 93 +- src/iss/debugger/riscv_target_adapter.h | 225 +- src/iss/factory.h | 40 +- src/iss/plugin/cycle_estimate.cpp | 37 +- src/iss/plugin/cycle_estimate.h | 24 +- src/iss/plugin/instruction_count.cpp | 41 +- src/iss/plugin/instruction_count.h | 14 +- src/main.cpp | 87 +- src/sysc/core_complex.cpp | 258 +- src/sysc/core_complex.h | 51 +- src/sysc/iss_factory.h | 40 +- src/sysc/register_tgc_c.cpp | 106 +- src/sysc/sc_core_adapter.h | 113 +- src/sysc/sc_core_adapter_if.h | 9 +- src/vm/asmjit/helper_func.h | 488 +- src/vm/asmjit/vm_tgc5c.cpp | 4317 +++++++------ src/vm/fp_functions.cpp | 372 +- src/vm/fp_functions.h | 8 +- src/vm/interp/vm_tgc5c.cpp | 3140 +++++----- src/vm/llvm/fp_impl.cpp | 94 +- src/vm/llvm/vm_tgc5c.cpp | 5402 ++++++++--------- src/vm/tcc/vm_tgc5c.cpp | 4264 ++++++------- 51 files changed, 11493 insertions(+), 12673 deletions(-) diff --git a/.clang-format b/.clang-format index 0d03f70..a2683b8 100644 --- a/.clang-format +++ b/.clang-format @@ -1,4 +1,3 @@ ---- Language: Cpp # BasedOnStyle: LLVM # should be in line with IndentWidth @@ -13,8 +12,8 @@ AllowAllParametersOfDeclarationOnNextLine: true AllowShortBlocksOnASingleLine: false AllowShortCaseLabelsOnASingleLine: false AllowShortFunctionsOnASingleLine: All -AllowShortIfStatementsOnASingleLine: true -AllowShortLoopsOnASingleLine: true +AllowShortIfStatementsOnASingleLine: false +AllowShortLoopsOnASingleLine: false AlwaysBreakAfterDefinitionReturnType: None AlwaysBreakAfterReturnType: None AlwaysBreakBeforeMultilineStrings: false @@ -39,8 +38,8 @@ BreakBeforeTernaryOperators: true BreakConstructorInitializersBeforeComma: true BreakAfterJavaFieldAnnotations: false BreakStringLiterals: true -ColumnLimit: 120 -CommentPragmas: '^ IWYU pragma:' +ColumnLimit: 140 +CommentPragmas: '^( IWYU pragma:| @suppress)' ConstructorInitializerAllOnOneLineOrOnePerLine: false ConstructorInitializerIndentWidth: 0 ContinuationIndentWidth: 4 @@ -76,13 +75,13 @@ PenaltyBreakFirstLessLess: 120 PenaltyBreakString: 1000 PenaltyExcessCharacter: 1000000 PenaltyReturnTypeOnItsOwnLine: 60 -PointerAlignment: Right +PointerAlignment: Left ReflowComments: true SortIncludes: true SpaceAfterCStyleCast: false SpaceAfterTemplateKeyword: true SpaceBeforeAssignmentOperators: true -SpaceBeforeParens: ControlStatements +SpaceBeforeParens: Never SpaceInEmptyParentheses: false SpacesBeforeTrailingComments: 1 SpacesInAngles: false diff --git a/softfloat/build/Linux-386-GCC/platform.h b/softfloat/build/Linux-386-GCC/platform.h index 420aa4e..eb224b1 100644 --- a/softfloat/build/Linux-386-GCC/platform.h +++ b/softfloat/build/Linux-386-GCC/platform.h @@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define LITTLEENDIAN 1 /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #ifdef __GNUC_STDC_INLINE__ #define INLINE inline #else @@ -47,7 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #endif /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define SOFTFLOAT_BUILTIN_CLZ 1 #include "opts-GCC.h" - diff --git a/softfloat/build/Linux-386-SSE2-GCC/platform.h b/softfloat/build/Linux-386-SSE2-GCC/platform.h index 420aa4e..eb224b1 100644 --- a/softfloat/build/Linux-386-SSE2-GCC/platform.h +++ b/softfloat/build/Linux-386-SSE2-GCC/platform.h @@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define LITTLEENDIAN 1 /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #ifdef __GNUC_STDC_INLINE__ #define INLINE inline #else @@ -47,7 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #endif /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define SOFTFLOAT_BUILTIN_CLZ 1 #include "opts-GCC.h" - diff --git a/softfloat/build/Linux-ARM-VFPv2-GCC/platform.h b/softfloat/build/Linux-ARM-VFPv2-GCC/platform.h index 420aa4e..eb224b1 100644 --- a/softfloat/build/Linux-ARM-VFPv2-GCC/platform.h +++ b/softfloat/build/Linux-ARM-VFPv2-GCC/platform.h @@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define LITTLEENDIAN 1 /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #ifdef __GNUC_STDC_INLINE__ #define INLINE inline #else @@ -47,7 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #endif /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define SOFTFLOAT_BUILTIN_CLZ 1 #include "opts-GCC.h" - diff --git a/softfloat/build/Linux-x86_64-GCC/platform.h b/softfloat/build/Linux-x86_64-GCC/platform.h index 92c3044..630cb43 100644 --- a/softfloat/build/Linux-x86_64-GCC/platform.h +++ b/softfloat/build/Linux-x86_64-GCC/platform.h @@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define LITTLEENDIAN 1 /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #ifdef __GNUC_STDC_INLINE__ //#define INLINE inline #define INLINE static @@ -48,10 +48,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #endif /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #ifdef __GNUC__ #define SOFTFLOAT_BUILTIN_CLZ 1 #define SOFTFLOAT_INTRINSIC_INT128 1 #endif #include "opts-GCC.h" - diff --git a/softfloat/build/Win32-MinGW/platform.h b/softfloat/build/Win32-MinGW/platform.h index 420aa4e..eb224b1 100644 --- a/softfloat/build/Win32-MinGW/platform.h +++ b/softfloat/build/Win32-MinGW/platform.h @@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define LITTLEENDIAN 1 /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #ifdef __GNUC_STDC_INLINE__ #define INLINE inline #else @@ -47,7 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #endif /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define SOFTFLOAT_BUILTIN_CLZ 1 #include "opts-GCC.h" - diff --git a/softfloat/build/Win32-SSE2-MinGW/platform.h b/softfloat/build/Win32-SSE2-MinGW/platform.h index 420aa4e..eb224b1 100644 --- a/softfloat/build/Win32-SSE2-MinGW/platform.h +++ b/softfloat/build/Win32-SSE2-MinGW/platform.h @@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define LITTLEENDIAN 1 /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #ifdef __GNUC_STDC_INLINE__ #define INLINE inline #else @@ -47,7 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #endif /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define SOFTFLOAT_BUILTIN_CLZ 1 #include "opts-GCC.h" - diff --git a/softfloat/build/Win64-MinGW-w64/platform.h b/softfloat/build/Win64-MinGW-w64/platform.h index 2fccb6c..737a708 100644 --- a/softfloat/build/Win64-MinGW-w64/platform.h +++ b/softfloat/build/Win64-MinGW-w64/platform.h @@ -35,11 +35,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define LITTLEENDIAN 1 /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #ifdef __GNUC_STDC_INLINE__ #define INLINE inline #else @@ -47,8 +47,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #endif /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ #define SOFTFLOAT_BUILTIN_CLZ 1 #define SOFTFLOAT_INTRINSIC_INT128 1 #include "opts-GCC.h" - diff --git a/softfloat/build/template-FAST_INT64/platform.h b/softfloat/build/template-FAST_INT64/platform.h index b63e2a7..b59e6c5 100644 --- a/softfloat/build/template-FAST_INT64/platform.h +++ b/softfloat/build/template-FAST_INT64/platform.h @@ -37,14 +37,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // Edit lines marked with `==>'. See "SoftFloat-source.html". /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -==> #define LITTLEENDIAN 1 + *----------------------------------------------------------------------------*/ +== > #define LITTLEENDIAN 1 -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -==> #define INLINE inline - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -==> #define THREAD_LOCAL _Thread_local + /*---------------------------------------------------------------------------- + *----------------------------------------------------------------------------*/ + == > #define INLINE inline + /*---------------------------------------------------------------------------- + *----------------------------------------------------------------------------*/ + == > #define THREAD_LOCAL _Thread_local diff --git a/softfloat/build/template-not-FAST_INT64/platform.h b/softfloat/build/template-not-FAST_INT64/platform.h index b63e2a7..b59e6c5 100644 --- a/softfloat/build/template-not-FAST_INT64/platform.h +++ b/softfloat/build/template-not-FAST_INT64/platform.h @@ -37,14 +37,13 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // Edit lines marked with `==>'. See "SoftFloat-source.html". /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -==> #define LITTLEENDIAN 1 + *----------------------------------------------------------------------------*/ +== > #define LITTLEENDIAN 1 -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -==> #define INLINE inline - -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -==> #define THREAD_LOCAL _Thread_local + /*---------------------------------------------------------------------------- + *----------------------------------------------------------------------------*/ + == > #define INLINE inline + /*---------------------------------------------------------------------------- + *----------------------------------------------------------------------------*/ + == > #define THREAD_LOCAL _Thread_local diff --git a/softfloat/source/8086-SSE/specialize.h b/softfloat/source/8086-SSE/specialize.h index 5fe119a..23b1632 100644 --- a/softfloat/source/8086-SSE/specialize.h +++ b/softfloat/source/8086-SSE/specialize.h @@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef specialize_h #define specialize_h 1 -#include -#include #include "primitiveTypes.h" #include "softfloat.h" +#include +#include /*---------------------------------------------------------------------------- | Default value for 'softfloat_detectTininess'. @@ -53,21 +53,21 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *----------------------------------------------------------------------------*/ #define ui32_fromPosOverflow 0xFFFFFFFF #define ui32_fromNegOverflow 0xFFFFFFFF -#define ui32_fromNaN 0xFFFFFFFF -#define i32_fromPosOverflow (-0x7FFFFFFF - 1) -#define i32_fromNegOverflow (-0x7FFFFFFF - 1) -#define i32_fromNaN (-0x7FFFFFFF - 1) +#define ui32_fromNaN 0xFFFFFFFF +#define i32_fromPosOverflow (-0x7FFFFFFF - 1) +#define i32_fromNegOverflow (-0x7FFFFFFF - 1) +#define i32_fromNaN (-0x7FFFFFFF - 1) /*---------------------------------------------------------------------------- | The values to return on conversions to 64-bit integer formats that raise an | invalid exception. *----------------------------------------------------------------------------*/ -#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define ui64_fromNegOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define ui64_fromNaN UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define i64_fromPosOverflow (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) -#define i64_fromNegOverflow (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) -#define i64_fromNaN (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) +#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF) +#define ui64_fromNegOverflow UINT64_C(0xFFFFFFFFFFFFFFFF) +#define ui64_fromNaN UINT64_C(0xFFFFFFFFFFFFFFFF) +#define i64_fromPosOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1) +#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1) +#define i64_fromNaN (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1) /*---------------------------------------------------------------------------- | "Common NaN" structure, used to transfer NaN representations from one format @@ -92,7 +92,7 @@ struct commonNaN { | 16-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF)) +#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF)) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts @@ -100,13 +100,13 @@ struct commonNaN { | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr ); +void softfloat_f16UIToCommonNaN(uint_fast16_t uiA, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ); +uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- @@ -114,8 +114,7 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ); | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast16_t - softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB ); +uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 32-bit floating-point NaN. @@ -127,7 +126,7 @@ uint_fast16_t | 32-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF)) +#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF)) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts @@ -135,13 +134,13 @@ uint_fast16_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr ); +void softfloat_f32UIToCommonNaN(uint_fast32_t uiA, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ); +uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- @@ -149,20 +148,20 @@ uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ); | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast32_t - softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB ); +uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 64-bit floating-point NaN. *----------------------------------------------------------------------------*/ -#define defaultNaNF64UI UINT64_C( 0xFFF8000000000000 ) +#define defaultNaNF64UI UINT64_C(0xFFF8000000000000) /*---------------------------------------------------------------------------- | Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a | 64-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF ))) +#define softfloat_isSigNaNF64UI(uiA) \ + ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF))) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts @@ -170,13 +169,13 @@ uint_fast32_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr ); +void softfloat_f64UIToCommonNaN(uint_fast64_t uiA, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ); +uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- @@ -184,14 +183,13 @@ uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ); | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast64_t - softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ); +uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 80-bit extended floating-point NaN. *----------------------------------------------------------------------------*/ #define defaultNaNExtF80UI64 0xFFFF -#define defaultNaNExtF80UI0 UINT64_C( 0xC000000000000000 ) +#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000) /*---------------------------------------------------------------------------- | Returns true when the 80-bit unsigned integer formed from concatenating @@ -199,7 +197,8 @@ uint_fast64_t | floating-point signaling NaN. | Note: This macro evaluates its arguments more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF ))) +#define softfloat_isSigNaNExtF80UI(uiA64, uiA0) \ + ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF))) #ifdef SOFTFLOAT_FAST_INT64 @@ -215,16 +214,14 @@ uint_fast64_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_extF80UIToCommonNaN( - uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ); +void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended | floating-point NaN, and returns the bit pattern of this value as an unsigned | integer. *----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); +struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting the unsigned integer formed from concatenating 'uiA64' and @@ -235,19 +232,13 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); | result. If either original floating-point value is a signaling NaN, the | invalid exception is raised. *----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNExtF80UI( - uint_fast16_t uiA64, - uint_fast64_t uiA0, - uint_fast16_t uiB64, - uint_fast64_t uiB0 - ); +struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 128-bit floating-point NaN. *----------------------------------------------------------------------------*/ -#define defaultNaNF128UI64 UINT64_C( 0xFFFF800000000000 ) -#define defaultNaNF128UI0 UINT64_C( 0 ) +#define defaultNaNF128UI64 UINT64_C(0xFFFF800000000000) +#define defaultNaNF128UI0 UINT64_C(0) /*---------------------------------------------------------------------------- | Returns true when the 128-bit unsigned integer formed from concatenating @@ -255,7 +246,8 @@ struct uint128 | point signaling NaN. | Note: This macro evaluates its arguments more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF )))) +#define softfloat_isSigNaNF128UI(uiA64, uiA0) \ + ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF)))) /*---------------------------------------------------------------------------- | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' @@ -264,15 +256,13 @@ struct uint128 | pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid exception | is raised. *----------------------------------------------------------------------------*/ -void - softfloat_f128UIToCommonNaN( - uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ); +void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); +struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*); /*---------------------------------------------------------------------------- | Interpreting the unsigned integer formed from concatenating 'uiA64' and @@ -283,13 +273,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); | If either original floating-point value is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNF128UI( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0 - ); +struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0); #else @@ -304,18 +288,14 @@ struct uint128 | common NaN at the location pointed to by 'zPtr'. If the NaN is a signaling | NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_extF80MToCommonNaN( - const struct extFloat80M *aSPtr, struct commonNaN *zPtr ); +void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended | floating-point NaN, and stores this NaN at the location pointed to by | 'zSPtr'. *----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToExtF80M( - const struct commonNaN *aPtr, struct extFloat80M *zSPtr ); +void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr); /*---------------------------------------------------------------------------- | Assuming at least one of the two 80-bit extended floating-point values @@ -323,12 +303,7 @@ void | at the location pointed to by 'zSPtr'. If either original floating-point | value is a signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNExtF80M( - const struct extFloat80M *aSPtr, - const struct extFloat80M *bSPtr, - struct extFloat80M *zSPtr - ); +void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 128-bit floating-point NaN. @@ -336,7 +311,7 @@ void #define defaultNaNF128UI96 0xFFFF8000 #define defaultNaNF128UI64 0 #define defaultNaNF128UI32 0 -#define defaultNaNF128UI0 0 +#define defaultNaNF128UI0 0 /*---------------------------------------------------------------------------- | Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN, @@ -346,8 +321,7 @@ void | four 32-bit elements that concatenate in the platform's normal endian order | to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr ); +void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point @@ -355,8 +329,7 @@ void | 'zWPtr' points to an array of four 32-bit elements that concatenate in the | platform's normal endian order to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ); +void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr); /*---------------------------------------------------------------------------- | Assuming at least one of the two 128-bit floating-point values pointed to by @@ -366,11 +339,8 @@ void | and 'zWPtr' points to an array of four 32-bit elements that concatenate in | the platform's normal endian order to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNF128M( - const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr ); +void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr); #endif #endif - diff --git a/softfloat/source/8086/specialize.h b/softfloat/source/8086/specialize.h index 5fe119a..23b1632 100644 --- a/softfloat/source/8086/specialize.h +++ b/softfloat/source/8086/specialize.h @@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef specialize_h #define specialize_h 1 -#include -#include #include "primitiveTypes.h" #include "softfloat.h" +#include +#include /*---------------------------------------------------------------------------- | Default value for 'softfloat_detectTininess'. @@ -53,21 +53,21 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *----------------------------------------------------------------------------*/ #define ui32_fromPosOverflow 0xFFFFFFFF #define ui32_fromNegOverflow 0xFFFFFFFF -#define ui32_fromNaN 0xFFFFFFFF -#define i32_fromPosOverflow (-0x7FFFFFFF - 1) -#define i32_fromNegOverflow (-0x7FFFFFFF - 1) -#define i32_fromNaN (-0x7FFFFFFF - 1) +#define ui32_fromNaN 0xFFFFFFFF +#define i32_fromPosOverflow (-0x7FFFFFFF - 1) +#define i32_fromNegOverflow (-0x7FFFFFFF - 1) +#define i32_fromNaN (-0x7FFFFFFF - 1) /*---------------------------------------------------------------------------- | The values to return on conversions to 64-bit integer formats that raise an | invalid exception. *----------------------------------------------------------------------------*/ -#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define ui64_fromNegOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define ui64_fromNaN UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define i64_fromPosOverflow (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) -#define i64_fromNegOverflow (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) -#define i64_fromNaN (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) +#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF) +#define ui64_fromNegOverflow UINT64_C(0xFFFFFFFFFFFFFFFF) +#define ui64_fromNaN UINT64_C(0xFFFFFFFFFFFFFFFF) +#define i64_fromPosOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1) +#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1) +#define i64_fromNaN (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1) /*---------------------------------------------------------------------------- | "Common NaN" structure, used to transfer NaN representations from one format @@ -92,7 +92,7 @@ struct commonNaN { | 16-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF)) +#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF)) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts @@ -100,13 +100,13 @@ struct commonNaN { | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr ); +void softfloat_f16UIToCommonNaN(uint_fast16_t uiA, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ); +uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- @@ -114,8 +114,7 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ); | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast16_t - softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB ); +uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 32-bit floating-point NaN. @@ -127,7 +126,7 @@ uint_fast16_t | 32-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF)) +#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF)) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts @@ -135,13 +134,13 @@ uint_fast16_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr ); +void softfloat_f32UIToCommonNaN(uint_fast32_t uiA, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ); +uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- @@ -149,20 +148,20 @@ uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ); | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast32_t - softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB ); +uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 64-bit floating-point NaN. *----------------------------------------------------------------------------*/ -#define defaultNaNF64UI UINT64_C( 0xFFF8000000000000 ) +#define defaultNaNF64UI UINT64_C(0xFFF8000000000000) /*---------------------------------------------------------------------------- | Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a | 64-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF ))) +#define softfloat_isSigNaNF64UI(uiA) \ + ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF))) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts @@ -170,13 +169,13 @@ uint_fast32_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr ); +void softfloat_f64UIToCommonNaN(uint_fast64_t uiA, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ); +uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- @@ -184,14 +183,13 @@ uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ); | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast64_t - softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ); +uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 80-bit extended floating-point NaN. *----------------------------------------------------------------------------*/ #define defaultNaNExtF80UI64 0xFFFF -#define defaultNaNExtF80UI0 UINT64_C( 0xC000000000000000 ) +#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000) /*---------------------------------------------------------------------------- | Returns true when the 80-bit unsigned integer formed from concatenating @@ -199,7 +197,8 @@ uint_fast64_t | floating-point signaling NaN. | Note: This macro evaluates its arguments more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF ))) +#define softfloat_isSigNaNExtF80UI(uiA64, uiA0) \ + ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF))) #ifdef SOFTFLOAT_FAST_INT64 @@ -215,16 +214,14 @@ uint_fast64_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_extF80UIToCommonNaN( - uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ); +void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended | floating-point NaN, and returns the bit pattern of this value as an unsigned | integer. *----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); +struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting the unsigned integer formed from concatenating 'uiA64' and @@ -235,19 +232,13 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); | result. If either original floating-point value is a signaling NaN, the | invalid exception is raised. *----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNExtF80UI( - uint_fast16_t uiA64, - uint_fast64_t uiA0, - uint_fast16_t uiB64, - uint_fast64_t uiB0 - ); +struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 128-bit floating-point NaN. *----------------------------------------------------------------------------*/ -#define defaultNaNF128UI64 UINT64_C( 0xFFFF800000000000 ) -#define defaultNaNF128UI0 UINT64_C( 0 ) +#define defaultNaNF128UI64 UINT64_C(0xFFFF800000000000) +#define defaultNaNF128UI0 UINT64_C(0) /*---------------------------------------------------------------------------- | Returns true when the 128-bit unsigned integer formed from concatenating @@ -255,7 +246,8 @@ struct uint128 | point signaling NaN. | Note: This macro evaluates its arguments more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF )))) +#define softfloat_isSigNaNF128UI(uiA64, uiA0) \ + ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF)))) /*---------------------------------------------------------------------------- | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' @@ -264,15 +256,13 @@ struct uint128 | pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid exception | is raised. *----------------------------------------------------------------------------*/ -void - softfloat_f128UIToCommonNaN( - uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ); +void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); +struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*); /*---------------------------------------------------------------------------- | Interpreting the unsigned integer formed from concatenating 'uiA64' and @@ -283,13 +273,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); | If either original floating-point value is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNF128UI( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0 - ); +struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0); #else @@ -304,18 +288,14 @@ struct uint128 | common NaN at the location pointed to by 'zPtr'. If the NaN is a signaling | NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_extF80MToCommonNaN( - const struct extFloat80M *aSPtr, struct commonNaN *zPtr ); +void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended | floating-point NaN, and stores this NaN at the location pointed to by | 'zSPtr'. *----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToExtF80M( - const struct commonNaN *aPtr, struct extFloat80M *zSPtr ); +void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr); /*---------------------------------------------------------------------------- | Assuming at least one of the two 80-bit extended floating-point values @@ -323,12 +303,7 @@ void | at the location pointed to by 'zSPtr'. If either original floating-point | value is a signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNExtF80M( - const struct extFloat80M *aSPtr, - const struct extFloat80M *bSPtr, - struct extFloat80M *zSPtr - ); +void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 128-bit floating-point NaN. @@ -336,7 +311,7 @@ void #define defaultNaNF128UI96 0xFFFF8000 #define defaultNaNF128UI64 0 #define defaultNaNF128UI32 0 -#define defaultNaNF128UI0 0 +#define defaultNaNF128UI0 0 /*---------------------------------------------------------------------------- | Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN, @@ -346,8 +321,7 @@ void | four 32-bit elements that concatenate in the platform's normal endian order | to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr ); +void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point @@ -355,8 +329,7 @@ void | 'zWPtr' points to an array of four 32-bit elements that concatenate in the | platform's normal endian order to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ); +void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr); /*---------------------------------------------------------------------------- | Assuming at least one of the two 128-bit floating-point values pointed to by @@ -366,11 +339,8 @@ void | and 'zWPtr' points to an array of four 32-bit elements that concatenate in | the platform's normal endian order to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNF128M( - const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr ); +void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr); #endif #endif - diff --git a/softfloat/source/ARM-VFPv2-defaultNaN/specialize.h b/softfloat/source/ARM-VFPv2-defaultNaN/specialize.h index 2c481a2..9d8e569 100644 --- a/softfloat/source/ARM-VFPv2-defaultNaN/specialize.h +++ b/softfloat/source/ARM-VFPv2-defaultNaN/specialize.h @@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef specialize_h #define specialize_h 1 -#include -#include #include "primitiveTypes.h" #include "softfloat.h" +#include +#include /*---------------------------------------------------------------------------- | Default value for 'softfloat_detectTininess'. @@ -53,27 +53,29 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *----------------------------------------------------------------------------*/ #define ui32_fromPosOverflow 0xFFFFFFFF #define ui32_fromNegOverflow 0 -#define ui32_fromNaN 0 -#define i32_fromPosOverflow 0x7FFFFFFF -#define i32_fromNegOverflow (-0x7FFFFFFF - 1) -#define i32_fromNaN 0 +#define ui32_fromNaN 0 +#define i32_fromPosOverflow 0x7FFFFFFF +#define i32_fromNegOverflow (-0x7FFFFFFF - 1) +#define i32_fromNaN 0 /*---------------------------------------------------------------------------- | The values to return on conversions to 64-bit integer formats that raise an | invalid exception. *----------------------------------------------------------------------------*/ -#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF ) +#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF) #define ui64_fromNegOverflow 0 -#define ui64_fromNaN 0 -#define i64_fromPosOverflow INT64_C( 0x7FFFFFFFFFFFFFFF ) -#define i64_fromNegOverflow (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) -#define i64_fromNaN 0 +#define ui64_fromNaN 0 +#define i64_fromPosOverflow INT64_C(0x7FFFFFFFFFFFFFFF) +#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1) +#define i64_fromNaN 0 /*---------------------------------------------------------------------------- | "Common NaN" structure, used to transfer NaN representations from one format | to another. *----------------------------------------------------------------------------*/ -struct commonNaN { char _unused; }; +struct commonNaN { + char _unused; +}; /*---------------------------------------------------------------------------- | The bit pattern for a default generated 16-bit floating-point NaN. @@ -85,7 +87,7 @@ struct commonNaN { char _unused; }; | 16-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF)) +#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF)) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts @@ -93,13 +95,15 @@ struct commonNaN { char _unused; }; | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -#define softfloat_f16UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x0200) ) softfloat_raiseFlags( softfloat_flag_invalid ) +#define softfloat_f16UIToCommonNaN(uiA, zPtr) \ + if(!((uiA)&0x0200)) \ + softfloat_raiseFlags(softfloat_flag_invalid) /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -#define softfloat_commonNaNToF16UI( aPtr ) ((uint_fast16_t) defaultNaNF16UI) +#define softfloat_commonNaNToF16UI(aPtr) ((uint_fast16_t)defaultNaNF16UI) /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- @@ -107,8 +111,7 @@ struct commonNaN { char _unused; }; | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast16_t - softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB ); +uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 32-bit floating-point NaN. @@ -120,7 +123,7 @@ uint_fast16_t | 32-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF)) +#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF)) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts @@ -128,13 +131,15 @@ uint_fast16_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -#define softfloat_f32UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & 0x00400000) ) softfloat_raiseFlags( softfloat_flag_invalid ) +#define softfloat_f32UIToCommonNaN(uiA, zPtr) \ + if(!((uiA)&0x00400000)) \ + softfloat_raiseFlags(softfloat_flag_invalid) /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -#define softfloat_commonNaNToF32UI( aPtr ) ((uint_fast32_t) defaultNaNF32UI) +#define softfloat_commonNaNToF32UI(aPtr) ((uint_fast32_t)defaultNaNF32UI) /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- @@ -142,20 +147,20 @@ uint_fast16_t | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast32_t - softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB ); +uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 64-bit floating-point NaN. *----------------------------------------------------------------------------*/ -#define defaultNaNF64UI UINT64_C( 0x7FF8000000000000 ) +#define defaultNaNF64UI UINT64_C(0x7FF8000000000000) /*---------------------------------------------------------------------------- | Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a | 64-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF ))) +#define softfloat_isSigNaNF64UI(uiA) \ + ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF))) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts @@ -163,13 +168,15 @@ uint_fast32_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -#define softfloat_f64UIToCommonNaN( uiA, zPtr ) if ( ! ((uiA) & UINT64_C( 0x0008000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid ) +#define softfloat_f64UIToCommonNaN(uiA, zPtr) \ + if(!((uiA)&UINT64_C(0x0008000000000000))) \ + softfloat_raiseFlags(softfloat_flag_invalid) /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -#define softfloat_commonNaNToF64UI( aPtr ) ((uint_fast64_t) defaultNaNF64UI) +#define softfloat_commonNaNToF64UI(aPtr) ((uint_fast64_t)defaultNaNF64UI) /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- @@ -177,14 +184,13 @@ uint_fast32_t | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast64_t - softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ); +uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 80-bit extended floating-point NaN. *----------------------------------------------------------------------------*/ #define defaultNaNExtF80UI64 0x7FFF -#define defaultNaNExtF80UI0 UINT64_C( 0xC000000000000000 ) +#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000) /*---------------------------------------------------------------------------- | Returns true when the 80-bit unsigned integer formed from concatenating @@ -192,7 +198,8 @@ uint_fast64_t | floating-point signaling NaN. | Note: This macro evaluates its arguments more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF ))) +#define softfloat_isSigNaNExtF80UI(uiA64, uiA0) \ + ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF))) #ifdef SOFTFLOAT_FAST_INT64 @@ -208,24 +215,25 @@ uint_fast64_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -#define softfloat_extF80UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA0) & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid ) +#define softfloat_extF80UIToCommonNaN(uiA64, uiA0, zPtr) \ + if(!((uiA0)&UINT64_C(0x4000000000000000))) \ + softfloat_raiseFlags(softfloat_flag_invalid) /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended | floating-point NaN, and returns the bit pattern of this value as an unsigned | integer. *----------------------------------------------------------------------------*/ -#if defined INLINE && ! defined softfloat_commonNaNToExtF80UI +#if defined INLINE && !defined softfloat_commonNaNToExtF80UI INLINE -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ) -{ +struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr) { struct uint128 uiZ; uiZ.v64 = defaultNaNExtF80UI64; - uiZ.v0 = defaultNaNExtF80UI0; + uiZ.v0 = defaultNaNExtF80UI0; return uiZ; } #else -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); +struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr); #endif /*---------------------------------------------------------------------------- @@ -237,19 +245,13 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); | result. If either original floating-point value is a signaling NaN, the | invalid exception is raised. *----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNExtF80UI( - uint_fast16_t uiA64, - uint_fast64_t uiA0, - uint_fast16_t uiB64, - uint_fast64_t uiB0 - ); +struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 128-bit floating-point NaN. *----------------------------------------------------------------------------*/ -#define defaultNaNF128UI64 UINT64_C( 0x7FFF800000000000 ) -#define defaultNaNF128UI0 UINT64_C( 0 ) +#define defaultNaNF128UI64 UINT64_C(0x7FFF800000000000) +#define defaultNaNF128UI0 UINT64_C(0) /*---------------------------------------------------------------------------- | Returns true when the 128-bit unsigned integer formed from concatenating @@ -257,7 +259,8 @@ struct uint128 | point signaling NaN. | Note: This macro evaluates its arguments more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF )))) +#define softfloat_isSigNaNF128UI(uiA64, uiA0) \ + ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF)))) /*---------------------------------------------------------------------------- | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' @@ -266,23 +269,24 @@ struct uint128 | pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid exception | is raised. *----------------------------------------------------------------------------*/ -#define softfloat_f128UIToCommonNaN( uiA64, uiA0, zPtr ) if ( ! ((uiA64) & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid ) +#define softfloat_f128UIToCommonNaN(uiA64, uiA0, zPtr) \ + if(!((uiA64)&UINT64_C(0x0000800000000000))) \ + softfloat_raiseFlags(softfloat_flag_invalid) /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -#if defined INLINE && ! defined softfloat_commonNaNToF128UI +#if defined INLINE && !defined softfloat_commonNaNToF128UI INLINE -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN *aPtr ) -{ +struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN* aPtr) { struct uint128 uiZ; uiZ.v64 = defaultNaNF128UI64; - uiZ.v0 = defaultNaNF128UI0; + uiZ.v0 = defaultNaNF128UI0; return uiZ; } #else -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); +struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*); #endif /*---------------------------------------------------------------------------- @@ -294,13 +298,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); | If either original floating-point value is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNF128UI( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0 - ); +struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0); #else @@ -315,26 +313,23 @@ struct uint128 | common NaN at the location pointed to by 'zPtr'. If the NaN is a signaling | NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -#define softfloat_extF80MToCommonNaN( aSPtr, zPtr ) if ( ! ((aSPtr)->signif & UINT64_C( 0x4000000000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid ) +#define softfloat_extF80MToCommonNaN(aSPtr, zPtr) \ + if(!((aSPtr)->signif & UINT64_C(0x4000000000000000))) \ + softfloat_raiseFlags(softfloat_flag_invalid) /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended | floating-point NaN, and stores this NaN at the location pointed to by | 'zSPtr'. *----------------------------------------------------------------------------*/ -#if defined INLINE && ! defined softfloat_commonNaNToExtF80M +#if defined INLINE && !defined softfloat_commonNaNToExtF80M INLINE -void - softfloat_commonNaNToExtF80M( - const struct commonNaN *aPtr, struct extFloat80M *zSPtr ) -{ +void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr) { zSPtr->signExp = defaultNaNExtF80UI64; - zSPtr->signif = defaultNaNExtF80UI0; + zSPtr->signif = defaultNaNExtF80UI0; } #else -void - softfloat_commonNaNToExtF80M( - const struct commonNaN *aPtr, struct extFloat80M *zSPtr ); +void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr); #endif /*---------------------------------------------------------------------------- @@ -343,12 +338,7 @@ void | at the location pointed to by 'zSPtr'. If either original floating-point | value is a signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNExtF80M( - const struct extFloat80M *aSPtr, - const struct extFloat80M *bSPtr, - struct extFloat80M *zSPtr - ); +void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 128-bit floating-point NaN. @@ -356,7 +346,7 @@ void #define defaultNaNF128UI96 0x7FFF8000 #define defaultNaNF128UI64 0 #define defaultNaNF128UI32 0 -#define defaultNaNF128UI0 0 +#define defaultNaNF128UI0 0 /*---------------------------------------------------------------------------- | Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN, @@ -366,7 +356,9 @@ void | four 32-bit elements that concatenate in the platform's normal endian order | to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -#define softfloat_f128MToCommonNaN( aWPtr, zPtr ) if ( ! ((aWPtr)[indexWordHi( 4 )] & UINT64_C( 0x0000800000000000 )) ) softfloat_raiseFlags( softfloat_flag_invalid ) +#define softfloat_f128MToCommonNaN(aWPtr, zPtr) \ + if(!((aWPtr)[indexWordHi(4)] & UINT64_C(0x0000800000000000))) \ + softfloat_raiseFlags(softfloat_flag_invalid) /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point @@ -374,19 +366,16 @@ void | 'zWPtr' points to an array of four 32-bit elements that concatenate in the | platform's normal endian order to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -#if defined INLINE && ! defined softfloat_commonNaNToF128M +#if defined INLINE && !defined softfloat_commonNaNToF128M INLINE -void - softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ) -{ - zWPtr[indexWord( 4, 3 )] = defaultNaNF128UI96; - zWPtr[indexWord( 4, 2 )] = defaultNaNF128UI64; - zWPtr[indexWord( 4, 1 )] = defaultNaNF128UI32; - zWPtr[indexWord( 4, 0 )] = defaultNaNF128UI0; +void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr) { + zWPtr[indexWord(4, 3)] = defaultNaNF128UI96; + zWPtr[indexWord(4, 2)] = defaultNaNF128UI64; + zWPtr[indexWord(4, 1)] = defaultNaNF128UI32; + zWPtr[indexWord(4, 0)] = defaultNaNF128UI0; } #else -void - softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ); +void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr); #endif /*---------------------------------------------------------------------------- @@ -397,11 +386,8 @@ void | and 'zWPtr' points to an array of four 32-bit elements that concatenate in | the platform's normal endian order to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNF128M( - const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr ); +void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr); #endif #endif - diff --git a/softfloat/source/ARM-VFPv2/specialize.h b/softfloat/source/ARM-VFPv2/specialize.h index 5321f33..638e690 100644 --- a/softfloat/source/ARM-VFPv2/specialize.h +++ b/softfloat/source/ARM-VFPv2/specialize.h @@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef specialize_h #define specialize_h 1 -#include -#include #include "primitiveTypes.h" #include "softfloat.h" +#include +#include /*---------------------------------------------------------------------------- | Default value for 'softfloat_detectTininess'. @@ -53,21 +53,21 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *----------------------------------------------------------------------------*/ #define ui32_fromPosOverflow 0xFFFFFFFF #define ui32_fromNegOverflow 0 -#define ui32_fromNaN 0 -#define i32_fromPosOverflow 0x7FFFFFFF -#define i32_fromNegOverflow (-0x7FFFFFFF - 1) -#define i32_fromNaN 0 +#define ui32_fromNaN 0 +#define i32_fromPosOverflow 0x7FFFFFFF +#define i32_fromNegOverflow (-0x7FFFFFFF - 1) +#define i32_fromNaN 0 /*---------------------------------------------------------------------------- | The values to return on conversions to 64-bit integer formats that raise an | invalid exception. *----------------------------------------------------------------------------*/ -#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF ) +#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF) #define ui64_fromNegOverflow 0 -#define ui64_fromNaN 0 -#define i64_fromPosOverflow INT64_C( 0x7FFFFFFFFFFFFFFF ) -#define i64_fromNegOverflow (-INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1) -#define i64_fromNaN 0 +#define ui64_fromNaN 0 +#define i64_fromPosOverflow INT64_C(0x7FFFFFFFFFFFFFFF) +#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1) +#define i64_fromNaN 0 /*---------------------------------------------------------------------------- | "Common NaN" structure, used to transfer NaN representations from one format @@ -92,7 +92,7 @@ struct commonNaN { | 16-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF)) +#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF)) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts @@ -100,13 +100,13 @@ struct commonNaN { | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr ); +void softfloat_f16UIToCommonNaN(uint_fast16_t uiA, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ); +uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- @@ -114,8 +114,7 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ); | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast16_t - softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB ); +uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 32-bit floating-point NaN. @@ -127,7 +126,7 @@ uint_fast16_t | 32-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF)) +#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF)) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts @@ -135,13 +134,13 @@ uint_fast16_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr ); +void softfloat_f32UIToCommonNaN(uint_fast32_t uiA, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ); +uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- @@ -149,20 +148,20 @@ uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ); | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast32_t - softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB ); +uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 64-bit floating-point NaN. *----------------------------------------------------------------------------*/ -#define defaultNaNF64UI UINT64_C( 0x7FF8000000000000 ) +#define defaultNaNF64UI UINT64_C(0x7FF8000000000000) /*---------------------------------------------------------------------------- | Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a | 64-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF ))) +#define softfloat_isSigNaNF64UI(uiA) \ + ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF))) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts @@ -170,13 +169,13 @@ uint_fast32_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr ); +void softfloat_f64UIToCommonNaN(uint_fast64_t uiA, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ); +uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- @@ -184,14 +183,13 @@ uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ); | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast64_t - softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ); +uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 80-bit extended floating-point NaN. *----------------------------------------------------------------------------*/ #define defaultNaNExtF80UI64 0x7FFF -#define defaultNaNExtF80UI0 UINT64_C( 0xC000000000000000 ) +#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000) /*---------------------------------------------------------------------------- | Returns true when the 80-bit unsigned integer formed from concatenating @@ -199,7 +197,8 @@ uint_fast64_t | floating-point signaling NaN. | Note: This macro evaluates its arguments more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF ))) +#define softfloat_isSigNaNExtF80UI(uiA64, uiA0) \ + ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF))) #ifdef SOFTFLOAT_FAST_INT64 @@ -215,16 +214,14 @@ uint_fast64_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_extF80UIToCommonNaN( - uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ); +void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended | floating-point NaN, and returns the bit pattern of this value as an unsigned | integer. *----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); +struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting the unsigned integer formed from concatenating 'uiA64' and @@ -235,19 +232,13 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); | result. If either original floating-point value is a signaling NaN, the | invalid exception is raised. *----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNExtF80UI( - uint_fast16_t uiA64, - uint_fast64_t uiA0, - uint_fast16_t uiB64, - uint_fast64_t uiB0 - ); +struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 128-bit floating-point NaN. *----------------------------------------------------------------------------*/ -#define defaultNaNF128UI64 UINT64_C( 0x7FFF800000000000 ) -#define defaultNaNF128UI0 UINT64_C( 0 ) +#define defaultNaNF128UI64 UINT64_C(0x7FFF800000000000) +#define defaultNaNF128UI0 UINT64_C(0) /*---------------------------------------------------------------------------- | Returns true when the 128-bit unsigned integer formed from concatenating @@ -255,7 +246,8 @@ struct uint128 | point signaling NaN. | Note: This macro evaluates its arguments more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF )))) +#define softfloat_isSigNaNF128UI(uiA64, uiA0) \ + ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF)))) /*---------------------------------------------------------------------------- | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' @@ -264,15 +256,13 @@ struct uint128 | pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid exception | is raised. *----------------------------------------------------------------------------*/ -void - softfloat_f128UIToCommonNaN( - uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ); +void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); +struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*); /*---------------------------------------------------------------------------- | Interpreting the unsigned integer formed from concatenating 'uiA64' and @@ -283,13 +273,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); | If either original floating-point value is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNF128UI( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0 - ); +struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0); #else @@ -304,18 +288,14 @@ struct uint128 | common NaN at the location pointed to by 'zPtr'. If the NaN is a signaling | NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_extF80MToCommonNaN( - const struct extFloat80M *aSPtr, struct commonNaN *zPtr ); +void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended | floating-point NaN, and stores this NaN at the location pointed to by | 'zSPtr'. *----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToExtF80M( - const struct commonNaN *aPtr, struct extFloat80M *zSPtr ); +void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr); /*---------------------------------------------------------------------------- | Assuming at least one of the two 80-bit extended floating-point values @@ -323,12 +303,7 @@ void | at the location pointed to by 'zSPtr'. If either original floating-point | value is a signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNExtF80M( - const struct extFloat80M *aSPtr, - const struct extFloat80M *bSPtr, - struct extFloat80M *zSPtr - ); +void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 128-bit floating-point NaN. @@ -336,7 +311,7 @@ void #define defaultNaNF128UI96 0x7FFF8000 #define defaultNaNF128UI64 0 #define defaultNaNF128UI32 0 -#define defaultNaNF128UI0 0 +#define defaultNaNF128UI0 0 /*---------------------------------------------------------------------------- | Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN, @@ -346,8 +321,7 @@ void | four 32-bit elements that concatenate in the platform's normal endian order | to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr ); +void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point @@ -355,8 +329,7 @@ void | 'zWPtr' points to an array of four 32-bit elements that concatenate in the | platform's normal endian order to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ); +void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr); /*---------------------------------------------------------------------------- | Assuming at least one of the two 128-bit floating-point values pointed to by @@ -366,11 +339,8 @@ void | and 'zWPtr' points to an array of four 32-bit elements that concatenate in | the platform's normal endian order to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNF128M( - const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr ); +void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr); #endif #endif - diff --git a/softfloat/source/RISCV/specialize.h b/softfloat/source/RISCV/specialize.h index 1cb9854..f0cb14c 100644 --- a/softfloat/source/RISCV/specialize.h +++ b/softfloat/source/RISCV/specialize.h @@ -37,10 +37,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef specialize_h #define specialize_h 1 -#include -#include #include "primitiveTypes.h" #include "softfloat.h" +#include +#include /*---------------------------------------------------------------------------- | Default value for 'softfloat_detectTininess'. @@ -53,21 +53,21 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *----------------------------------------------------------------------------*/ #define ui32_fromPosOverflow UINT32_C(0xFFFFFFFF) #define ui32_fromNegOverflow UINT32_C(0x0) -#define ui32_fromNaN UINT32_C(0xFFFFFFFF) -#define i32_fromPosOverflow INT64_C(0x7FFFFFFF) -#define i32_fromNegOverflow (-INT64_C(0x7FFFFFFF)-1) -#define i32_fromNaN INT64_C(0x7FFFFFFF) +#define ui32_fromNaN UINT32_C(0xFFFFFFFF) +#define i32_fromPosOverflow INT64_C(0x7FFFFFFF) +#define i32_fromNegOverflow (-INT64_C(0x7FFFFFFF) - 1) +#define i32_fromNaN INT64_C(0x7FFFFFFF) /*---------------------------------------------------------------------------- | The values to return on conversions to 64-bit integer formats that raise an | invalid exception. *----------------------------------------------------------------------------*/ -#define ui64_fromPosOverflow UINT64_C( 0xFFFFFFFFFFFFFFFF ) -#define ui64_fromNegOverflow UINT64_C( 0x0 ) -#define ui64_fromNaN UINT64_C( 0xFFFFFFFFFFFFFFFF) -#define i64_fromPosOverflow INT64_C( 0x7FFFFFFFFFFFFFFF) -#define i64_fromNegOverflow (-INT64_C( 0x7FFFFFFFFFFFFFFF)-1) -#define i64_fromNaN INT64_C( 0x7FFFFFFFFFFFFFFF) +#define ui64_fromPosOverflow UINT64_C(0xFFFFFFFFFFFFFFFF) +#define ui64_fromNegOverflow UINT64_C(0x0) +#define ui64_fromNaN UINT64_C(0xFFFFFFFFFFFFFFFF) +#define i64_fromPosOverflow INT64_C(0x7FFFFFFFFFFFFFFF) +#define i64_fromNegOverflow (-INT64_C(0x7FFFFFFFFFFFFFFF) - 1) +#define i64_fromNaN INT64_C(0x7FFFFFFFFFFFFFFF) /*---------------------------------------------------------------------------- | "Common NaN" structure, used to transfer NaN representations from one format @@ -92,7 +92,7 @@ struct commonNaN { | 16-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF16UI( uiA ) ((((uiA) & 0x7E00) == 0x7C00) && ((uiA) & 0x01FF)) +#define softfloat_isSigNaNF16UI(uiA) ((((uiA)&0x7E00) == 0x7C00) && ((uiA)&0x01FF)) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 16-bit floating-point NaN, converts @@ -100,13 +100,13 @@ struct commonNaN { | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void softfloat_f16UIToCommonNaN( uint_fast16_t uiA, struct commonNaN *zPtr ); +void softfloat_f16UIToCommonNaN(uint_fast16_t uiA, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 16-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ); +uint_fast16_t softfloat_commonNaNToF16UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 16-bit floating- @@ -114,8 +114,7 @@ uint_fast16_t softfloat_commonNaNToF16UI( const struct commonNaN *aPtr ); | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast16_t - softfloat_propagateNaNF16UI( uint_fast16_t uiA, uint_fast16_t uiB ); +uint_fast16_t softfloat_propagateNaNF16UI(uint_fast16_t uiA, uint_fast16_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 32-bit floating-point NaN. @@ -127,7 +126,7 @@ uint_fast16_t | 32-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF32UI( uiA ) ((((uiA) & 0x7FC00000) == 0x7F800000) && ((uiA) & 0x003FFFFF)) +#define softfloat_isSigNaNF32UI(uiA) ((((uiA)&0x7FC00000) == 0x7F800000) && ((uiA)&0x003FFFFF)) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 32-bit floating-point NaN, converts @@ -135,13 +134,13 @@ uint_fast16_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void softfloat_f32UIToCommonNaN( uint_fast32_t uiA, struct commonNaN *zPtr ); +void softfloat_f32UIToCommonNaN(uint_fast32_t uiA, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 32-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ); +uint_fast32_t softfloat_commonNaNToF32UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 32-bit floating- @@ -149,20 +148,20 @@ uint_fast32_t softfloat_commonNaNToF32UI( const struct commonNaN *aPtr ); | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast32_t - softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB ); +uint_fast32_t softfloat_propagateNaNF32UI(uint_fast32_t uiA, uint_fast32_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 64-bit floating-point NaN. *----------------------------------------------------------------------------*/ -#define defaultNaNF64UI UINT64_C( 0x7FF8000000000000 ) +#define defaultNaNF64UI UINT64_C(0x7FF8000000000000) /*---------------------------------------------------------------------------- | Returns true when 64-bit unsigned integer 'uiA' has the bit pattern of a | 64-bit floating-point signaling NaN. | Note: This macro evaluates its argument more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF64UI( uiA ) ((((uiA) & UINT64_C( 0x7FF8000000000000 )) == UINT64_C( 0x7FF0000000000000 )) && ((uiA) & UINT64_C( 0x0007FFFFFFFFFFFF ))) +#define softfloat_isSigNaNF64UI(uiA) \ + ((((uiA)&UINT64_C(0x7FF8000000000000)) == UINT64_C(0x7FF0000000000000)) && ((uiA)&UINT64_C(0x0007FFFFFFFFFFFF))) /*---------------------------------------------------------------------------- | Assuming 'uiA' has the bit pattern of a 64-bit floating-point NaN, converts @@ -170,13 +169,13 @@ uint_fast32_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void softfloat_f64UIToCommonNaN( uint_fast64_t uiA, struct commonNaN *zPtr ); +void softfloat_f64UIToCommonNaN(uint_fast64_t uiA, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 64-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ); +uint_fast64_t softfloat_commonNaNToF64UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting 'uiA' and 'uiB' as the bit patterns of two 64-bit floating- @@ -184,14 +183,13 @@ uint_fast64_t softfloat_commonNaNToF64UI( const struct commonNaN *aPtr ); | the combined NaN result. If either 'uiA' or 'uiB' has the pattern of a | signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -uint_fast64_t - softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB ); +uint_fast64_t softfloat_propagateNaNF64UI(uint_fast64_t uiA, uint_fast64_t uiB); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 80-bit extended floating-point NaN. *----------------------------------------------------------------------------*/ #define defaultNaNExtF80UI64 0xFFFF -#define defaultNaNExtF80UI0 UINT64_C( 0xC000000000000000 ) +#define defaultNaNExtF80UI0 UINT64_C(0xC000000000000000) /*---------------------------------------------------------------------------- | Returns true when the 80-bit unsigned integer formed from concatenating @@ -199,7 +197,8 @@ uint_fast64_t | floating-point signaling NaN. | Note: This macro evaluates its arguments more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNExtF80UI( uiA64, uiA0 ) ((((uiA64) & 0x7FFF) == 0x7FFF) && ! ((uiA0) & UINT64_C( 0x4000000000000000 )) && ((uiA0) & UINT64_C( 0x3FFFFFFFFFFFFFFF ))) +#define softfloat_isSigNaNExtF80UI(uiA64, uiA0) \ + ((((uiA64)&0x7FFF) == 0x7FFF) && !((uiA0)&UINT64_C(0x4000000000000000)) && ((uiA0)&UINT64_C(0x3FFFFFFFFFFFFFFF))) #ifdef SOFTFLOAT_FAST_INT64 @@ -215,16 +214,14 @@ uint_fast64_t | location pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_extF80UIToCommonNaN( - uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ); +void softfloat_extF80UIToCommonNaN(uint_fast16_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended | floating-point NaN, and returns the bit pattern of this value as an unsigned | integer. *----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); +struct uint128 softfloat_commonNaNToExtF80UI(const struct commonNaN* aPtr); /*---------------------------------------------------------------------------- | Interpreting the unsigned integer formed from concatenating 'uiA64' and @@ -235,19 +232,13 @@ struct uint128 softfloat_commonNaNToExtF80UI( const struct commonNaN *aPtr ); | result. If either original floating-point value is a signaling NaN, the | invalid exception is raised. *----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNExtF80UI( - uint_fast16_t uiA64, - uint_fast64_t uiA0, - uint_fast16_t uiB64, - uint_fast64_t uiB0 - ); +struct uint128 softfloat_propagateNaNExtF80UI(uint_fast16_t uiA64, uint_fast64_t uiA0, uint_fast16_t uiB64, uint_fast64_t uiB0); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 128-bit floating-point NaN. *----------------------------------------------------------------------------*/ -#define defaultNaNF128UI64 UINT64_C( 0xFFFF800000000000 ) -#define defaultNaNF128UI0 UINT64_C( 0 ) +#define defaultNaNF128UI64 UINT64_C(0xFFFF800000000000) +#define defaultNaNF128UI0 UINT64_C(0) /*---------------------------------------------------------------------------- | Returns true when the 128-bit unsigned integer formed from concatenating @@ -255,7 +246,8 @@ struct uint128 | point signaling NaN. | Note: This macro evaluates its arguments more than once. *----------------------------------------------------------------------------*/ -#define softfloat_isSigNaNF128UI( uiA64, uiA0 ) ((((uiA64) & UINT64_C( 0x7FFF800000000000 )) == UINT64_C( 0x7FFF000000000000 )) && ((uiA0) || ((uiA64) & UINT64_C( 0x00007FFFFFFFFFFF )))) +#define softfloat_isSigNaNF128UI(uiA64, uiA0) \ + ((((uiA64)&UINT64_C(0x7FFF800000000000)) == UINT64_C(0x7FFF000000000000)) && ((uiA0) || ((uiA64)&UINT64_C(0x00007FFFFFFFFFFF)))) /*---------------------------------------------------------------------------- | Assuming the unsigned integer formed from concatenating 'uiA64' and 'uiA0' @@ -264,15 +256,13 @@ struct uint128 | pointed to by 'zPtr'. If the NaN is a signaling NaN, the invalid exception | is raised. *----------------------------------------------------------------------------*/ -void - softfloat_f128UIToCommonNaN( - uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN *zPtr ); +void softfloat_f128UIToCommonNaN(uint_fast64_t uiA64, uint_fast64_t uiA0, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point | NaN, and returns the bit pattern of this value as an unsigned integer. *----------------------------------------------------------------------------*/ -struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); +struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN*); /*---------------------------------------------------------------------------- | Interpreting the unsigned integer formed from concatenating 'uiA64' and @@ -283,13 +273,7 @@ struct uint128 softfloat_commonNaNToF128UI( const struct commonNaN * ); | If either original floating-point value is a signaling NaN, the invalid | exception is raised. *----------------------------------------------------------------------------*/ -struct uint128 - softfloat_propagateNaNF128UI( - uint_fast64_t uiA64, - uint_fast64_t uiA0, - uint_fast64_t uiB64, - uint_fast64_t uiB0 - ); +struct uint128 softfloat_propagateNaNF128UI(uint_fast64_t uiA64, uint_fast64_t uiA0, uint_fast64_t uiB64, uint_fast64_t uiB0); #else @@ -304,18 +288,14 @@ struct uint128 | common NaN at the location pointed to by 'zPtr'. If the NaN is a signaling | NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_extF80MToCommonNaN( - const struct extFloat80M *aSPtr, struct commonNaN *zPtr ); +void softfloat_extF80MToCommonNaN(const struct extFloat80M* aSPtr, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into an 80-bit extended | floating-point NaN, and stores this NaN at the location pointed to by | 'zSPtr'. *----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToExtF80M( - const struct commonNaN *aPtr, struct extFloat80M *zSPtr ); +void softfloat_commonNaNToExtF80M(const struct commonNaN* aPtr, struct extFloat80M* zSPtr); /*---------------------------------------------------------------------------- | Assuming at least one of the two 80-bit extended floating-point values @@ -323,12 +303,7 @@ void | at the location pointed to by 'zSPtr'. If either original floating-point | value is a signaling NaN, the invalid exception is raised. *----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNExtF80M( - const struct extFloat80M *aSPtr, - const struct extFloat80M *bSPtr, - struct extFloat80M *zSPtr - ); +void softfloat_propagateNaNExtF80M(const struct extFloat80M* aSPtr, const struct extFloat80M* bSPtr, struct extFloat80M* zSPtr); /*---------------------------------------------------------------------------- | The bit pattern for a default generated 128-bit floating-point NaN. @@ -336,7 +311,7 @@ void #define defaultNaNF128UI96 0xFFFF8000 #define defaultNaNF128UI64 0 #define defaultNaNF128UI32 0 -#define defaultNaNF128UI0 0 +#define defaultNaNF128UI0 0 /*---------------------------------------------------------------------------- | Assuming the 128-bit floating-point value pointed to by 'aWPtr' is a NaN, @@ -346,8 +321,7 @@ void | four 32-bit elements that concatenate in the platform's normal endian order | to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_f128MToCommonNaN( const uint32_t *aWPtr, struct commonNaN *zPtr ); +void softfloat_f128MToCommonNaN(const uint32_t* aWPtr, struct commonNaN* zPtr); /*---------------------------------------------------------------------------- | Converts the common NaN pointed to by 'aPtr' into a 128-bit floating-point @@ -355,8 +329,7 @@ void | 'zWPtr' points to an array of four 32-bit elements that concatenate in the | platform's normal endian order to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_commonNaNToF128M( const struct commonNaN *aPtr, uint32_t *zWPtr ); +void softfloat_commonNaNToF128M(const struct commonNaN* aPtr, uint32_t* zWPtr); /*---------------------------------------------------------------------------- | Assuming at least one of the two 128-bit floating-point values pointed to by @@ -366,11 +339,8 @@ void | and 'zWPtr' points to an array of four 32-bit elements that concatenate in | the platform's normal endian order to form a 128-bit floating-point value. *----------------------------------------------------------------------------*/ -void - softfloat_propagateNaNF128M( - const uint32_t *aWPtr, const uint32_t *bWPtr, uint32_t *zWPtr ); +void softfloat_propagateNaNF128M(const uint32_t* aWPtr, const uint32_t* bWPtr, uint32_t* zWPtr); #endif #endif - diff --git a/softfloat/source/include/internals.h b/softfloat/source/include/internals.h index 020b340..bd976d1 100644 --- a/softfloat/source/include/internals.h +++ b/softfloat/source/include/internals.h @@ -37,242 +37,205 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef internals_h #define internals_h 1 -#include -#include #include "primitives.h" #include "softfloat_types.h" +#include +#include -union ui16_f16 { uint16_t ui; float16_t f; }; -union ui32_f32 { uint32_t ui; float32_t f; }; -union ui64_f64 { uint64_t ui; float64_t f; }; - -#ifdef SOFTFLOAT_FAST_INT64 -union extF80M_extF80 { struct extFloat80M fM; extFloat80_t f; }; -union ui128_f128 { struct uint128 ui; float128_t f; }; -#endif - -enum { - softfloat_mulAdd_subC = 1, - softfloat_mulAdd_subProd = 2 +union ui16_f16 { + uint16_t ui; + float16_t f; +}; +union ui32_f32 { + uint32_t ui; + float32_t f; +}; +union ui64_f64 { + uint64_t ui; + float64_t f; }; -/*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -uint_fast32_t softfloat_roundToUI32( bool, uint_fast64_t, uint_fast8_t, bool ); - #ifdef SOFTFLOAT_FAST_INT64 -uint_fast64_t - softfloat_roundToUI64( - bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool ); -#else -uint_fast64_t softfloat_roundMToUI64( bool, uint32_t *, uint_fast8_t, bool ); +union extF80M_extF80 { + struct extFloat80M fM; + extFloat80_t f; +}; +union ui128_f128 { + struct uint128 ui; + float128_t f; +}; #endif -int_fast32_t softfloat_roundToI32( bool, uint_fast64_t, uint_fast8_t, bool ); +enum { softfloat_mulAdd_subC = 1, softfloat_mulAdd_subProd = 2 }; + +/*---------------------------------------------------------------------------- + *----------------------------------------------------------------------------*/ +uint_fast32_t softfloat_roundToUI32(bool, uint_fast64_t, uint_fast8_t, bool); #ifdef SOFTFLOAT_FAST_INT64 -int_fast64_t - softfloat_roundToI64( - bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool ); +uint_fast64_t softfloat_roundToUI64(bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool); #else -int_fast64_t softfloat_roundMToI64( bool, uint32_t *, uint_fast8_t, bool ); +uint_fast64_t softfloat_roundMToUI64(bool, uint32_t*, uint_fast8_t, bool); +#endif + +int_fast32_t softfloat_roundToI32(bool, uint_fast64_t, uint_fast8_t, bool); + +#ifdef SOFTFLOAT_FAST_INT64 +int_fast64_t softfloat_roundToI64(bool, uint_fast64_t, uint_fast64_t, uint_fast8_t, bool); +#else +int_fast64_t softfloat_roundMToI64(bool, uint32_t*, uint_fast8_t, bool); #endif /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define signF16UI( a ) ((bool) ((uint16_t) (a)>>15)) -#define expF16UI( a ) ((int_fast8_t) ((a)>>10) & 0x1F) -#define fracF16UI( a ) ((a) & 0x03FF) -#define packToF16UI( sign, exp, sig ) (((uint16_t) (sign)<<15) + ((uint16_t) (exp)<<10) + (sig)) + *----------------------------------------------------------------------------*/ +#define signF16UI(a) ((bool)((uint16_t)(a) >> 15)) +#define expF16UI(a) ((int_fast8_t)((a) >> 10) & 0x1F) +#define fracF16UI(a) ((a)&0x03FF) +#define packToF16UI(sign, exp, sig) (((uint16_t)(sign) << 15) + ((uint16_t)(exp) << 10) + (sig)) -#define isNaNF16UI( a ) (((~(a) & 0x7C00) == 0) && ((a) & 0x03FF)) +#define isNaNF16UI(a) (((~(a)&0x7C00) == 0) && ((a)&0x03FF)) -struct exp8_sig16 { int_fast8_t exp; uint_fast16_t sig; }; -struct exp8_sig16 softfloat_normSubnormalF16Sig( uint_fast16_t ); +struct exp8_sig16 { + int_fast8_t exp; + uint_fast16_t sig; +}; +struct exp8_sig16 softfloat_normSubnormalF16Sig(uint_fast16_t); -float16_t softfloat_roundPackToF16( bool, int_fast16_t, uint_fast16_t ); -float16_t softfloat_normRoundPackToF16( bool, int_fast16_t, uint_fast16_t ); +float16_t softfloat_roundPackToF16(bool, int_fast16_t, uint_fast16_t); +float16_t softfloat_normRoundPackToF16(bool, int_fast16_t, uint_fast16_t); -float16_t softfloat_addMagsF16( uint_fast16_t, uint_fast16_t ); -float16_t softfloat_subMagsF16( uint_fast16_t, uint_fast16_t ); -float16_t - softfloat_mulAddF16( - uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t ); +float16_t softfloat_addMagsF16(uint_fast16_t, uint_fast16_t); +float16_t softfloat_subMagsF16(uint_fast16_t, uint_fast16_t); +float16_t softfloat_mulAddF16(uint_fast16_t, uint_fast16_t, uint_fast16_t, uint_fast8_t); /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define signF32UI( a ) ((bool) ((uint32_t) (a)>>31)) -#define expF32UI( a ) ((int_fast16_t) ((a)>>23) & 0xFF) -#define fracF32UI( a ) ((a) & 0x007FFFFF) -#define packToF32UI( sign, exp, sig ) (((uint32_t) (sign)<<31) + ((uint32_t) (exp)<<23) + (sig)) + *----------------------------------------------------------------------------*/ +#define signF32UI(a) ((bool)((uint32_t)(a) >> 31)) +#define expF32UI(a) ((int_fast16_t)((a) >> 23) & 0xFF) +#define fracF32UI(a) ((a)&0x007FFFFF) +#define packToF32UI(sign, exp, sig) (((uint32_t)(sign) << 31) + ((uint32_t)(exp) << 23) + (sig)) -#define isNaNF32UI( a ) (((~(a) & 0x7F800000) == 0) && ((a) & 0x007FFFFF)) +#define isNaNF32UI(a) (((~(a)&0x7F800000) == 0) && ((a)&0x007FFFFF)) -struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; }; -struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t ); +struct exp16_sig32 { + int_fast16_t exp; + uint_fast32_t sig; +}; +struct exp16_sig32 softfloat_normSubnormalF32Sig(uint_fast32_t); -float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t ); -float32_t softfloat_normRoundPackToF32( bool, int_fast16_t, uint_fast32_t ); +float32_t softfloat_roundPackToF32(bool, int_fast16_t, uint_fast32_t); +float32_t softfloat_normRoundPackToF32(bool, int_fast16_t, uint_fast32_t); -float32_t softfloat_addMagsF32( uint_fast32_t, uint_fast32_t ); -float32_t softfloat_subMagsF32( uint_fast32_t, uint_fast32_t ); -float32_t - softfloat_mulAddF32( - uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t ); +float32_t softfloat_addMagsF32(uint_fast32_t, uint_fast32_t); +float32_t softfloat_subMagsF32(uint_fast32_t, uint_fast32_t); +float32_t softfloat_mulAddF32(uint_fast32_t, uint_fast32_t, uint_fast32_t, uint_fast8_t); /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define signF64UI( a ) ((bool) ((uint64_t) (a)>>63)) -#define expF64UI( a ) ((int_fast16_t) ((a)>>52) & 0x7FF) -#define fracF64UI( a ) ((a) & UINT64_C( 0x000FFFFFFFFFFFFF )) -#define packToF64UI( sign, exp, sig ) ((uint64_t) (((uint_fast64_t) (sign)<<63) + ((uint_fast64_t) (exp)<<52) + (sig))) + *----------------------------------------------------------------------------*/ +#define signF64UI(a) ((bool)((uint64_t)(a) >> 63)) +#define expF64UI(a) ((int_fast16_t)((a) >> 52) & 0x7FF) +#define fracF64UI(a) ((a)&UINT64_C(0x000FFFFFFFFFFFFF)) +#define packToF64UI(sign, exp, sig) ((uint64_t)(((uint_fast64_t)(sign) << 63) + ((uint_fast64_t)(exp) << 52) + (sig))) -#define isNaNF64UI( a ) (((~(a) & UINT64_C( 0x7FF0000000000000 )) == 0) && ((a) & UINT64_C( 0x000FFFFFFFFFFFFF ))) +#define isNaNF64UI(a) (((~(a)&UINT64_C(0x7FF0000000000000)) == 0) && ((a)&UINT64_C(0x000FFFFFFFFFFFFF))) -struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; }; -struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t ); +struct exp16_sig64 { + int_fast16_t exp; + uint_fast64_t sig; +}; +struct exp16_sig64 softfloat_normSubnormalF64Sig(uint_fast64_t); -float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t ); -float64_t softfloat_normRoundPackToF64( bool, int_fast16_t, uint_fast64_t ); +float64_t softfloat_roundPackToF64(bool, int_fast16_t, uint_fast64_t); +float64_t softfloat_normRoundPackToF64(bool, int_fast16_t, uint_fast64_t); -float64_t softfloat_addMagsF64( uint_fast64_t, uint_fast64_t, bool ); -float64_t softfloat_subMagsF64( uint_fast64_t, uint_fast64_t, bool ); -float64_t - softfloat_mulAddF64( - uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t ); +float64_t softfloat_addMagsF64(uint_fast64_t, uint_fast64_t, bool); +float64_t softfloat_subMagsF64(uint_fast64_t, uint_fast64_t, bool); +float64_t softfloat_mulAddF64(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t); /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define signExtF80UI64( a64 ) ((bool) ((uint16_t) (a64)>>15)) -#define expExtF80UI64( a64 ) ((a64) & 0x7FFF) -#define packToExtF80UI64( sign, exp ) ((uint_fast16_t) (sign)<<15 | (exp)) + *----------------------------------------------------------------------------*/ +#define signExtF80UI64(a64) ((bool)((uint16_t)(a64) >> 15)) +#define expExtF80UI64(a64) ((a64)&0x7FFF) +#define packToExtF80UI64(sign, exp) ((uint_fast16_t)(sign) << 15 | (exp)) -#define isNaNExtF80UI( a64, a0 ) ((((a64) & 0x7FFF) == 0x7FFF) && ((a0) & UINT64_C( 0x7FFFFFFFFFFFFFFF ))) +#define isNaNExtF80UI(a64, a0) ((((a64)&0x7FFF) == 0x7FFF) && ((a0)&UINT64_C(0x7FFFFFFFFFFFFFFF))) #ifdef SOFTFLOAT_FAST_INT64 /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ -struct exp32_sig64 { int_fast32_t exp; uint64_t sig; }; -struct exp32_sig64 softfloat_normSubnormalExtF80Sig( uint_fast64_t ); +struct exp32_sig64 { + int_fast32_t exp; + uint64_t sig; +}; +struct exp32_sig64 softfloat_normSubnormalExtF80Sig(uint_fast64_t); -extFloat80_t - softfloat_roundPackToExtF80( - bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t ); -extFloat80_t - softfloat_normRoundPackToExtF80( - bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t ); +extFloat80_t softfloat_roundPackToExtF80(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t); +extFloat80_t softfloat_normRoundPackToExtF80(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast8_t); -extFloat80_t - softfloat_addMagsExtF80( - uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool ); -extFloat80_t - softfloat_subMagsExtF80( - uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool ); +extFloat80_t softfloat_addMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool); +extFloat80_t softfloat_subMagsExtF80(uint_fast16_t, uint_fast64_t, uint_fast16_t, uint_fast64_t, bool); /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define signF128UI64( a64 ) ((bool) ((uint64_t) (a64)>>63)) -#define expF128UI64( a64 ) ((int_fast32_t) ((a64)>>48) & 0x7FFF) -#define fracF128UI64( a64 ) ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF )) -#define packToF128UI64( sign, exp, sig64 ) (((uint_fast64_t) (sign)<<63) + ((uint_fast64_t) (exp)<<48) + (sig64)) + *----------------------------------------------------------------------------*/ +#define signF128UI64(a64) ((bool)((uint64_t)(a64) >> 63)) +#define expF128UI64(a64) ((int_fast32_t)((a64) >> 48) & 0x7FFF) +#define fracF128UI64(a64) ((a64)&UINT64_C(0x0000FFFFFFFFFFFF)) +#define packToF128UI64(sign, exp, sig64) (((uint_fast64_t)(sign) << 63) + ((uint_fast64_t)(exp) << 48) + (sig64)) -#define isNaNF128UI( a64, a0 ) (((~(a64) & UINT64_C( 0x7FFF000000000000 )) == 0) && (a0 || ((a64) & UINT64_C( 0x0000FFFFFFFFFFFF )))) +#define isNaNF128UI(a64, a0) (((~(a64)&UINT64_C(0x7FFF000000000000)) == 0) && (a0 || ((a64)&UINT64_C(0x0000FFFFFFFFFFFF)))) -struct exp32_sig128 { int_fast32_t exp; struct uint128 sig; }; -struct exp32_sig128 - softfloat_normSubnormalF128Sig( uint_fast64_t, uint_fast64_t ); +struct exp32_sig128 { + int_fast32_t exp; + struct uint128 sig; +}; +struct exp32_sig128 softfloat_normSubnormalF128Sig(uint_fast64_t, uint_fast64_t); -float128_t - softfloat_roundPackToF128( - bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t ); -float128_t - softfloat_normRoundPackToF128( - bool, int_fast32_t, uint_fast64_t, uint_fast64_t ); +float128_t softfloat_roundPackToF128(bool, int_fast32_t, uint_fast64_t, uint_fast64_t, uint_fast64_t); +float128_t softfloat_normRoundPackToF128(bool, int_fast32_t, uint_fast64_t, uint_fast64_t); -float128_t - softfloat_addMagsF128( - uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool ); -float128_t - softfloat_subMagsF128( - uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool ); -float128_t - softfloat_mulAddF128( - uint_fast64_t, - uint_fast64_t, - uint_fast64_t, - uint_fast64_t, - uint_fast64_t, - uint_fast64_t, - uint_fast8_t - ); +float128_t softfloat_addMagsF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool); +float128_t softfloat_subMagsF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, bool); +float128_t softfloat_mulAddF128(uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast64_t, uint_fast8_t); #else /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ + *----------------------------------------------------------------------------*/ -bool - softfloat_tryPropagateNaNExtF80M( - const struct extFloat80M *, - const struct extFloat80M *, - struct extFloat80M * - ); -void softfloat_invalidExtF80M( struct extFloat80M * ); +bool softfloat_tryPropagateNaNExtF80M(const struct extFloat80M*, const struct extFloat80M*, struct extFloat80M*); +void softfloat_invalidExtF80M(struct extFloat80M*); -int softfloat_normExtF80SigM( uint64_t * ); +int softfloat_normExtF80SigM(uint64_t*); -void - softfloat_roundPackMToExtF80M( - bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * ); -void - softfloat_normRoundPackMToExtF80M( - bool, int32_t, uint32_t *, uint_fast8_t, struct extFloat80M * ); +void softfloat_roundPackMToExtF80M(bool, int32_t, uint32_t*, uint_fast8_t, struct extFloat80M*); +void softfloat_normRoundPackMToExtF80M(bool, int32_t, uint32_t*, uint_fast8_t, struct extFloat80M*); -void - softfloat_addExtF80M( - const struct extFloat80M *, - const struct extFloat80M *, - struct extFloat80M *, - bool - ); +void softfloat_addExtF80M(const struct extFloat80M*, const struct extFloat80M*, struct extFloat80M*, bool); -int - softfloat_compareNonnormExtF80M( - const struct extFloat80M *, const struct extFloat80M * ); +int softfloat_compareNonnormExtF80M(const struct extFloat80M*, const struct extFloat80M*); /*---------------------------------------------------------------------------- -*----------------------------------------------------------------------------*/ -#define signF128UI96( a96 ) ((bool) ((uint32_t) (a96)>>31)) -#define expF128UI96( a96 ) ((int32_t) ((a96)>>16) & 0x7FFF) -#define fracF128UI96( a96 ) ((a96) & 0x0000FFFF) -#define packToF128UI96( sign, exp, sig96 ) (((uint32_t) (sign)<<31) + ((uint32_t) (exp)<<16) + (sig96)) + *----------------------------------------------------------------------------*/ +#define signF128UI96(a96) ((bool)((uint32_t)(a96) >> 31)) +#define expF128UI96(a96) ((int32_t)((a96) >> 16) & 0x7FFF) +#define fracF128UI96(a96) ((a96)&0x0000FFFF) +#define packToF128UI96(sign, exp, sig96) (((uint32_t)(sign) << 31) + ((uint32_t)(exp) << 16) + (sig96)) -bool softfloat_isNaNF128M( const uint32_t * ); +bool softfloat_isNaNF128M(const uint32_t*); -bool - softfloat_tryPropagateNaNF128M( - const uint32_t *, const uint32_t *, uint32_t * ); -void softfloat_invalidF128M( uint32_t * ); +bool softfloat_tryPropagateNaNF128M(const uint32_t*, const uint32_t*, uint32_t*); +void softfloat_invalidF128M(uint32_t*); -int softfloat_shiftNormSigF128M( const uint32_t *, uint_fast8_t, uint32_t * ); +int softfloat_shiftNormSigF128M(const uint32_t*, uint_fast8_t, uint32_t*); -void softfloat_roundPackMToF128M( bool, int32_t, uint32_t *, uint32_t * ); -void softfloat_normRoundPackMToF128M( bool, int32_t, uint32_t *, uint32_t * ); +void softfloat_roundPackMToF128M(bool, int32_t, uint32_t*, uint32_t*); +void softfloat_normRoundPackMToF128M(bool, int32_t, uint32_t*, uint32_t*); -void - softfloat_addF128M( const uint32_t *, const uint32_t *, uint32_t *, bool ); -void - softfloat_mulAddF128M( - const uint32_t *, - const uint32_t *, - const uint32_t *, - uint32_t *, - uint_fast8_t - ); +void softfloat_addF128M(const uint32_t*, const uint32_t*, uint32_t*, bool); +void softfloat_mulAddF128M(const uint32_t*, const uint32_t*, const uint32_t*, uint32_t*, uint_fast8_t); #endif #endif - diff --git a/softfloat/source/include/opts-GCC.h b/softfloat/source/include/opts-GCC.h index 18c1523..99a4127 100644 --- a/softfloat/source/include/opts-GCC.h +++ b/softfloat/source/include/opts-GCC.h @@ -39,70 +39,70 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifdef INLINE -#include #include "primitiveTypes.h" +#include #ifdef SOFTFLOAT_BUILTIN_CLZ -INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a ) - { return a ? __builtin_clz( a ) - 16 : 16; } +INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) { return a ? __builtin_clz(a) - 16 : 16; } #define softfloat_countLeadingZeros16 softfloat_countLeadingZeros16 -INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a ) - { return a ? __builtin_clz( a ) : 32; } +INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) { return a ? __builtin_clz(a) : 32; } #define softfloat_countLeadingZeros32 softfloat_countLeadingZeros32 -INLINE uint_fast8_t softfloat_countLeadingZeros64( uint64_t a ) - { return a ? __builtin_clzll( a ) : 64; } +INLINE uint_fast8_t softfloat_countLeadingZeros64(uint64_t a) { return a ? __builtin_clzll(a) : 64; } #define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64 #endif #ifdef SOFTFLOAT_INTRINSIC_INT128 -INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b ) -{ - union { unsigned __int128 ui; struct uint128 s; } uZ; - uZ.ui = (unsigned __int128) a * ((uint_fast64_t) b<<32); +INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) { + union { + unsigned __int128 ui; + struct uint128 s; + } uZ; + uZ.ui = (unsigned __int128)a * ((uint_fast64_t)b << 32); return uZ.s; } #define softfloat_mul64ByShifted32To128 softfloat_mul64ByShifted32To128 -INLINE struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b ) -{ - union { unsigned __int128 ui; struct uint128 s; } uZ; - uZ.ui = (unsigned __int128) a * b; +INLINE struct uint128 softfloat_mul64To128(uint64_t a, uint64_t b) { + union { + unsigned __int128 ui; + struct uint128 s; + } uZ; + uZ.ui = (unsigned __int128)a * b; return uZ.s; } #define softfloat_mul64To128 softfloat_mul64To128 INLINE -struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b ) -{ - union { unsigned __int128 ui; struct uint128 s; } uZ; - uZ.ui = ((unsigned __int128) a64<<64 | a0) * b; +struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) { + union { + unsigned __int128 ui; + struct uint128 s; + } uZ; + uZ.ui = ((unsigned __int128)a64 << 64 | a0) * b; return uZ.s; } #define softfloat_mul128By32 softfloat_mul128By32 INLINE -void - softfloat_mul128To256M( - uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr ) -{ +void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr) { unsigned __int128 z0, mid1, mid, z128; - z0 = (unsigned __int128) a0 * b0; - mid1 = (unsigned __int128) a64 * b0; - mid = mid1 + (unsigned __int128) a0 * b64; - z128 = (unsigned __int128) a64 * b64; - z128 += (unsigned __int128) (mid < mid1)<<64 | mid>>64; + z0 = (unsigned __int128)a0 * b0; + mid1 = (unsigned __int128)a64 * b0; + mid = mid1 + (unsigned __int128)a0 * b64; + z128 = (unsigned __int128)a64 * b64; + z128 += (unsigned __int128)(mid < mid1) << 64 | mid >> 64; mid <<= 64; z0 += mid; z128 += (z0 < mid); - zPtr[indexWord( 4, 0 )] = z0; - zPtr[indexWord( 4, 1 )] = z0>>64; - zPtr[indexWord( 4, 2 )] = z128; - zPtr[indexWord( 4, 3 )] = z128>>64; + zPtr[indexWord(4, 0)] = z0; + zPtr[indexWord(4, 1)] = z0 >> 64; + zPtr[indexWord(4, 2)] = z128; + zPtr[indexWord(4, 3)] = z128 >> 64; } #define softfloat_mul128To256M softfloat_mul128To256M @@ -111,4 +111,3 @@ void #endif #endif - diff --git a/softfloat/source/include/primitiveTypes.h b/softfloat/source/include/primitiveTypes.h index a4a6dd1..fca21f9 100644 --- a/softfloat/source/include/primitiveTypes.h +++ b/softfloat/source/include/primitiveTypes.h @@ -42,13 +42,27 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifdef SOFTFLOAT_FAST_INT64 #ifdef LITTLEENDIAN -struct uint128 { uint64_t v0, v64; }; -struct uint64_extra { uint64_t extra, v; }; -struct uint128_extra { uint64_t extra; struct uint128 v; }; +struct uint128 { + uint64_t v0, v64; +}; +struct uint64_extra { + uint64_t extra, v; +}; +struct uint128_extra { + uint64_t extra; + struct uint128 v; +}; #else -struct uint128 { uint64_t v64, v0; }; -struct uint64_extra { uint64_t v, extra; }; -struct uint128_extra { struct uint128 v; uint64_t extra; }; +struct uint128 { + uint64_t v64, v0; +}; +struct uint64_extra { + uint64_t v, extra; +}; +struct uint128_extra { + struct uint128 v; + uint64_t extra; +}; #endif #endif @@ -59,27 +73,28 @@ struct uint128_extra { struct uint128 v; uint64_t extra; }; *----------------------------------------------------------------------------*/ #ifdef LITTLEENDIAN #define wordIncr 1 -#define indexWord( total, n ) (n) -#define indexWordHi( total ) ((total) - 1) -#define indexWordLo( total ) 0 -#define indexMultiword( total, m, n ) (n) -#define indexMultiwordHi( total, n ) ((total) - (n)) -#define indexMultiwordLo( total, n ) 0 -#define indexMultiwordHiBut( total, n ) (n) -#define indexMultiwordLoBut( total, n ) 0 -#define INIT_UINTM4( v3, v2, v1, v0 ) { v0, v1, v2, v3 } +#define indexWord(total, n) (n) +#define indexWordHi(total) ((total)-1) +#define indexWordLo(total) 0 +#define indexMultiword(total, m, n) (n) +#define indexMultiwordHi(total, n) ((total) - (n)) +#define indexMultiwordLo(total, n) 0 +#define indexMultiwordHiBut(total, n) (n) +#define indexMultiwordLoBut(total, n) 0 +#define INIT_UINTM4(v3, v2, v1, v0) \ + { v0, v1, v2, v3 } #else #define wordIncr -1 -#define indexWord( total, n ) ((total) - 1 - (n)) -#define indexWordHi( total ) 0 -#define indexWordLo( total ) ((total) - 1) -#define indexMultiword( total, m, n ) ((total) - 1 - (m)) -#define indexMultiwordHi( total, n ) 0 -#define indexMultiwordLo( total, n ) ((total) - (n)) -#define indexMultiwordHiBut( total, n ) 0 -#define indexMultiwordLoBut( total, n ) (n) -#define INIT_UINTM4( v3, v2, v1, v0 ) { v3, v2, v1, v0 } +#define indexWord(total, n) ((total)-1 - (n)) +#define indexWordHi(total) 0 +#define indexWordLo(total) ((total)-1) +#define indexMultiword(total, m, n) ((total)-1 - (m)) +#define indexMultiwordHi(total, n) 0 +#define indexMultiwordLo(total, n) ((total) - (n)) +#define indexMultiwordHiBut(total, n) 0 +#define indexMultiwordLoBut(total, n) (n) +#define INIT_UINTM4(v3, v2, v1, v0) \ + { v3, v2, v1, v0 } #endif #endif - diff --git a/softfloat/source/include/primitives.h b/softfloat/source/include/primitives.h index 863ab45..11967d2 100644 --- a/softfloat/source/include/primitives.h +++ b/softfloat/source/include/primitives.h @@ -37,9 +37,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef primitives_h #define primitives_h 1 +#include "primitiveTypes.h" #include #include -#include "primitiveTypes.h" #ifndef softfloat_shortShiftRightJam64 /*---------------------------------------------------------------------------- @@ -50,10 +50,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) INLINE -uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist ) - { return a>>dist | ((a & (((uint_fast64_t) 1<> dist | ((a & (((uint_fast64_t)1 << dist) - 1)) != 0); } #else -uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist ); +uint64_t softfloat_shortShiftRightJam64(uint64_t a, uint_fast8_t dist); #endif #endif @@ -68,13 +67,11 @@ uint64_t softfloat_shortShiftRightJam64( uint64_t a, uint_fast8_t dist ); | is zero or nonzero. *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist ) -{ - return - (dist < 31) ? a>>dist | ((uint32_t) (a<<(-dist & 31)) != 0) : (a != 0); +INLINE uint32_t softfloat_shiftRightJam32(uint32_t a, uint_fast16_t dist) { + return (dist < 31) ? a >> dist | ((uint32_t)(a << (-dist & 31)) != 0) : (a != 0); } #else -uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist ); +uint32_t softfloat_shiftRightJam32(uint32_t a, uint_fast16_t dist); #endif #endif @@ -89,13 +86,11 @@ uint32_t softfloat_shiftRightJam32( uint32_t a, uint_fast16_t dist ); | is zero or nonzero. *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) -INLINE uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist ) -{ - return - (dist < 63) ? a>>dist | ((uint64_t) (a<<(-dist & 63)) != 0) : (a != 0); +INLINE uint64_t softfloat_shiftRightJam64(uint64_t a, uint_fast32_t dist) { + return (dist < 63) ? a >> dist | ((uint64_t)(a << (-dist & 63)) != 0) : (a != 0); } #else -uint64_t softfloat_shiftRightJam64( uint64_t a, uint_fast32_t dist ); +uint64_t softfloat_shiftRightJam64(uint64_t a, uint_fast32_t dist); #endif #endif @@ -112,10 +107,9 @@ extern const uint_least8_t softfloat_countLeadingZeros8[256]; | 'a'. If 'a' is zero, 16 is returned. *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) -INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a ) -{ +INLINE uint_fast8_t softfloat_countLeadingZeros16(uint16_t a) { uint_fast8_t count = 8; - if ( 0x100 <= a ) { + if(0x100 <= a) { count = 0; a >>= 8; } @@ -123,7 +117,7 @@ INLINE uint_fast8_t softfloat_countLeadingZeros16( uint16_t a ) return count; } #else -uint_fast8_t softfloat_countLeadingZeros16( uint16_t a ); +uint_fast8_t softfloat_countLeadingZeros16(uint16_t a); #endif #endif @@ -133,22 +127,21 @@ uint_fast8_t softfloat_countLeadingZeros16( uint16_t a ); | 'a'. If 'a' is zero, 32 is returned. *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) -INLINE uint_fast8_t softfloat_countLeadingZeros32( uint32_t a ) -{ +INLINE uint_fast8_t softfloat_countLeadingZeros32(uint32_t a) { uint_fast8_t count = 0; - if ( a < 0x10000 ) { + if(a < 0x10000) { count = 16; a <<= 16; } - if ( a < 0x1000000 ) { + if(a < 0x1000000) { count += 8; a <<= 8; } - count += softfloat_countLeadingZeros8[a>>24]; + count += softfloat_countLeadingZeros8[a >> 24]; return count; } #else -uint_fast8_t softfloat_countLeadingZeros32( uint32_t a ); +uint_fast8_t softfloat_countLeadingZeros32(uint32_t a); #endif #endif @@ -157,7 +150,7 @@ uint_fast8_t softfloat_countLeadingZeros32( uint32_t a ); | Returns the number of leading 0 bits before the most-significant 1 bit of | 'a'. If 'a' is zero, 64 is returned. *----------------------------------------------------------------------------*/ -uint_fast8_t softfloat_countLeadingZeros64( uint64_t a ); +uint_fast8_t softfloat_countLeadingZeros64(uint64_t a); #endif extern const uint16_t softfloat_approxRecip_1k0s[16]; @@ -176,9 +169,9 @@ extern const uint16_t softfloat_approxRecip_1k1s[16]; | (units in the last place). *----------------------------------------------------------------------------*/ #ifdef SOFTFLOAT_FAST_DIV64TO32 -#define softfloat_approxRecip32_1( a ) ((uint32_t) (UINT64_C( 0x7FFFFFFFFFFFFFFF ) / (uint32_t) (a))) +#define softfloat_approxRecip32_1(a) ((uint32_t)(UINT64_C(0x7FFFFFFFFFFFFFFF) / (uint32_t)(a))) #else -uint32_t softfloat_approxRecip32_1( uint32_t a ); +uint32_t softfloat_approxRecip32_1(uint32_t a); #endif #endif @@ -204,7 +197,7 @@ extern const uint16_t softfloat_approxRecipSqrt_1k1s[16]; | returned is also always within the range 0.5 to 1; thus, the most- | significant bit of the result is always set. *----------------------------------------------------------------------------*/ -uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a ); +uint32_t softfloat_approxRecipSqrt32_1(unsigned int oddExpA, uint32_t a); #endif #ifdef SOFTFLOAT_FAST_INT64 @@ -222,10 +215,9 @@ uint32_t softfloat_approxRecipSqrt32_1( unsigned int oddExpA, uint32_t a ); *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (1 <= INLINE_LEVEL) INLINE -bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) - { return (a64 == b64) && (a0 == b0); } +bool softfloat_eq128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 == b64) && (a0 == b0); } #else -bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); +bool softfloat_eq128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0); #endif #endif @@ -237,10 +229,9 @@ bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) INLINE -bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) - { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); } +bool softfloat_le128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 < b64) || ((a64 == b64) && (a0 <= b0)); } #else -bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); +bool softfloat_le128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0); #endif #endif @@ -252,10 +243,9 @@ bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) INLINE -bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) - { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); } +bool softfloat_lt128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { return (a64 < b64) || ((a64 == b64) && (a0 < b0)); } #else -bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); +bool softfloat_lt128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0); #endif #endif @@ -266,17 +256,14 @@ bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) INLINE -struct uint128 - softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist ) -{ +struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8_t dist) { struct uint128 z; - z.v64 = a64<>(-dist & 63); - z.v0 = a0<> (-dist & 63); + z.v0 = a0 << dist; return z; } #else -struct uint128 - softfloat_shortShiftLeft128( uint64_t a64, uint64_t a0, uint_fast8_t dist ); +struct uint128 softfloat_shortShiftLeft128(uint64_t a64, uint64_t a0, uint_fast8_t dist); #endif #endif @@ -287,17 +274,14 @@ struct uint128 *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) INLINE -struct uint128 - softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist ) -{ +struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast8_t dist) { struct uint128 z; - z.v64 = a64>>dist; - z.v0 = a64<<(-dist & 63) | a0>>dist; + z.v64 = a64 >> dist; + z.v0 = a64 << (-dist & 63) | a0 >> dist; return z; } #else -struct uint128 - softfloat_shortShiftRight128( uint64_t a64, uint64_t a0, uint_fast8_t dist ); +struct uint128 softfloat_shortShiftRight128(uint64_t a64, uint64_t a0, uint_fast8_t dist); #endif #endif @@ -308,19 +292,14 @@ struct uint128 *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) INLINE -struct uint64_extra - softfloat_shortShiftRightJam64Extra( - uint64_t a, uint64_t extra, uint_fast8_t dist ) -{ +struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast8_t dist) { struct uint64_extra z; - z.v = a>>dist; - z.extra = a<<(-dist & 63) | (extra != 0); + z.v = a >> dist; + z.extra = a << (-dist & 63) | (extra != 0); return z; } #else -struct uint64_extra - softfloat_shortShiftRightJam64Extra( - uint64_t a, uint64_t extra, uint_fast8_t dist ); +struct uint64_extra softfloat_shortShiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast8_t dist); #endif #endif @@ -334,22 +313,15 @@ struct uint64_extra *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) INLINE -struct uint128 - softfloat_shortShiftRightJam128( - uint64_t a64, uint64_t a0, uint_fast8_t dist ) -{ +struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_fast8_t dist) { uint_fast8_t negDist = -dist; struct uint128 z; - z.v64 = a64>>dist; - z.v0 = - a64<<(negDist & 63) | a0>>dist - | ((uint64_t) (a0<<(negDist & 63)) != 0); + z.v64 = a64 >> dist; + z.v0 = a64 << (negDist & 63) | a0 >> dist | ((uint64_t)(a0 << (negDist & 63)) != 0); return z; } #else -struct uint128 - softfloat_shortShiftRightJam128( - uint64_t a64, uint64_t a0, uint_fast8_t dist ); +struct uint128 softfloat_shortShiftRightJam128(uint64_t a64, uint64_t a0, uint_fast8_t dist); #endif #endif @@ -360,21 +332,16 @@ struct uint128 *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) INLINE -struct uint128_extra - softfloat_shortShiftRightJam128Extra( - uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist ) -{ +struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist) { uint_fast8_t negDist = -dist; struct uint128_extra z; - z.v.v64 = a64>>dist; - z.v.v0 = a64<<(negDist & 63) | a0>>dist; - z.extra = a0<<(negDist & 63) | (extra != 0); + z.v.v64 = a64 >> dist; + z.v.v0 = a64 << (negDist & 63) | a0 >> dist; + z.extra = a0 << (negDist & 63) | (extra != 0); return z; } #else -struct uint128_extra - softfloat_shortShiftRightJam128Extra( - uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist ); +struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast8_t dist); #endif #endif @@ -397,14 +364,11 @@ struct uint128_extra *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (4 <= INLINE_LEVEL) INLINE -struct uint64_extra - softfloat_shiftRightJam64Extra( - uint64_t a, uint64_t extra, uint_fast32_t dist ) -{ +struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast32_t dist) { struct uint64_extra z; - if ( dist < 64 ) { - z.v = a>>dist; - z.extra = a<<(-dist & 63); + if(dist < 64) { + z.v = a >> dist; + z.extra = a << (-dist & 63); } else { z.v = 0; z.extra = (dist == 64) ? a : (a != 0); @@ -413,9 +377,7 @@ struct uint64_extra return z; } #else -struct uint64_extra - softfloat_shiftRightJam64Extra( - uint64_t a, uint64_t extra, uint_fast32_t dist ); +struct uint64_extra softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint_fast32_t dist); #endif #endif @@ -430,8 +392,7 @@ struct uint64_extra | greater than 128, the result will be either 0 or 1, depending on whether the | original 128 bits are all zeros. *----------------------------------------------------------------------------*/ -struct uint128 - softfloat_shiftRightJam128( uint64_t a64, uint64_t a0, uint_fast32_t dist ); +struct uint128 softfloat_shiftRightJam128(uint64_t a64, uint64_t a0, uint_fast32_t dist); #endif #ifndef softfloat_shiftRightJam128Extra @@ -452,9 +413,7 @@ struct uint128 | is modified as described above and returned in the 'extra' field of the | result.) *----------------------------------------------------------------------------*/ -struct uint128_extra - softfloat_shiftRightJam128Extra( - uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist ); +struct uint128_extra softfloat_shiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint_fast32_t dist); #endif #ifndef softfloat_shiftRightJam256M @@ -470,9 +429,7 @@ struct uint128_extra | is greater than 256, the stored result will be either 0 or 1, depending on | whether the original 256 bits are all zeros. *----------------------------------------------------------------------------*/ -void - softfloat_shiftRightJam256M( - const uint64_t *aPtr, uint_fast32_t dist, uint64_t *zPtr ); +void softfloat_shiftRightJam256M(const uint64_t* aPtr, uint_fast32_t dist, uint64_t* zPtr); #endif #ifndef softfloat_add128 @@ -483,17 +440,14 @@ void *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) INLINE -struct uint128 - softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) -{ +struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { struct uint128 z; z.v0 = a0 + b0; z.v64 = a64 + b64 + (z.v0 < a0); return z; } #else -struct uint128 - softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); +struct uint128 softfloat_add128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0); #endif #endif @@ -505,9 +459,7 @@ struct uint128 | an array of four 64-bit elements that concatenate in the platform's normal | endian order to form a 256-bit integer. *----------------------------------------------------------------------------*/ -void - softfloat_add256M( - const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr ); +void softfloat_add256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPtr); #endif #ifndef softfloat_sub128 @@ -518,9 +470,7 @@ void *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) INLINE -struct uint128 - softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ) -{ +struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0) { struct uint128 z; z.v0 = a0 - b0; z.v64 = a64 - b64; @@ -528,8 +478,7 @@ struct uint128 return z; } #else -struct uint128 - softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 ); +struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0); #endif #endif @@ -542,9 +491,7 @@ struct uint128 | 64-bit elements that concatenate in the platform's normal endian order to | form a 256-bit integer. *----------------------------------------------------------------------------*/ -void - softfloat_sub256M( - const uint64_t *aPtr, const uint64_t *bPtr, uint64_t *zPtr ); +void softfloat_sub256M(const uint64_t* aPtr, const uint64_t* bPtr, uint64_t* zPtr); #endif #ifndef softfloat_mul64ByShifted32To128 @@ -552,17 +499,16 @@ void | Returns the 128-bit product of 'a', 'b', and 2^32. *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (3 <= INLINE_LEVEL) -INLINE struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b ) -{ +INLINE struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b) { uint_fast64_t mid; struct uint128 z; - mid = (uint_fast64_t) (uint32_t) a * b; - z.v0 = mid<<32; - z.v64 = (uint_fast64_t) (uint32_t) (a>>32) * b + (mid>>32); + mid = (uint_fast64_t)(uint32_t)a * b; + z.v0 = mid << 32; + z.v64 = (uint_fast64_t)(uint32_t)(a >> 32) * b + (mid >> 32); return z; } #else -struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b ); +struct uint128 softfloat_mul64ByShifted32To128(uint64_t a, uint32_t b); #endif #endif @@ -570,7 +516,7 @@ struct uint128 softfloat_mul64ByShifted32To128( uint64_t a, uint32_t b ); /*---------------------------------------------------------------------------- | Returns the 128-bit product of 'a' and 'b'. *----------------------------------------------------------------------------*/ -struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b ); +struct uint128 softfloat_mul64To128(uint64_t a, uint64_t b); #endif #ifndef softfloat_mul128By32 @@ -581,19 +527,18 @@ struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b ); *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (4 <= INLINE_LEVEL) INLINE -struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b ) -{ +struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b) { struct uint128 z; uint_fast64_t mid; uint_fast32_t carry; z.v0 = a0 * b; - mid = (uint_fast64_t) (uint32_t) (a0>>32) * b; - carry = (uint32_t) ((uint_fast32_t) (z.v0>>32) - (uint_fast32_t) mid); - z.v64 = a64 * b + (uint_fast32_t) ((mid + carry)>>32); + mid = (uint_fast64_t)(uint32_t)(a0 >> 32) * b; + carry = (uint32_t)((uint_fast32_t)(z.v0 >> 32) - (uint_fast32_t)mid); + z.v64 = a64 * b + (uint_fast32_t)((mid + carry) >> 32); return z; } #else -struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b ); +struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b); #endif #endif @@ -605,9 +550,7 @@ struct uint128 softfloat_mul128By32( uint64_t a64, uint64_t a0, uint32_t b ); | Argument 'zPtr' points to an array of four 64-bit elements that concatenate | in the platform's normal endian order to form a 256-bit integer. *----------------------------------------------------------------------------*/ -void - softfloat_mul128To256M( - uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t *zPtr ); +void softfloat_mul128To256M(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0, uint64_t* zPtr); #endif #else @@ -626,7 +569,7 @@ void | Each of 'aPtr' and 'bPtr' points to an array of three 32-bit elements that | concatenate in the platform's normal endian order to form a 96-bit integer. *----------------------------------------------------------------------------*/ -int_fast8_t softfloat_compare96M( const uint32_t *aPtr, const uint32_t *bPtr ); +int_fast8_t softfloat_compare96M(const uint32_t* aPtr, const uint32_t* bPtr); #endif #ifndef softfloat_compare128M @@ -638,8 +581,7 @@ int_fast8_t softfloat_compare96M( const uint32_t *aPtr, const uint32_t *bPtr ); | Each of 'aPtr' and 'bPtr' points to an array of four 32-bit elements that | concatenate in the platform's normal endian order to form a 128-bit integer. *----------------------------------------------------------------------------*/ -int_fast8_t - softfloat_compare128M( const uint32_t *aPtr, const uint32_t *bPtr ); +int_fast8_t softfloat_compare128M(const uint32_t* aPtr, const uint32_t* bPtr); #endif #ifndef softfloat_shortShiftLeft64To96M @@ -652,19 +594,14 @@ int_fast8_t *----------------------------------------------------------------------------*/ #if defined INLINE_LEVEL && (2 <= INLINE_LEVEL) INLINE -void - softfloat_shortShiftLeft64To96M( - uint64_t a, uint_fast8_t dist, uint32_t *zPtr ) -{ - zPtr[indexWord( 3, 0 )] = (uint32_t) a<>= 32 - dist; - zPtr[indexWord( 3, 2 )] = a>>32; - zPtr[indexWord( 3, 1 )] = a; + zPtr[indexWord(3, 2)] = a >> 32; + zPtr[indexWord(3, 1)] = a; } #else -void - softfloat_shortShiftLeft64To96M( - uint64_t a, uint_fast8_t dist, uint32_t *zPtr ); +void softfloat_shortShiftLeft64To96M(uint64_t a, uint_fast8_t dist, uint32_t* zPtr); #endif #endif @@ -678,13 +615,7 @@ void | that concatenate in the platform's normal endian order to form an N-bit | integer. *----------------------------------------------------------------------------*/ -void - softfloat_shortShiftLeftM( - uint_fast8_t size_words, - const uint32_t *aPtr, - uint_fast8_t dist, - uint32_t *zPtr - ); +void softfloat_shortShiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint_fast8_t dist, uint32_t* zPtr); #endif #ifndef softfloat_shortShiftLeft96M @@ -692,7 +623,7 @@ void | This function or macro is the same as 'softfloat_shortShiftLeftM' with | 'size_words' = 3 (N = 96). *----------------------------------------------------------------------------*/ -#define softfloat_shortShiftLeft96M( aPtr, dist, zPtr ) softfloat_shortShiftLeftM( 3, aPtr, dist, zPtr ) +#define softfloat_shortShiftLeft96M(aPtr, dist, zPtr) softfloat_shortShiftLeftM(3, aPtr, dist, zPtr) #endif #ifndef softfloat_shortShiftLeft128M @@ -700,7 +631,7 @@ void | This function or macro is the same as 'softfloat_shortShiftLeftM' with | 'size_words' = 4 (N = 128). *----------------------------------------------------------------------------*/ -#define softfloat_shortShiftLeft128M( aPtr, dist, zPtr ) softfloat_shortShiftLeftM( 4, aPtr, dist, zPtr ) +#define softfloat_shortShiftLeft128M(aPtr, dist, zPtr) softfloat_shortShiftLeftM(4, aPtr, dist, zPtr) #endif #ifndef softfloat_shortShiftLeft160M @@ -708,7 +639,7 @@ void | This function or macro is the same as 'softfloat_shortShiftLeftM' with | 'size_words' = 5 (N = 160). *----------------------------------------------------------------------------*/ -#define softfloat_shortShiftLeft160M( aPtr, dist, zPtr ) softfloat_shortShiftLeftM( 5, aPtr, dist, zPtr ) +#define softfloat_shortShiftLeft160M(aPtr, dist, zPtr) softfloat_shortShiftLeftM(5, aPtr, dist, zPtr) #endif #ifndef softfloat_shiftLeftM @@ -722,13 +653,7 @@ void | The value of 'dist' can be arbitrarily large. In particular, if 'dist' is | greater than N, the stored result will be 0. *----------------------------------------------------------------------------*/ -void - softfloat_shiftLeftM( - uint_fast8_t size_words, - const uint32_t *aPtr, - uint32_t dist, - uint32_t *zPtr - ); +void softfloat_shiftLeftM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr); #endif #ifndef softfloat_shiftLeft96M @@ -736,7 +661,7 @@ void | This function or macro is the same as 'softfloat_shiftLeftM' with | 'size_words' = 3 (N = 96). *----------------------------------------------------------------------------*/ -#define softfloat_shiftLeft96M( aPtr, dist, zPtr ) softfloat_shiftLeftM( 3, aPtr, dist, zPtr ) +#define softfloat_shiftLeft96M(aPtr, dist, zPtr) softfloat_shiftLeftM(3, aPtr, dist, zPtr) #endif #ifndef softfloat_shiftLeft128M @@ -744,7 +669,7 @@ void | This function or macro is the same as 'softfloat_shiftLeftM' with | 'size_words' = 4 (N = 128). *----------------------------------------------------------------------------*/ -#define softfloat_shiftLeft128M( aPtr, dist, zPtr ) softfloat_shiftLeftM( 4, aPtr, dist, zPtr ) +#define softfloat_shiftLeft128M(aPtr, dist, zPtr) softfloat_shiftLeftM(4, aPtr, dist, zPtr) #endif #ifndef softfloat_shiftLeft160M @@ -752,7 +677,7 @@ void | This function or macro is the same as 'softfloat_shiftLeftM' with | 'size_words' = 5 (N = 160). *----------------------------------------------------------------------------*/ -#define softfloat_shiftLeft160M( aPtr, dist, zPtr ) softfloat_shiftLeftM( 5, aPtr, dist, zPtr ) +#define softfloat_shiftLeft160M(aPtr, dist, zPtr) softfloat_shiftLeftM(5, aPtr, dist, zPtr) #endif #ifndef softfloat_shortShiftRightM @@ -765,13 +690,7 @@ void | that concatenate in the platform's normal endian order to form an N-bit | integer. *----------------------------------------------------------------------------*/ -void - softfloat_shortShiftRightM( - uint_fast8_t size_words, - const uint32_t *aPtr, - uint_fast8_t dist, - uint32_t *zPtr - ); +void softfloat_shortShiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint_fast8_t dist, uint32_t* zPtr); #endif #ifndef softfloat_shortShiftRight128M @@ -779,7 +698,7 @@ void | This function or macro is the same as 'softfloat_shortShiftRightM' with | 'size_words' = 4 (N = 128). *----------------------------------------------------------------------------*/ -#define softfloat_shortShiftRight128M( aPtr, dist, zPtr ) softfloat_shortShiftRightM( 4, aPtr, dist, zPtr ) +#define softfloat_shortShiftRight128M(aPtr, dist, zPtr) softfloat_shortShiftRightM(4, aPtr, dist, zPtr) #endif #ifndef softfloat_shortShiftRight160M @@ -787,7 +706,7 @@ void | This function or macro is the same as 'softfloat_shortShiftRightM' with | 'size_words' = 5 (N = 160). *----------------------------------------------------------------------------*/ -#define softfloat_shortShiftRight160M( aPtr, dist, zPtr ) softfloat_shortShiftRightM( 5, aPtr, dist, zPtr ) +#define softfloat_shortShiftRight160M(aPtr, dist, zPtr) softfloat_shortShiftRightM(5, aPtr, dist, zPtr) #endif #ifndef softfloat_shortShiftRightJamM @@ -801,9 +720,7 @@ void | to a 'size_words'-long array of 32-bit elements that concatenate in the | platform's normal endian order to form an N-bit integer. *----------------------------------------------------------------------------*/ -void - softfloat_shortShiftRightJamM( - uint_fast8_t, const uint32_t *, uint_fast8_t, uint32_t * ); +void softfloat_shortShiftRightJamM(uint_fast8_t, const uint32_t*, uint_fast8_t, uint32_t*); #endif #ifndef softfloat_shortShiftRightJam160M @@ -811,7 +728,7 @@ void | This function or macro is the same as 'softfloat_shortShiftRightJamM' with | 'size_words' = 5 (N = 160). *----------------------------------------------------------------------------*/ -#define softfloat_shortShiftRightJam160M( aPtr, dist, zPtr ) softfloat_shortShiftRightJamM( 5, aPtr, dist, zPtr ) +#define softfloat_shortShiftRightJam160M(aPtr, dist, zPtr) softfloat_shortShiftRightJamM(5, aPtr, dist, zPtr) #endif #ifndef softfloat_shiftRightM @@ -825,13 +742,7 @@ void | The value of 'dist' can be arbitrarily large. In particular, if 'dist' is | greater than N, the stored result will be 0. *----------------------------------------------------------------------------*/ -void - softfloat_shiftRightM( - uint_fast8_t size_words, - const uint32_t *aPtr, - uint32_t dist, - uint32_t *zPtr - ); +void softfloat_shiftRightM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr); #endif #ifndef softfloat_shiftRight96M @@ -839,7 +750,7 @@ void | This function or macro is the same as 'softfloat_shiftRightM' with | 'size_words' = 3 (N = 96). *----------------------------------------------------------------------------*/ -#define softfloat_shiftRight96M( aPtr, dist, zPtr ) softfloat_shiftRightM( 3, aPtr, dist, zPtr ) +#define softfloat_shiftRight96M(aPtr, dist, zPtr) softfloat_shiftRightM(3, aPtr, dist, zPtr) #endif #ifndef softfloat_shiftRightJamM @@ -856,13 +767,7 @@ void | is greater than N, the stored result will be either 0 or 1, depending on | whether the original N bits are all zeros. *----------------------------------------------------------------------------*/ -void - softfloat_shiftRightJamM( - uint_fast8_t size_words, - const uint32_t *aPtr, - uint32_t dist, - uint32_t *zPtr - ); +void softfloat_shiftRightJamM(uint_fast8_t size_words, const uint32_t* aPtr, uint32_t dist, uint32_t* zPtr); #endif #ifndef softfloat_shiftRightJam96M @@ -870,7 +775,7 @@ void | This function or macro is the same as 'softfloat_shiftRightJamM' with | 'size_words' = 3 (N = 96). *----------------------------------------------------------------------------*/ -#define softfloat_shiftRightJam96M( aPtr, dist, zPtr ) softfloat_shiftRightJamM( 3, aPtr, dist, zPtr ) +#define softfloat_shiftRightJam96M(aPtr, dist, zPtr) softfloat_shiftRightJamM(3, aPtr, dist, zPtr) #endif #ifndef softfloat_shiftRightJam128M @@ -878,7 +783,7 @@ void | This function or macro is the same as 'softfloat_shiftRightJamM' with | 'size_words' = 4 (N = 128). *----------------------------------------------------------------------------*/ -#define softfloat_shiftRightJam128M( aPtr, dist, zPtr ) softfloat_shiftRightJamM( 4, aPtr, dist, zPtr ) +#define softfloat_shiftRightJam128M(aPtr, dist, zPtr) softfloat_shiftRightJamM(4, aPtr, dist, zPtr) #endif #ifndef softfloat_shiftRightJam160M @@ -886,7 +791,7 @@ void | This function or macro is the same as 'softfloat_shiftRightJamM' with | 'size_words' = 5 (N = 160). *----------------------------------------------------------------------------*/ -#define softfloat_shiftRightJam160M( aPtr, dist, zPtr ) softfloat_shiftRightJamM( 5, aPtr, dist, zPtr ) +#define softfloat_shiftRightJam160M(aPtr, dist, zPtr) softfloat_shiftRightJamM(5, aPtr, dist, zPtr) #endif #ifndef softfloat_addM @@ -898,13 +803,7 @@ void | elements that concatenate in the platform's normal endian order to form an | N-bit integer. *----------------------------------------------------------------------------*/ -void - softfloat_addM( - uint_fast8_t size_words, - const uint32_t *aPtr, - const uint32_t *bPtr, - uint32_t *zPtr - ); +void softfloat_addM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr); #endif #ifndef softfloat_add96M @@ -912,7 +811,7 @@ void | This function or macro is the same as 'softfloat_addM' with 'size_words' | = 3 (N = 96). *----------------------------------------------------------------------------*/ -#define softfloat_add96M( aPtr, bPtr, zPtr ) softfloat_addM( 3, aPtr, bPtr, zPtr ) +#define softfloat_add96M(aPtr, bPtr, zPtr) softfloat_addM(3, aPtr, bPtr, zPtr) #endif #ifndef softfloat_add128M @@ -920,7 +819,7 @@ void | This function or macro is the same as 'softfloat_addM' with 'size_words' | = 4 (N = 128). *----------------------------------------------------------------------------*/ -#define softfloat_add128M( aPtr, bPtr, zPtr ) softfloat_addM( 4, aPtr, bPtr, zPtr ) +#define softfloat_add128M(aPtr, bPtr, zPtr) softfloat_addM(4, aPtr, bPtr, zPtr) #endif #ifndef softfloat_add160M @@ -928,7 +827,7 @@ void | This function or macro is the same as 'softfloat_addM' with 'size_words' | = 5 (N = 160). *----------------------------------------------------------------------------*/ -#define softfloat_add160M( aPtr, bPtr, zPtr ) softfloat_addM( 5, aPtr, bPtr, zPtr ) +#define softfloat_add160M(aPtr, bPtr, zPtr) softfloat_addM(5, aPtr, bPtr, zPtr) #endif #ifndef softfloat_addCarryM @@ -940,14 +839,7 @@ void | points to a 'size_words'-long array of 32-bit elements that concatenate in | the platform's normal endian order to form an N-bit integer. *----------------------------------------------------------------------------*/ -uint_fast8_t - softfloat_addCarryM( - uint_fast8_t size_words, - const uint32_t *aPtr, - const uint32_t *bPtr, - uint_fast8_t carry, - uint32_t *zPtr - ); +uint_fast8_t softfloat_addCarryM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint_fast8_t carry, uint32_t* zPtr); #endif #ifndef softfloat_addComplCarryM @@ -956,14 +848,8 @@ uint_fast8_t | the value of the unsigned integer pointed to by 'bPtr' is bit-wise completed | before the addition. *----------------------------------------------------------------------------*/ -uint_fast8_t - softfloat_addComplCarryM( - uint_fast8_t size_words, - const uint32_t *aPtr, - const uint32_t *bPtr, - uint_fast8_t carry, - uint32_t *zPtr - ); +uint_fast8_t softfloat_addComplCarryM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint_fast8_t carry, + uint32_t* zPtr); #endif #ifndef softfloat_addComplCarry96M @@ -971,7 +857,7 @@ uint_fast8_t | This function or macro is the same as 'softfloat_addComplCarryM' with | 'size_words' = 3 (N = 96). *----------------------------------------------------------------------------*/ -#define softfloat_addComplCarry96M( aPtr, bPtr, carry, zPtr ) softfloat_addComplCarryM( 3, aPtr, bPtr, carry, zPtr ) +#define softfloat_addComplCarry96M(aPtr, bPtr, carry, zPtr) softfloat_addComplCarryM(3, aPtr, bPtr, carry, zPtr) #endif #ifndef softfloat_negXM @@ -981,7 +867,7 @@ uint_fast8_t | points to a 'size_words'-long array of 32-bit elements that concatenate in | the platform's normal endian order to form an N-bit integer. *----------------------------------------------------------------------------*/ -void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr ); +void softfloat_negXM(uint_fast8_t size_words, uint32_t* zPtr); #endif #ifndef softfloat_negX96M @@ -989,7 +875,7 @@ void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr ); | This function or macro is the same as 'softfloat_negXM' with 'size_words' | = 3 (N = 96). *----------------------------------------------------------------------------*/ -#define softfloat_negX96M( zPtr ) softfloat_negXM( 3, zPtr ) +#define softfloat_negX96M(zPtr) softfloat_negXM(3, zPtr) #endif #ifndef softfloat_negX128M @@ -997,7 +883,7 @@ void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr ); | This function or macro is the same as 'softfloat_negXM' with 'size_words' | = 4 (N = 128). *----------------------------------------------------------------------------*/ -#define softfloat_negX128M( zPtr ) softfloat_negXM( 4, zPtr ) +#define softfloat_negX128M(zPtr) softfloat_negXM(4, zPtr) #endif #ifndef softfloat_negX160M @@ -1005,7 +891,7 @@ void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr ); | This function or macro is the same as 'softfloat_negXM' with 'size_words' | = 5 (N = 160). *----------------------------------------------------------------------------*/ -#define softfloat_negX160M( zPtr ) softfloat_negXM( 5, zPtr ) +#define softfloat_negX160M(zPtr) softfloat_negXM(5, zPtr) #endif #ifndef softfloat_negX256M @@ -1013,7 +899,7 @@ void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr ); | This function or macro is the same as 'softfloat_negXM' with 'size_words' | = 8 (N = 256). *----------------------------------------------------------------------------*/ -#define softfloat_negX256M( zPtr ) softfloat_negXM( 8, zPtr ) +#define softfloat_negX256M(zPtr) softfloat_negXM(8, zPtr) #endif #ifndef softfloat_sub1XM @@ -1024,7 +910,7 @@ void softfloat_negXM( uint_fast8_t size_words, uint32_t *zPtr ); | elements that concatenate in the platform's normal endian order to form an | N-bit integer. *----------------------------------------------------------------------------*/ -void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr ); +void softfloat_sub1XM(uint_fast8_t size_words, uint32_t* zPtr); #endif #ifndef softfloat_sub1X96M @@ -1032,7 +918,7 @@ void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr ); | This function or macro is the same as 'softfloat_sub1XM' with 'size_words' | = 3 (N = 96). *----------------------------------------------------------------------------*/ -#define softfloat_sub1X96M( zPtr ) softfloat_sub1XM( 3, zPtr ) +#define softfloat_sub1X96M(zPtr) softfloat_sub1XM(3, zPtr) #endif #ifndef softfloat_sub1X160M @@ -1040,7 +926,7 @@ void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr ); | This function or macro is the same as 'softfloat_sub1XM' with 'size_words' | = 5 (N = 160). *----------------------------------------------------------------------------*/ -#define softfloat_sub1X160M( zPtr ) softfloat_sub1XM( 5, zPtr ) +#define softfloat_sub1X160M(zPtr) softfloat_sub1XM(5, zPtr) #endif #ifndef softfloat_subM @@ -1052,13 +938,7 @@ void softfloat_sub1XM( uint_fast8_t size_words, uint32_t *zPtr ); | array of 32-bit elements that concatenate in the platform's normal endian | order to form an N-bit integer. *----------------------------------------------------------------------------*/ -void - softfloat_subM( - uint_fast8_t size_words, - const uint32_t *aPtr, - const uint32_t *bPtr, - uint32_t *zPtr - ); +void softfloat_subM(uint_fast8_t size_words, const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr); #endif #ifndef softfloat_sub96M @@ -1066,7 +946,7 @@ void | This function or macro is the same as 'softfloat_subM' with 'size_words' | = 3 (N = 96). *----------------------------------------------------------------------------*/ -#define softfloat_sub96M( aPtr, bPtr, zPtr ) softfloat_subM( 3, aPtr, bPtr, zPtr ) +#define softfloat_sub96M(aPtr, bPtr, zPtr) softfloat_subM(3, aPtr, bPtr, zPtr) #endif #ifndef softfloat_sub128M @@ -1074,7 +954,7 @@ void | This function or macro is the same as 'softfloat_subM' with 'size_words' | = 4 (N = 128). *----------------------------------------------------------------------------*/ -#define softfloat_sub128M( aPtr, bPtr, zPtr ) softfloat_subM( 4, aPtr, bPtr, zPtr ) +#define softfloat_sub128M(aPtr, bPtr, zPtr) softfloat_subM(4, aPtr, bPtr, zPtr) #endif #ifndef softfloat_sub160M @@ -1082,7 +962,7 @@ void | This function or macro is the same as 'softfloat_subM' with 'size_words' | = 5 (N = 160). *----------------------------------------------------------------------------*/ -#define softfloat_sub160M( aPtr, bPtr, zPtr ) softfloat_subM( 5, aPtr, bPtr, zPtr ) +#define softfloat_sub160M(aPtr, bPtr, zPtr) softfloat_subM(5, aPtr, bPtr, zPtr) #endif #ifndef softfloat_mul64To128M @@ -1092,7 +972,7 @@ void | elements that concatenate in the platform's normal endian order to form a | 128-bit integer. *----------------------------------------------------------------------------*/ -void softfloat_mul64To128M( uint64_t a, uint64_t b, uint32_t *zPtr ); +void softfloat_mul64To128M(uint64_t a, uint64_t b, uint32_t* zPtr); #endif #ifndef softfloat_mul128MTo256M @@ -1104,9 +984,7 @@ void softfloat_mul64To128M( uint64_t a, uint64_t b, uint32_t *zPtr ); | Argument 'zPtr' points to an array of eight 32-bit elements that concatenate | to form a 256-bit integer. *----------------------------------------------------------------------------*/ -void - softfloat_mul128MTo256M( - const uint32_t *aPtr, const uint32_t *bPtr, uint32_t *zPtr ); +void softfloat_mul128MTo256M(const uint32_t* aPtr, const uint32_t* bPtr, uint32_t* zPtr); #endif #ifndef softfloat_remStepMBy32 @@ -1119,15 +997,8 @@ void | to a 'size_words'-long array of 32-bit elements that concatenate in the | platform's normal endian order to form an N-bit integer. *----------------------------------------------------------------------------*/ -void - softfloat_remStepMBy32( - uint_fast8_t size_words, - const uint32_t *remPtr, - uint_fast8_t dist, - const uint32_t *bPtr, - uint32_t q, - uint32_t *zPtr - ); +void softfloat_remStepMBy32(uint_fast8_t size_words, const uint32_t* remPtr, uint_fast8_t dist, const uint32_t* bPtr, uint32_t q, + uint32_t* zPtr); #endif #ifndef softfloat_remStep96MBy32 @@ -1135,7 +1006,7 @@ void | This function or macro is the same as 'softfloat_remStepMBy32' with | 'size_words' = 3 (N = 96). *----------------------------------------------------------------------------*/ -#define softfloat_remStep96MBy32( remPtr, dist, bPtr, q, zPtr ) softfloat_remStepMBy32( 3, remPtr, dist, bPtr, q, zPtr ) +#define softfloat_remStep96MBy32(remPtr, dist, bPtr, q, zPtr) softfloat_remStepMBy32(3, remPtr, dist, bPtr, q, zPtr) #endif #ifndef softfloat_remStep128MBy32 @@ -1143,7 +1014,7 @@ void | This function or macro is the same as 'softfloat_remStepMBy32' with | 'size_words' = 4 (N = 128). *----------------------------------------------------------------------------*/ -#define softfloat_remStep128MBy32( remPtr, dist, bPtr, q, zPtr ) softfloat_remStepMBy32( 4, remPtr, dist, bPtr, q, zPtr ) +#define softfloat_remStep128MBy32(remPtr, dist, bPtr, q, zPtr) softfloat_remStepMBy32(4, remPtr, dist, bPtr, q, zPtr) #endif #ifndef softfloat_remStep160MBy32 @@ -1151,10 +1022,9 @@ void | This function or macro is the same as 'softfloat_remStepMBy32' with | 'size_words' = 5 (N = 160). *----------------------------------------------------------------------------*/ -#define softfloat_remStep160MBy32( remPtr, dist, bPtr, q, zPtr ) softfloat_remStepMBy32( 5, remPtr, dist, bPtr, q, zPtr ) +#define softfloat_remStep160MBy32(remPtr, dist, bPtr, q, zPtr) softfloat_remStepMBy32(5, remPtr, dist, bPtr, q, zPtr) #endif #endif #endif - diff --git a/softfloat/source/include/softfloat.h b/softfloat/source/include/softfloat.h index b33374c..f07211e 100644 --- a/softfloat/source/include/softfloat.h +++ b/softfloat/source/include/softfloat.h @@ -34,7 +34,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================*/ - /*============================================================================ | Note: If SoftFloat is made available as a general library for programs to | use, it is strongly recommended that a platform-specific version of this @@ -42,13 +41,12 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | eliminates all dependencies on compile-time macros. *============================================================================*/ - #ifndef softfloat_h #define softfloat_h 1 +#include "softfloat_types.h" #include #include -#include "softfloat_types.h" #ifndef THREAD_LOCAL #define THREAD_LOCAL @@ -58,10 +56,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | Software floating-point underflow tininess-detection mode. *----------------------------------------------------------------------------*/ extern THREAD_LOCAL uint_fast8_t softfloat_detectTininess; -enum { - softfloat_tininess_beforeRounding = 0, - softfloat_tininess_afterRounding = 1 -}; +enum { softfloat_tininess_beforeRounding = 0, softfloat_tininess_afterRounding = 1 }; /*---------------------------------------------------------------------------- | Software floating-point rounding mode. (Mode "odd" is supported only if @@ -69,12 +64,12 @@ enum { *----------------------------------------------------------------------------*/ extern THREAD_LOCAL uint_fast8_t softfloat_roundingMode; enum { - softfloat_round_near_even = 0, - softfloat_round_minMag = 1, - softfloat_round_min = 2, - softfloat_round_max = 3, + softfloat_round_near_even = 0, + softfloat_round_minMag = 1, + softfloat_round_min = 2, + softfloat_round_max = 3, softfloat_round_near_maxMag = 4, - softfloat_round_odd = 6 + softfloat_round_odd = 6 }; /*---------------------------------------------------------------------------- @@ -82,162 +77,162 @@ enum { *----------------------------------------------------------------------------*/ extern THREAD_LOCAL uint_fast8_t softfloat_exceptionFlags; enum { - softfloat_flag_inexact = 1, - softfloat_flag_underflow = 2, - softfloat_flag_overflow = 4, - softfloat_flag_infinite = 8, - softfloat_flag_invalid = 16 + softfloat_flag_inexact = 1, + softfloat_flag_underflow = 2, + softfloat_flag_overflow = 4, + softfloat_flag_infinite = 8, + softfloat_flag_invalid = 16 }; /*---------------------------------------------------------------------------- | Routine to raise any or all of the software floating-point exception flags. *----------------------------------------------------------------------------*/ -void softfloat_raiseFlags( uint_fast8_t ); +void softfloat_raiseFlags(uint_fast8_t); /*---------------------------------------------------------------------------- | Integer-to-floating-point conversion routines. *----------------------------------------------------------------------------*/ -float16_t ui32_to_f16( uint32_t ); -float32_t ui32_to_f32( uint32_t ); -float64_t ui32_to_f64( uint32_t ); +float16_t ui32_to_f16(uint32_t); +float32_t ui32_to_f32(uint32_t); +float64_t ui32_to_f64(uint32_t); #ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t ui32_to_extF80( uint32_t ); -float128_t ui32_to_f128( uint32_t ); +extFloat80_t ui32_to_extF80(uint32_t); +float128_t ui32_to_f128(uint32_t); #endif -void ui32_to_extF80M( uint32_t, extFloat80_t * ); -void ui32_to_f128M( uint32_t, float128_t * ); -float16_t ui64_to_f16( uint64_t ); -float32_t ui64_to_f32( uint64_t ); -float64_t ui64_to_f64( uint64_t ); +void ui32_to_extF80M(uint32_t, extFloat80_t*); +void ui32_to_f128M(uint32_t, float128_t*); +float16_t ui64_to_f16(uint64_t); +float32_t ui64_to_f32(uint64_t); +float64_t ui64_to_f64(uint64_t); #ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t ui64_to_extF80( uint64_t ); -float128_t ui64_to_f128( uint64_t ); +extFloat80_t ui64_to_extF80(uint64_t); +float128_t ui64_to_f128(uint64_t); #endif -void ui64_to_extF80M( uint64_t, extFloat80_t * ); -void ui64_to_f128M( uint64_t, float128_t * ); -float16_t i32_to_f16( int32_t ); -float32_t i32_to_f32( int32_t ); -float64_t i32_to_f64( int32_t ); +void ui64_to_extF80M(uint64_t, extFloat80_t*); +void ui64_to_f128M(uint64_t, float128_t*); +float16_t i32_to_f16(int32_t); +float32_t i32_to_f32(int32_t); +float64_t i32_to_f64(int32_t); #ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t i32_to_extF80( int32_t ); -float128_t i32_to_f128( int32_t ); +extFloat80_t i32_to_extF80(int32_t); +float128_t i32_to_f128(int32_t); #endif -void i32_to_extF80M( int32_t, extFloat80_t * ); -void i32_to_f128M( int32_t, float128_t * ); -float16_t i64_to_f16( int64_t ); -float32_t i64_to_f32( int64_t ); -float64_t i64_to_f64( int64_t ); +void i32_to_extF80M(int32_t, extFloat80_t*); +void i32_to_f128M(int32_t, float128_t*); +float16_t i64_to_f16(int64_t); +float32_t i64_to_f32(int64_t); +float64_t i64_to_f64(int64_t); #ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t i64_to_extF80( int64_t ); -float128_t i64_to_f128( int64_t ); +extFloat80_t i64_to_extF80(int64_t); +float128_t i64_to_f128(int64_t); #endif -void i64_to_extF80M( int64_t, extFloat80_t * ); -void i64_to_f128M( int64_t, float128_t * ); +void i64_to_extF80M(int64_t, extFloat80_t*); +void i64_to_f128M(int64_t, float128_t*); /*---------------------------------------------------------------------------- | 16-bit (half-precision) floating-point operations. *----------------------------------------------------------------------------*/ -uint_fast32_t f16_to_ui32( float16_t, uint_fast8_t, bool ); -uint_fast64_t f16_to_ui64( float16_t, uint_fast8_t, bool ); -int_fast32_t f16_to_i32( float16_t, uint_fast8_t, bool ); -int_fast64_t f16_to_i64( float16_t, uint_fast8_t, bool ); -uint_fast32_t f16_to_ui32_r_minMag( float16_t, bool ); -uint_fast64_t f16_to_ui64_r_minMag( float16_t, bool ); -int_fast32_t f16_to_i32_r_minMag( float16_t, bool ); -int_fast64_t f16_to_i64_r_minMag( float16_t, bool ); -float32_t f16_to_f32( float16_t ); -float64_t f16_to_f64( float16_t ); +uint_fast32_t f16_to_ui32(float16_t, uint_fast8_t, bool); +uint_fast64_t f16_to_ui64(float16_t, uint_fast8_t, bool); +int_fast32_t f16_to_i32(float16_t, uint_fast8_t, bool); +int_fast64_t f16_to_i64(float16_t, uint_fast8_t, bool); +uint_fast32_t f16_to_ui32_r_minMag(float16_t, bool); +uint_fast64_t f16_to_ui64_r_minMag(float16_t, bool); +int_fast32_t f16_to_i32_r_minMag(float16_t, bool); +int_fast64_t f16_to_i64_r_minMag(float16_t, bool); +float32_t f16_to_f32(float16_t); +float64_t f16_to_f64(float16_t); #ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t f16_to_extF80( float16_t ); -float128_t f16_to_f128( float16_t ); +extFloat80_t f16_to_extF80(float16_t); +float128_t f16_to_f128(float16_t); #endif -void f16_to_extF80M( float16_t, extFloat80_t * ); -void f16_to_f128M( float16_t, float128_t * ); -float16_t f16_roundToInt( float16_t, uint_fast8_t, bool ); -float16_t f16_add( float16_t, float16_t ); -float16_t f16_sub( float16_t, float16_t ); -float16_t f16_mul( float16_t, float16_t ); -float16_t f16_mulAdd( float16_t, float16_t, float16_t ); -float16_t f16_div( float16_t, float16_t ); -float16_t f16_rem( float16_t, float16_t ); -float16_t f16_sqrt( float16_t ); -bool f16_eq( float16_t, float16_t ); -bool f16_le( float16_t, float16_t ); -bool f16_lt( float16_t, float16_t ); -bool f16_eq_signaling( float16_t, float16_t ); -bool f16_le_quiet( float16_t, float16_t ); -bool f16_lt_quiet( float16_t, float16_t ); -bool f16_isSignalingNaN( float16_t ); +void f16_to_extF80M(float16_t, extFloat80_t*); +void f16_to_f128M(float16_t, float128_t*); +float16_t f16_roundToInt(float16_t, uint_fast8_t, bool); +float16_t f16_add(float16_t, float16_t); +float16_t f16_sub(float16_t, float16_t); +float16_t f16_mul(float16_t, float16_t); +float16_t f16_mulAdd(float16_t, float16_t, float16_t); +float16_t f16_div(float16_t, float16_t); +float16_t f16_rem(float16_t, float16_t); +float16_t f16_sqrt(float16_t); +bool f16_eq(float16_t, float16_t); +bool f16_le(float16_t, float16_t); +bool f16_lt(float16_t, float16_t); +bool f16_eq_signaling(float16_t, float16_t); +bool f16_le_quiet(float16_t, float16_t); +bool f16_lt_quiet(float16_t, float16_t); +bool f16_isSignalingNaN(float16_t); /*---------------------------------------------------------------------------- | 32-bit (single-precision) floating-point operations. *----------------------------------------------------------------------------*/ -uint_fast32_t f32_to_ui32( float32_t, uint_fast8_t, bool ); -uint_fast64_t f32_to_ui64( float32_t, uint_fast8_t, bool ); -int_fast32_t f32_to_i32( float32_t, uint_fast8_t, bool ); -int_fast64_t f32_to_i64( float32_t, uint_fast8_t, bool ); -uint_fast32_t f32_to_ui32_r_minMag( float32_t, bool ); -uint_fast64_t f32_to_ui64_r_minMag( float32_t, bool ); -int_fast32_t f32_to_i32_r_minMag( float32_t, bool ); -int_fast64_t f32_to_i64_r_minMag( float32_t, bool ); -float16_t f32_to_f16( float32_t ); -float64_t f32_to_f64( float32_t ); +uint_fast32_t f32_to_ui32(float32_t, uint_fast8_t, bool); +uint_fast64_t f32_to_ui64(float32_t, uint_fast8_t, bool); +int_fast32_t f32_to_i32(float32_t, uint_fast8_t, bool); +int_fast64_t f32_to_i64(float32_t, uint_fast8_t, bool); +uint_fast32_t f32_to_ui32_r_minMag(float32_t, bool); +uint_fast64_t f32_to_ui64_r_minMag(float32_t, bool); +int_fast32_t f32_to_i32_r_minMag(float32_t, bool); +int_fast64_t f32_to_i64_r_minMag(float32_t, bool); +float16_t f32_to_f16(float32_t); +float64_t f32_to_f64(float32_t); #ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t f32_to_extF80( float32_t ); -float128_t f32_to_f128( float32_t ); +extFloat80_t f32_to_extF80(float32_t); +float128_t f32_to_f128(float32_t); #endif -void f32_to_extF80M( float32_t, extFloat80_t * ); -void f32_to_f128M( float32_t, float128_t * ); -float32_t f32_roundToInt( float32_t, uint_fast8_t, bool ); -float32_t f32_add( float32_t, float32_t ); -float32_t f32_sub( float32_t, float32_t ); -float32_t f32_mul( float32_t, float32_t ); -float32_t f32_mulAdd( float32_t, float32_t, float32_t ); -float32_t f32_div( float32_t, float32_t ); -float32_t f32_rem( float32_t, float32_t ); -float32_t f32_sqrt( float32_t ); -bool f32_eq( float32_t, float32_t ); -bool f32_le( float32_t, float32_t ); -bool f32_lt( float32_t, float32_t ); -bool f32_eq_signaling( float32_t, float32_t ); -bool f32_le_quiet( float32_t, float32_t ); -bool f32_lt_quiet( float32_t, float32_t ); -bool f32_isSignalingNaN( float32_t ); +void f32_to_extF80M(float32_t, extFloat80_t*); +void f32_to_f128M(float32_t, float128_t*); +float32_t f32_roundToInt(float32_t, uint_fast8_t, bool); +float32_t f32_add(float32_t, float32_t); +float32_t f32_sub(float32_t, float32_t); +float32_t f32_mul(float32_t, float32_t); +float32_t f32_mulAdd(float32_t, float32_t, float32_t); +float32_t f32_div(float32_t, float32_t); +float32_t f32_rem(float32_t, float32_t); +float32_t f32_sqrt(float32_t); +bool f32_eq(float32_t, float32_t); +bool f32_le(float32_t, float32_t); +bool f32_lt(float32_t, float32_t); +bool f32_eq_signaling(float32_t, float32_t); +bool f32_le_quiet(float32_t, float32_t); +bool f32_lt_quiet(float32_t, float32_t); +bool f32_isSignalingNaN(float32_t); /*---------------------------------------------------------------------------- | 64-bit (double-precision) floating-point operations. *----------------------------------------------------------------------------*/ -uint_fast32_t f64_to_ui32( float64_t, uint_fast8_t, bool ); -uint_fast64_t f64_to_ui64( float64_t, uint_fast8_t, bool ); -int_fast32_t f64_to_i32( float64_t, uint_fast8_t, bool ); -int_fast64_t f64_to_i64( float64_t, uint_fast8_t, bool ); -uint_fast32_t f64_to_ui32_r_minMag( float64_t, bool ); -uint_fast64_t f64_to_ui64_r_minMag( float64_t, bool ); -int_fast32_t f64_to_i32_r_minMag( float64_t, bool ); -int_fast64_t f64_to_i64_r_minMag( float64_t, bool ); -float16_t f64_to_f16( float64_t ); -float32_t f64_to_f32( float64_t ); +uint_fast32_t f64_to_ui32(float64_t, uint_fast8_t, bool); +uint_fast64_t f64_to_ui64(float64_t, uint_fast8_t, bool); +int_fast32_t f64_to_i32(float64_t, uint_fast8_t, bool); +int_fast64_t f64_to_i64(float64_t, uint_fast8_t, bool); +uint_fast32_t f64_to_ui32_r_minMag(float64_t, bool); +uint_fast64_t f64_to_ui64_r_minMag(float64_t, bool); +int_fast32_t f64_to_i32_r_minMag(float64_t, bool); +int_fast64_t f64_to_i64_r_minMag(float64_t, bool); +float16_t f64_to_f16(float64_t); +float32_t f64_to_f32(float64_t); #ifdef SOFTFLOAT_FAST_INT64 -extFloat80_t f64_to_extF80( float64_t ); -float128_t f64_to_f128( float64_t ); +extFloat80_t f64_to_extF80(float64_t); +float128_t f64_to_f128(float64_t); #endif -void f64_to_extF80M( float64_t, extFloat80_t * ); -void f64_to_f128M( float64_t, float128_t * ); -float64_t f64_roundToInt( float64_t, uint_fast8_t, bool ); -float64_t f64_add( float64_t, float64_t ); -float64_t f64_sub( float64_t, float64_t ); -float64_t f64_mul( float64_t, float64_t ); -float64_t f64_mulAdd( float64_t, float64_t, float64_t ); -float64_t f64_div( float64_t, float64_t ); -float64_t f64_rem( float64_t, float64_t ); -float64_t f64_sqrt( float64_t ); -bool f64_eq( float64_t, float64_t ); -bool f64_le( float64_t, float64_t ); -bool f64_lt( float64_t, float64_t ); -bool f64_eq_signaling( float64_t, float64_t ); -bool f64_le_quiet( float64_t, float64_t ); -bool f64_lt_quiet( float64_t, float64_t ); -bool f64_isSignalingNaN( float64_t ); +void f64_to_extF80M(float64_t, extFloat80_t*); +void f64_to_f128M(float64_t, float128_t*); +float64_t f64_roundToInt(float64_t, uint_fast8_t, bool); +float64_t f64_add(float64_t, float64_t); +float64_t f64_sub(float64_t, float64_t); +float64_t f64_mul(float64_t, float64_t); +float64_t f64_mulAdd(float64_t, float64_t, float64_t); +float64_t f64_div(float64_t, float64_t); +float64_t f64_rem(float64_t, float64_t); +float64_t f64_sqrt(float64_t); +bool f64_eq(float64_t, float64_t); +bool f64_le(float64_t, float64_t); +bool f64_lt(float64_t, float64_t); +bool f64_eq_signaling(float64_t, float64_t); +bool f64_le_quiet(float64_t, float64_t); +bool f64_lt_quiet(float64_t, float64_t); +bool f64_isSignalingNaN(float64_t); /*---------------------------------------------------------------------------- | Rounding precision for 80-bit extended double-precision floating-point. @@ -249,124 +244,118 @@ extern THREAD_LOCAL uint_fast8_t extF80_roundingPrecision; | 80-bit extended double-precision floating-point operations. *----------------------------------------------------------------------------*/ #ifdef SOFTFLOAT_FAST_INT64 -uint_fast32_t extF80_to_ui32( extFloat80_t, uint_fast8_t, bool ); -uint_fast64_t extF80_to_ui64( extFloat80_t, uint_fast8_t, bool ); -int_fast32_t extF80_to_i32( extFloat80_t, uint_fast8_t, bool ); -int_fast64_t extF80_to_i64( extFloat80_t, uint_fast8_t, bool ); -uint_fast32_t extF80_to_ui32_r_minMag( extFloat80_t, bool ); -uint_fast64_t extF80_to_ui64_r_minMag( extFloat80_t, bool ); -int_fast32_t extF80_to_i32_r_minMag( extFloat80_t, bool ); -int_fast64_t extF80_to_i64_r_minMag( extFloat80_t, bool ); -float16_t extF80_to_f16( extFloat80_t ); -float32_t extF80_to_f32( extFloat80_t ); -float64_t extF80_to_f64( extFloat80_t ); -float128_t extF80_to_f128( extFloat80_t ); -extFloat80_t extF80_roundToInt( extFloat80_t, uint_fast8_t, bool ); -extFloat80_t extF80_add( extFloat80_t, extFloat80_t ); -extFloat80_t extF80_sub( extFloat80_t, extFloat80_t ); -extFloat80_t extF80_mul( extFloat80_t, extFloat80_t ); -extFloat80_t extF80_div( extFloat80_t, extFloat80_t ); -extFloat80_t extF80_rem( extFloat80_t, extFloat80_t ); -extFloat80_t extF80_sqrt( extFloat80_t ); -bool extF80_eq( extFloat80_t, extFloat80_t ); -bool extF80_le( extFloat80_t, extFloat80_t ); -bool extF80_lt( extFloat80_t, extFloat80_t ); -bool extF80_eq_signaling( extFloat80_t, extFloat80_t ); -bool extF80_le_quiet( extFloat80_t, extFloat80_t ); -bool extF80_lt_quiet( extFloat80_t, extFloat80_t ); -bool extF80_isSignalingNaN( extFloat80_t ); +uint_fast32_t extF80_to_ui32(extFloat80_t, uint_fast8_t, bool); +uint_fast64_t extF80_to_ui64(extFloat80_t, uint_fast8_t, bool); +int_fast32_t extF80_to_i32(extFloat80_t, uint_fast8_t, bool); +int_fast64_t extF80_to_i64(extFloat80_t, uint_fast8_t, bool); +uint_fast32_t extF80_to_ui32_r_minMag(extFloat80_t, bool); +uint_fast64_t extF80_to_ui64_r_minMag(extFloat80_t, bool); +int_fast32_t extF80_to_i32_r_minMag(extFloat80_t, bool); +int_fast64_t extF80_to_i64_r_minMag(extFloat80_t, bool); +float16_t extF80_to_f16(extFloat80_t); +float32_t extF80_to_f32(extFloat80_t); +float64_t extF80_to_f64(extFloat80_t); +float128_t extF80_to_f128(extFloat80_t); +extFloat80_t extF80_roundToInt(extFloat80_t, uint_fast8_t, bool); +extFloat80_t extF80_add(extFloat80_t, extFloat80_t); +extFloat80_t extF80_sub(extFloat80_t, extFloat80_t); +extFloat80_t extF80_mul(extFloat80_t, extFloat80_t); +extFloat80_t extF80_div(extFloat80_t, extFloat80_t); +extFloat80_t extF80_rem(extFloat80_t, extFloat80_t); +extFloat80_t extF80_sqrt(extFloat80_t); +bool extF80_eq(extFloat80_t, extFloat80_t); +bool extF80_le(extFloat80_t, extFloat80_t); +bool extF80_lt(extFloat80_t, extFloat80_t); +bool extF80_eq_signaling(extFloat80_t, extFloat80_t); +bool extF80_le_quiet(extFloat80_t, extFloat80_t); +bool extF80_lt_quiet(extFloat80_t, extFloat80_t); +bool extF80_isSignalingNaN(extFloat80_t); #endif -uint_fast32_t extF80M_to_ui32( const extFloat80_t *, uint_fast8_t, bool ); -uint_fast64_t extF80M_to_ui64( const extFloat80_t *, uint_fast8_t, bool ); -int_fast32_t extF80M_to_i32( const extFloat80_t *, uint_fast8_t, bool ); -int_fast64_t extF80M_to_i64( const extFloat80_t *, uint_fast8_t, bool ); -uint_fast32_t extF80M_to_ui32_r_minMag( const extFloat80_t *, bool ); -uint_fast64_t extF80M_to_ui64_r_minMag( const extFloat80_t *, bool ); -int_fast32_t extF80M_to_i32_r_minMag( const extFloat80_t *, bool ); -int_fast64_t extF80M_to_i64_r_minMag( const extFloat80_t *, bool ); -float16_t extF80M_to_f16( const extFloat80_t * ); -float32_t extF80M_to_f32( const extFloat80_t * ); -float64_t extF80M_to_f64( const extFloat80_t * ); -void extF80M_to_f128M( const extFloat80_t *, float128_t * ); -void - extF80M_roundToInt( - const extFloat80_t *, uint_fast8_t, bool, extFloat80_t * ); -void extF80M_add( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ); -void extF80M_sub( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ); -void extF80M_mul( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ); -void extF80M_div( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ); -void extF80M_rem( const extFloat80_t *, const extFloat80_t *, extFloat80_t * ); -void extF80M_sqrt( const extFloat80_t *, extFloat80_t * ); -bool extF80M_eq( const extFloat80_t *, const extFloat80_t * ); -bool extF80M_le( const extFloat80_t *, const extFloat80_t * ); -bool extF80M_lt( const extFloat80_t *, const extFloat80_t * ); -bool extF80M_eq_signaling( const extFloat80_t *, const extFloat80_t * ); -bool extF80M_le_quiet( const extFloat80_t *, const extFloat80_t * ); -bool extF80M_lt_quiet( const extFloat80_t *, const extFloat80_t * ); -bool extF80M_isSignalingNaN( const extFloat80_t * ); +uint_fast32_t extF80M_to_ui32(const extFloat80_t*, uint_fast8_t, bool); +uint_fast64_t extF80M_to_ui64(const extFloat80_t*, uint_fast8_t, bool); +int_fast32_t extF80M_to_i32(const extFloat80_t*, uint_fast8_t, bool); +int_fast64_t extF80M_to_i64(const extFloat80_t*, uint_fast8_t, bool); +uint_fast32_t extF80M_to_ui32_r_minMag(const extFloat80_t*, bool); +uint_fast64_t extF80M_to_ui64_r_minMag(const extFloat80_t*, bool); +int_fast32_t extF80M_to_i32_r_minMag(const extFloat80_t*, bool); +int_fast64_t extF80M_to_i64_r_minMag(const extFloat80_t*, bool); +float16_t extF80M_to_f16(const extFloat80_t*); +float32_t extF80M_to_f32(const extFloat80_t*); +float64_t extF80M_to_f64(const extFloat80_t*); +void extF80M_to_f128M(const extFloat80_t*, float128_t*); +void extF80M_roundToInt(const extFloat80_t*, uint_fast8_t, bool, extFloat80_t*); +void extF80M_add(const extFloat80_t*, const extFloat80_t*, extFloat80_t*); +void extF80M_sub(const extFloat80_t*, const extFloat80_t*, extFloat80_t*); +void extF80M_mul(const extFloat80_t*, const extFloat80_t*, extFloat80_t*); +void extF80M_div(const extFloat80_t*, const extFloat80_t*, extFloat80_t*); +void extF80M_rem(const extFloat80_t*, const extFloat80_t*, extFloat80_t*); +void extF80M_sqrt(const extFloat80_t*, extFloat80_t*); +bool extF80M_eq(const extFloat80_t*, const extFloat80_t*); +bool extF80M_le(const extFloat80_t*, const extFloat80_t*); +bool extF80M_lt(const extFloat80_t*, const extFloat80_t*); +bool extF80M_eq_signaling(const extFloat80_t*, const extFloat80_t*); +bool extF80M_le_quiet(const extFloat80_t*, const extFloat80_t*); +bool extF80M_lt_quiet(const extFloat80_t*, const extFloat80_t*); +bool extF80M_isSignalingNaN(const extFloat80_t*); /*---------------------------------------------------------------------------- | 128-bit (quadruple-precision) floating-point operations. *----------------------------------------------------------------------------*/ #ifdef SOFTFLOAT_FAST_INT64 -uint_fast32_t f128_to_ui32( float128_t, uint_fast8_t, bool ); -uint_fast64_t f128_to_ui64( float128_t, uint_fast8_t, bool ); -int_fast32_t f128_to_i32( float128_t, uint_fast8_t, bool ); -int_fast64_t f128_to_i64( float128_t, uint_fast8_t, bool ); -uint_fast32_t f128_to_ui32_r_minMag( float128_t, bool ); -uint_fast64_t f128_to_ui64_r_minMag( float128_t, bool ); -int_fast32_t f128_to_i32_r_minMag( float128_t, bool ); -int_fast64_t f128_to_i64_r_minMag( float128_t, bool ); -float16_t f128_to_f16( float128_t ); -float32_t f128_to_f32( float128_t ); -float64_t f128_to_f64( float128_t ); -extFloat80_t f128_to_extF80( float128_t ); -float128_t f128_roundToInt( float128_t, uint_fast8_t, bool ); -float128_t f128_add( float128_t, float128_t ); -float128_t f128_sub( float128_t, float128_t ); -float128_t f128_mul( float128_t, float128_t ); -float128_t f128_mulAdd( float128_t, float128_t, float128_t ); -float128_t f128_div( float128_t, float128_t ); -float128_t f128_rem( float128_t, float128_t ); -float128_t f128_sqrt( float128_t ); -bool f128_eq( float128_t, float128_t ); -bool f128_le( float128_t, float128_t ); -bool f128_lt( float128_t, float128_t ); -bool f128_eq_signaling( float128_t, float128_t ); -bool f128_le_quiet( float128_t, float128_t ); -bool f128_lt_quiet( float128_t, float128_t ); -bool f128_isSignalingNaN( float128_t ); +uint_fast32_t f128_to_ui32(float128_t, uint_fast8_t, bool); +uint_fast64_t f128_to_ui64(float128_t, uint_fast8_t, bool); +int_fast32_t f128_to_i32(float128_t, uint_fast8_t, bool); +int_fast64_t f128_to_i64(float128_t, uint_fast8_t, bool); +uint_fast32_t f128_to_ui32_r_minMag(float128_t, bool); +uint_fast64_t f128_to_ui64_r_minMag(float128_t, bool); +int_fast32_t f128_to_i32_r_minMag(float128_t, bool); +int_fast64_t f128_to_i64_r_minMag(float128_t, bool); +float16_t f128_to_f16(float128_t); +float32_t f128_to_f32(float128_t); +float64_t f128_to_f64(float128_t); +extFloat80_t f128_to_extF80(float128_t); +float128_t f128_roundToInt(float128_t, uint_fast8_t, bool); +float128_t f128_add(float128_t, float128_t); +float128_t f128_sub(float128_t, float128_t); +float128_t f128_mul(float128_t, float128_t); +float128_t f128_mulAdd(float128_t, float128_t, float128_t); +float128_t f128_div(float128_t, float128_t); +float128_t f128_rem(float128_t, float128_t); +float128_t f128_sqrt(float128_t); +bool f128_eq(float128_t, float128_t); +bool f128_le(float128_t, float128_t); +bool f128_lt(float128_t, float128_t); +bool f128_eq_signaling(float128_t, float128_t); +bool f128_le_quiet(float128_t, float128_t); +bool f128_lt_quiet(float128_t, float128_t); +bool f128_isSignalingNaN(float128_t); #endif -uint_fast32_t f128M_to_ui32( const float128_t *, uint_fast8_t, bool ); -uint_fast64_t f128M_to_ui64( const float128_t *, uint_fast8_t, bool ); -int_fast32_t f128M_to_i32( const float128_t *, uint_fast8_t, bool ); -int_fast64_t f128M_to_i64( const float128_t *, uint_fast8_t, bool ); -uint_fast32_t f128M_to_ui32_r_minMag( const float128_t *, bool ); -uint_fast64_t f128M_to_ui64_r_minMag( const float128_t *, bool ); -int_fast32_t f128M_to_i32_r_minMag( const float128_t *, bool ); -int_fast64_t f128M_to_i64_r_minMag( const float128_t *, bool ); -float16_t f128M_to_f16( const float128_t * ); -float32_t f128M_to_f32( const float128_t * ); -float64_t f128M_to_f64( const float128_t * ); -void f128M_to_extF80M( const float128_t *, extFloat80_t * ); -void f128M_roundToInt( const float128_t *, uint_fast8_t, bool, float128_t * ); -void f128M_add( const float128_t *, const float128_t *, float128_t * ); -void f128M_sub( const float128_t *, const float128_t *, float128_t * ); -void f128M_mul( const float128_t *, const float128_t *, float128_t * ); -void - f128M_mulAdd( - const float128_t *, const float128_t *, const float128_t *, float128_t * - ); -void f128M_div( const float128_t *, const float128_t *, float128_t * ); -void f128M_rem( const float128_t *, const float128_t *, float128_t * ); -void f128M_sqrt( const float128_t *, float128_t * ); -bool f128M_eq( const float128_t *, const float128_t * ); -bool f128M_le( const float128_t *, const float128_t * ); -bool f128M_lt( const float128_t *, const float128_t * ); -bool f128M_eq_signaling( const float128_t *, const float128_t * ); -bool f128M_le_quiet( const float128_t *, const float128_t * ); -bool f128M_lt_quiet( const float128_t *, const float128_t * ); -bool f128M_isSignalingNaN( const float128_t * ); +uint_fast32_t f128M_to_ui32(const float128_t*, uint_fast8_t, bool); +uint_fast64_t f128M_to_ui64(const float128_t*, uint_fast8_t, bool); +int_fast32_t f128M_to_i32(const float128_t*, uint_fast8_t, bool); +int_fast64_t f128M_to_i64(const float128_t*, uint_fast8_t, bool); +uint_fast32_t f128M_to_ui32_r_minMag(const float128_t*, bool); +uint_fast64_t f128M_to_ui64_r_minMag(const float128_t*, bool); +int_fast32_t f128M_to_i32_r_minMag(const float128_t*, bool); +int_fast64_t f128M_to_i64_r_minMag(const float128_t*, bool); +float16_t f128M_to_f16(const float128_t*); +float32_t f128M_to_f32(const float128_t*); +float64_t f128M_to_f64(const float128_t*); +void f128M_to_extF80M(const float128_t*, extFloat80_t*); +void f128M_roundToInt(const float128_t*, uint_fast8_t, bool, float128_t*); +void f128M_add(const float128_t*, const float128_t*, float128_t*); +void f128M_sub(const float128_t*, const float128_t*, float128_t*); +void f128M_mul(const float128_t*, const float128_t*, float128_t*); +void f128M_mulAdd(const float128_t*, const float128_t*, const float128_t*, float128_t*); +void f128M_div(const float128_t*, const float128_t*, float128_t*); +void f128M_rem(const float128_t*, const float128_t*, float128_t*); +void f128M_sqrt(const float128_t*, float128_t*); +bool f128M_eq(const float128_t*, const float128_t*); +bool f128M_le(const float128_t*, const float128_t*); +bool f128M_lt(const float128_t*, const float128_t*); +bool f128M_eq_signaling(const float128_t*, const float128_t*); +bool f128M_le_quiet(const float128_t*, const float128_t*); +bool f128M_lt_quiet(const float128_t*, const float128_t*); +bool f128M_isSignalingNaN(const float128_t*); #endif - diff --git a/softfloat/source/include/softfloat_types.h b/softfloat/source/include/softfloat_types.h index bc30e31..3fcc9d5 100644 --- a/softfloat/source/include/softfloat_types.h +++ b/softfloat/source/include/softfloat_types.h @@ -47,10 +47,18 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | the types below may, if desired, be defined as aliases for the native types | (typically 'float' and 'double', and possibly 'long double'). *----------------------------------------------------------------------------*/ -typedef struct { uint16_t v; } float16_t; -typedef struct { uint32_t v; } float32_t; -typedef struct { uint64_t v; } float64_t; -typedef struct { uint64_t v[2]; } float128_t; +typedef struct { + uint16_t v; +} float16_t; +typedef struct { + uint32_t v; +} float32_t; +typedef struct { + uint64_t v; +} float64_t; +typedef struct { + uint64_t v[2]; +} float128_t; /*---------------------------------------------------------------------------- | The format of an 80-bit extended floating-point number in memory. This @@ -58,9 +66,15 @@ typedef struct { uint64_t v[2]; } float128_t; | named 'signif'. *----------------------------------------------------------------------------*/ #ifdef LITTLEENDIAN -struct extFloat80M { uint64_t signif; uint16_t signExp; }; +struct extFloat80M { + uint64_t signif; + uint16_t signExp; +}; #else -struct extFloat80M { uint16_t signExp; uint64_t signif; }; +struct extFloat80M { + uint16_t signExp; + uint64_t signif; +}; #endif /*---------------------------------------------------------------------------- @@ -78,4 +92,3 @@ struct extFloat80M { uint16_t signExp; uint64_t signif; }; typedef struct extFloat80M extFloat80_t; #endif - diff --git a/src/iss/arch/hwl.h b/src/iss/arch/hwl.h index 80f0798..c0b5185 100644 --- a/src/iss/arch/hwl.h +++ b/src/iss/arch/hwl.h @@ -50,45 +50,67 @@ public: virtual ~hwl() = default; protected: - iss::status read_custom_csr_reg(unsigned addr, reg_t &val) override; + iss::status read_custom_csr_reg(unsigned addr, reg_t& val) override; iss::status write_custom_csr_reg(unsigned addr, reg_t val) override; }; - -template -inline hwl::hwl(feature_config cfg): BASE(cfg) { - for (unsigned addr = 0x800; addr < 0x803; ++addr){ +template +inline hwl::hwl(feature_config cfg) +: BASE(cfg) { + for(unsigned addr = 0x800; addr < 0x803; ++addr) { this->register_custom_csr_rd(addr); this->register_custom_csr_wr(addr); } - for (unsigned addr = 0x804; addr < 0x807; ++addr){ + for(unsigned addr = 0x804; addr < 0x807; ++addr) { this->register_custom_csr_rd(addr); this->register_custom_csr_wr(addr); } } -template -inline iss::status iss::arch::hwl::read_custom_csr_reg(unsigned addr, reg_t &val) { - switch(addr){ - case 0x800: val = this->reg.lpstart0; break; - case 0x801: val = this->reg.lpend0; break; - case 0x802: val = this->reg.lpcount0; break; - case 0x804: val = this->reg.lpstart1; break; - case 0x805: val = this->reg.lpend1; break; - case 0x806: val = this->reg.lpcount1; break; +template inline iss::status iss::arch::hwl::read_custom_csr_reg(unsigned addr, reg_t& val) { + switch(addr) { + case 0x800: + val = this->reg.lpstart0; + break; + case 0x801: + val = this->reg.lpend0; + break; + case 0x802: + val = this->reg.lpcount0; + break; + case 0x804: + val = this->reg.lpstart1; + break; + case 0x805: + val = this->reg.lpend1; + break; + case 0x806: + val = this->reg.lpcount1; + break; } return iss::Ok; } -template -inline iss::status iss::arch::hwl::write_custom_csr_reg(unsigned addr, reg_t val) { - switch(addr){ - case 0x800: this->reg.lpstart0 = val; break; - case 0x801: this->reg.lpend0 = val; break; - case 0x802: this->reg.lpcount0 = val; break; - case 0x804: this->reg.lpstart1 = val; break; - case 0x805: this->reg.lpend1 = val; break; - case 0x806: this->reg.lpcount1 = val; break; +template inline iss::status iss::arch::hwl::write_custom_csr_reg(unsigned addr, reg_t val) { + switch(addr) { + case 0x800: + this->reg.lpstart0 = val; + break; + case 0x801: + this->reg.lpend0 = val; + break; + case 0x802: + this->reg.lpcount0 = val; + break; + case 0x804: + this->reg.lpstart1 = val; + break; + case 0x805: + this->reg.lpend1 = val; + break; + case 0x806: + this->reg.lpcount1 = val; + break; } return iss::Ok; } @@ -96,5 +118,4 @@ inline iss::status iss::arch::hwl::write_custom_csr_reg(unsigned addr, reg } // namespace arch } // namespace iss - #endif /* _RISCV_HART_M_P_H */ diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h index 4125297..4ac086d 100644 --- a/src/iss/arch/riscv_hart_common.h +++ b/src/iss/arch/riscv_hart_common.h @@ -43,7 +43,7 @@ namespace arch { enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 }; -enum features_e{FEAT_NONE, FEAT_PMP=1, FEAT_EXT_N=2, FEAT_CLIC=4, FEAT_DEBUG=8, FEAT_TCM=16}; +enum features_e { FEAT_NONE, FEAT_PMP = 1, FEAT_EXT_N = 2, FEAT_CLIC = 4, FEAT_DEBUG = 8, FEAT_TCM = 16 }; enum riscv_csr { /* user-level CSR */ @@ -51,17 +51,17 @@ enum riscv_csr { ustatus = 0x000, uie = 0x004, utvec = 0x005, - utvt = 0x007, //CLIC + utvt = 0x007, // CLIC // User Trap Handling uscratch = 0x040, uepc = 0x041, ucause = 0x042, utval = 0x043, uip = 0x044, - uxnti = 0x045, //CLIC - uintstatus = 0xCB1, // MRW Current interrupt levels (CLIC) - addr subject to change - uintthresh = 0x047, // MRW Interrupt-level threshold (CLIC) - addr subject to change - uscratchcsw = 0x048, // MRW Conditional scratch swap on priv mode change (CLIC) + uxnti = 0x045, // CLIC + uintstatus = 0xCB1, // MRW Current interrupt levels (CLIC) - addr subject to change + uintthresh = 0x047, // MRW Interrupt-level threshold (CLIC) - addr subject to change + uscratchcsw = 0x048, // MRW Conditional scratch swap on priv mode change (CLIC) uscratchcswl = 0x049, // MRW Conditional scratch swap on level change (CLIC) // User Floating-Point CSRs fflags = 0x001, @@ -112,17 +112,17 @@ enum riscv_csr { mie = 0x304, mtvec = 0x305, mcounteren = 0x306, - mtvt = 0x307, //CLIC + mtvt = 0x307, // CLIC // Machine Trap Handling mscratch = 0x340, mepc = 0x341, mcause = 0x342, mtval = 0x343, mip = 0x344, - mxnti = 0x345, //CLIC - mintstatus = 0xFB1, // MRW Current interrupt levels (CLIC) - addr subject to change - mintthresh = 0x347, // MRW Interrupt-level threshold (CLIC) - addr subject to change - mscratchcsw = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC) + mxnti = 0x345, // CLIC + mintstatus = 0xFB1, // MRW Current interrupt levels (CLIC) - addr subject to change + mintthresh = 0x347, // MRW Interrupt-level threshold (CLIC) - addr subject to change + mscratchcsw = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC) mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC) // Physical Memory Protection pmpcfg0 = 0x3A0, @@ -175,7 +175,6 @@ enum riscv_csr { dscratch1 = 0x7B3 }; - enum { PGSHIFT = 12, PTE_PPN_SHIFT = 10, @@ -193,7 +192,7 @@ enum { template inline bool PTE_TABLE(T PTE) { return (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V); } -enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4}; +enum { PRIV_U = 0, PRIV_S = 1, PRIV_M = 3, PRIV_D = 4 }; enum { ISA_A = 1, @@ -256,49 +255,49 @@ public: : trap_access(15 << 16, badaddr) {} }; -inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t *const data, unsigned length) { +inline void read_reg_uint32(uint64_t offs, uint32_t& reg, uint8_t* const data, unsigned length) { auto reg_ptr = reinterpret_cast(®); - switch (offs & 0x3) { + switch(offs & 0x3) { case 0: - for (auto i = 0U; i < length; ++i) + for(auto i = 0U; i < length; ++i) *(data + i) = *(reg_ptr + i); - break; + break; case 1: - for (auto i = 0U; i < length; ++i) + for(auto i = 0U; i < length; ++i) *(data + i) = *(reg_ptr + 1 + i); - break; + break; case 2: - for (auto i = 0U; i < length; ++i) + for(auto i = 0U; i < length; ++i) *(data + i) = *(reg_ptr + 2 + i); - break; + break; case 3: *data = *(reg_ptr + 3); - break; + break; } } -inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t *const data, unsigned length) { +inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t* const data, unsigned length) { auto reg_ptr = reinterpret_cast(®); - switch (offs & 0x3) { + switch(offs & 0x3) { case 0: - for (auto i = 0U; i < length; ++i) + for(auto i = 0U; i < length; ++i) *(reg_ptr + i) = *(data + i); - break; + break; case 1: - for (auto i = 0U; i < length; ++i) + for(auto i = 0U; i < length; ++i) *(reg_ptr + 1 + i) = *(data + i); - break; + break; case 2: - for (auto i = 0U; i < length; ++i) + for(auto i = 0U; i < length; ++i) *(reg_ptr + 2 + i) = *(data + i); - break; + break; case 3: - *(reg_ptr + 3) = *data ; - break; + *(reg_ptr + 3) = *data; + break; } } -} -} +} // namespace arch +} // namespace iss #endif diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 26e327d..0109ecc 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -35,22 +35,22 @@ #ifndef _RISCV_HART_M_P_H #define _RISCV_HART_M_P_H -#include "riscv_hart_common.h" #include "iss/arch/traits.h" #include "iss/instrumentation_if.h" #include "iss/log_categories.h" #include "iss/vm_if.h" +#include "riscv_hart_common.h" #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif #include #include #include +#include #include #include #include #include -#include #include #include #include @@ -66,30 +66,31 @@ namespace iss { namespace arch { -template class riscv_hart_m_p : public BASE { +template class riscv_hart_m_p : public BASE { protected: const std::array lvl = {{'U', 'S', 'H', 'M'}}; - const std::array trap_str = {{"" - "Instruction address misaligned", // 0 - "Instruction access fault", // 1 - "Illegal instruction", // 2 - "Breakpoint", // 3 - "Load address misaligned", // 4 - "Load access fault", // 5 - "Store/AMO address misaligned", // 6 - "Store/AMO access fault", // 7 - "Environment call from U-mode", // 8 - "Environment call from S-mode", // 9 - "Reserved", // a - "Environment call from M-mode", // b - "Instruction page fault", // c - "Load page fault", // d - "Reserved", // e - "Store/AMO page fault"}}; - const std::array irq_str = { - {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt", - "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt", - "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; + const std::array trap_str = {{"" + "Instruction address misaligned", // 0 + "Instruction access fault", // 1 + "Illegal instruction", // 2 + "Breakpoint", // 3 + "Load address misaligned", // 4 + "Load access fault", // 5 + "Store/AMO address misaligned", // 6 + "Store/AMO access fault", // 7 + "Environment call from U-mode", // 8 + "Environment call from S-mode", // 9 + "Reserved", // a + "Environment call from M-mode", // b + "Instruction page fault", // c + "Load page fault", // d + "Reserved", // e + "Store/AMO page fault"}}; + const std::array irq_str = {{"User software interrupt", "Supervisor software interrupt", "Reserved", + "Machine software interrupt", "User timer interrupt", "Supervisor timer interrupt", + "Reserved", "Machine timer interrupt", "User external interrupt", + "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; + public: using core = BASE; using this_class = riscv_hart_m_p; @@ -97,10 +98,10 @@ public: using reg_t = typename core::reg_t; using addr_t = typename core::addr_t; - using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &); - using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t); - using mem_read_f = iss::status(phys_addr_t addr, unsigned, uint8_t *const); - using mem_write_f = iss::status(phys_addr_t addr, unsigned, uint8_t const *const); + using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t&); + using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t); + using mem_read_f = iss::status(phys_addr_t addr, unsigned, uint8_t* const); + using mem_write_f = iss::status(phys_addr_t addr, unsigned, uint8_t const* const); // primary template template struct hart_state {}; @@ -108,7 +109,8 @@ public: template class hart_state::value>::type> { public: BEGIN_BF_DECL(mstatus_t, T); - // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11))) + // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR + // XS==11))) BF_FIELD(SD, 31, 1); // Trap SRET BF_FIELD(TSR, 22, 1); @@ -122,7 +124,8 @@ public: BF_FIELD(SUM, 18, 1); // Modify PRiVilege BF_FIELD(MPRV, 17, 1); - // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty + // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None + // dirty, some clean/Some dirty BF_FIELD(XS, 15, 2); // floating-point unit status Off/Initial/Clean/Dirty BF_FIELD(FS, 13, 2); @@ -149,13 +152,13 @@ public: static const reg_t mstatus_reset_val = 0x1800; void write_mstatus(T val) { - auto mask = get_mask() &0xff; // MPP is hardcode as 0x3 + auto mask = get_mask() & 0xff; // MPP is hardcode as 0x3 auto new_val = (mstatus.backing.val & ~mask) | (val & mask); mstatus = new_val; } static constexpr uint32_t get_mask() { - //return 0x807ff988UL; // 0b1000 0000 0111 1111 1111 1000 1000 1000 // only machine mode is supported + // return 0x807ff988UL; // 0b1000 0000 0111 1111 1111 1000 1000 1000 // only machine mode is supported // +-SD // | +-TSR // | |+-TW @@ -177,7 +180,8 @@ public: template class hart_state::value>::type> { public: BEGIN_BF_DECL(mstatus_t, T); - // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11))) + // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR + // XS==11))) BF_FIELD(SD, 63, 1); // value of XLEN for S-mode BF_FIELD(SXL, 34, 2); @@ -195,7 +199,8 @@ public: BF_FIELD(SUM, 18, 1); // Modify PRiVilege BF_FIELD(MPRV, 17, 1); - // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty + // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None + // dirty, some clean/Some dirty BF_FIELD(XS, 15, 2); // floating-point unit status Off/Initial/Clean/Dirty BF_FIELD(FS, 13, 2); @@ -222,13 +227,13 @@ public: static const reg_t mstatus_reset_val = 0x1800; void write_mstatus(T val) { - auto mask = get_mask() &0xff; // MPP is hardcode as 0x3 + auto mask = get_mask() & 0xff; // MPP is hardcode as 0x3 auto new_val = (mstatus.backing.val & ~mask) | (val & mask); mstatus = new_val; } static constexpr T get_mask() { - //return 0x8000000f007ff9ddULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011 + // return 0x8000000f007ff9ddULL; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011 // // +-TSR // |+-TW @@ -252,12 +257,8 @@ public: return 0b100010001000; // only machine mode is supported } - constexpr bool has_compressed() { - return traits::MISA_VAL&0b0100; - } - constexpr reg_t get_pc_mask() { - return has_compressed()?(reg_t)~1:(reg_t)~3; - } + constexpr bool has_compressed() { return traits::MISA_VAL & 0b0100; } + constexpr reg_t get_pc_mask() { return has_compressed() ? (reg_t)~1 : (reg_t)~3; } riscv_hart_m_p(feature_config cfg = feature_config{}); virtual ~riscv_hart_m_p() = default; @@ -266,36 +267,33 @@ public: std::pair load_file(std::string name, int type = -1) override; - iss::status read(const address_type type, const access_type access, const uint32_t space, - const uint64_t addr, const unsigned length, uint8_t *const data) override; - iss::status write(const address_type type, const access_type access, const uint32_t space, - const uint64_t addr, const unsigned length, const uint8_t *const data) override; + iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, + uint8_t* const data) override; + iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, + const uint8_t* const data) override; uint64_t enter_trap(uint64_t flags) override { return riscv_hart_m_p::enter_trap(flags, fault_data, fault_data); } uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override; uint64_t leave_trap(uint64_t flags) override; - const reg_t& get_mhartid() const { return mhartid_reg; } - void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; }; + const reg_t& get_mhartid() const { return mhartid_reg; } + void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; }; void disass_output(uint64_t pc, const std::string instr) override { - CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [s:0x{:x};c:{}]", - pc, instr, (reg_t)state.mstatus, this->reg.icount + cycle_offset); + CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [s:0x{:x};c:{}]", pc, instr, (reg_t)state.mstatus, + this->reg.icount + cycle_offset); }; - iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; } + iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; } - void set_csr(unsigned addr, reg_t val){ - csr[addr & csr.page_addr_mask] = val; - } + void set_csr(unsigned addr, reg_t val) { csr[addr & csr.page_addr_mask] = val; } + + void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); } - void set_irq_num(unsigned i) { - mcause_max_irq=1< &arch) + riscv_instrumentation_if(riscv_hart_m_p& arch) : arch(arch) {} /** * get the name of this architecture @@ -320,20 +318,20 @@ protected: bool is_branch_taken() override { return arch.reg.last_branch; } - unsigned get_reg_num() override {return traits::NUM_REGS;} + unsigned get_reg_num() override { return traits::NUM_REGS; } - riscv_hart_m_p &arch; + riscv_hart_m_p& arch; }; friend struct riscv_instrumentation_if; - virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data); - virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data); + virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t* const data); + virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t* const data); - iss::status read_clic(uint64_t addr, unsigned length, uint8_t *const data); - iss::status write_clic(uint64_t addr, unsigned length, const uint8_t *const data); + iss::status read_clic(uint64_t addr, unsigned length, uint8_t* const data); + iss::status write_clic(uint64_t addr, unsigned length, const uint8_t* const data); - virtual iss::status read_csr(unsigned addr, reg_t &val); + virtual iss::status read_csr(unsigned addr, reg_t& val); virtual iss::status write_csr(unsigned addr, reg_t val); hart_state_type state; @@ -360,7 +358,7 @@ protected: uint8_t clic_cfg_reg{0}; std::array clic_inttrig_reg; union clic_int_reg_t { - struct{ + struct { uint8_t ip; uint8_t ie; uint8_t attr; @@ -374,43 +372,39 @@ protected: std::vector tcm; - iss::status read_csr_reg(unsigned addr, reg_t &val); + iss::status read_csr_reg(unsigned addr, reg_t& val); iss::status write_csr_reg(unsigned addr, reg_t val); - iss::status read_null(unsigned addr, reg_t &val); - iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;} - iss::status read_cycle(unsigned addr, reg_t &val); + iss::status read_null(unsigned addr, reg_t& val); + iss::status write_null(unsigned addr, reg_t val) { return iss::status::Ok; } + iss::status read_cycle(unsigned addr, reg_t& val); iss::status write_cycle(unsigned addr, reg_t val); - iss::status read_instret(unsigned addr, reg_t &val); + iss::status read_instret(unsigned addr, reg_t& val); iss::status write_instret(unsigned addr, reg_t val); - iss::status read_tvec(unsigned addr, reg_t &val); - iss::status read_time(unsigned addr, reg_t &val); - iss::status read_status(unsigned addr, reg_t &val); + iss::status read_tvec(unsigned addr, reg_t& val); + iss::status read_time(unsigned addr, reg_t& val); + iss::status read_status(unsigned addr, reg_t& val); iss::status write_status(unsigned addr, reg_t val); - iss::status read_cause(unsigned addr, reg_t &val); + iss::status read_cause(unsigned addr, reg_t& val); iss::status write_cause(unsigned addr, reg_t val); - iss::status read_ie(unsigned addr, reg_t &val); + iss::status read_ie(unsigned addr, reg_t& val); iss::status write_ie(unsigned addr, reg_t val); - iss::status read_ip(unsigned addr, reg_t &val); - iss::status read_hartid(unsigned addr, reg_t &val); + iss::status read_ip(unsigned addr, reg_t& val); + iss::status read_hartid(unsigned addr, reg_t& val); iss::status write_epc(unsigned addr, reg_t val); iss::status read_intstatus(unsigned addr, reg_t& val); iss::status write_intthresh(unsigned addr, reg_t val); iss::status write_xtvt(unsigned addr, reg_t val); iss::status write_dcsr_dcsr(unsigned addr, reg_t val); - iss::status read_dcsr_reg(unsigned addr, reg_t &val); + iss::status read_dcsr_reg(unsigned addr, reg_t& val); iss::status write_dcsr_reg(unsigned addr, reg_t val); - iss::status read_dpc_reg(unsigned addr, reg_t &val); + iss::status read_dpc_reg(unsigned addr, reg_t& val); iss::status write_dpc_reg(unsigned addr, reg_t val); - virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;}; - virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;}; + virtual iss::status read_custom_csr_reg(unsigned addr, reg_t& val) { return iss::status::Err; }; + virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) { return iss::status::Err; }; - void register_custom_csr_rd(unsigned addr){ - csr_rd_cb[addr] = &this_class::read_custom_csr_reg; - } - void register_custom_csr_wr(unsigned addr){ - csr_wr_cb[addr] = &this_class::write_custom_csr_reg; - } + void register_custom_csr_rd(unsigned addr) { csr_rd_cb[addr] = &this_class::read_custom_csr_reg; } + void register_custom_csr_wr(unsigned addr) { csr_wr_cb[addr] = &this_class::write_custom_csr_reg; } reg_t mhartid_reg{0x0}; @@ -421,10 +415,10 @@ protected: std::vector> memfn_write; void insert_mem_range(uint64_t, uint64_t, std::function, std::function); feature_config cfg; - uint64_t mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16}; - inline bool debug_mode_active() {return this->reg.PRIV&0x4;} - std::pair, std::function> - replace_mem_access(std::function rd, std::function wr){ + uint64_t mcause_max_irq{(FEAT & features_e::FEAT_CLIC) ? 4096 : 16}; + inline bool debug_mode_active() { return this->reg.PRIV & 0x4; } + std::pair, std::function> replace_mem_access(std::function rd, + std::function wr) { std::pair, std::function> ret{hart_mem_rd_delegate, hart_mem_wr_delegate}; hart_mem_rd_delegate = rd; hart_mem_wr_delegate = wr; @@ -446,52 +440,61 @@ riscv_hart_m_p::riscv_hart_m_p(feature_config cfg) csr[mimpid] = 1; uart_buf.str(""); - for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){ + for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) { csr_rd_cb[addr] = &this_class::read_null; csr_wr_cb[addr] = &this_class::write_csr_reg; } - if(traits::XLEN==32) for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){ + if(traits::XLEN == 32) + for(unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr) { + csr_rd_cb[addr] = &this_class::read_null; + csr_wr_cb[addr] = &this_class::write_csr_reg; + } + for(unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr) { csr_rd_cb[addr] = &this_class::read_null; csr_wr_cb[addr] = &this_class::write_csr_reg; } - for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){ - csr_rd_cb[addr] = &this_class::read_null; - csr_wr_cb[addr] = &this_class::write_csr_reg; - } - for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){ + for(unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr) { csr_rd_cb[addr] = &this_class::read_null; } - if(traits::XLEN==32) for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){ - csr_rd_cb[addr] = &this_class::read_null; - //csr_wr_cb[addr] = &this_class::write_csr_reg; - } + if(traits::XLEN == 32) + for(unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr) { + csr_rd_cb[addr] = &this_class::read_null; + // csr_wr_cb[addr] = &this_class::write_csr_reg; + } // common regs const std::array roaddrs{{misa, mvendorid, marchid, mimpid}}; - for(auto addr: roaddrs) { + for(auto addr : roaddrs) { csr_rd_cb[addr] = &this_class::read_csr_reg; csr_wr_cb[addr] = &this_class::write_null; } const std::array rwaddrs{{mepc, mtvec, mscratch, mtval}}; - for(auto addr: rwaddrs) { + for(auto addr : rwaddrs) { csr_rd_cb[addr] = &this_class::read_csr_reg; csr_wr_cb[addr] = &this_class::write_csr_reg; } // special handling & overrides csr_rd_cb[time] = &this_class::read_time; - if(traits::XLEN==32) csr_rd_cb[timeh] = &this_class::read_time; + if(traits::XLEN == 32) + csr_rd_cb[timeh] = &this_class::read_time; csr_rd_cb[cycle] = &this_class::read_cycle; - if(traits::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle; + if(traits::XLEN == 32) + csr_rd_cb[cycleh] = &this_class::read_cycle; csr_rd_cb[instret] = &this_class::read_instret; - if(traits::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret; + if(traits::XLEN == 32) + csr_rd_cb[instreth] = &this_class::read_instret; csr_rd_cb[mcycle] = &this_class::read_cycle; csr_wr_cb[mcycle] = &this_class::write_cycle; - if(traits::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle; - if(traits::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle; + if(traits::XLEN == 32) + csr_rd_cb[mcycleh] = &this_class::read_cycle; + if(traits::XLEN == 32) + csr_wr_cb[mcycleh] = &this_class::write_cycle; csr_rd_cb[minstret] = &this_class::read_instret; csr_wr_cb[minstret] = &this_class::write_instret; - if(traits::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret; - if(traits::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret; + if(traits::XLEN == 32) + csr_rd_cb[minstreth] = &this_class::read_instret; + if(traits::XLEN == 32) + csr_wr_cb[minstreth] = &this_class::write_instret; csr_rd_cb[mstatus] = &this_class::read_status; csr_wr_cb[mstatus] = &this_class::write_status; csr_rd_cb[mcause] = &this_class::read_cause; @@ -510,39 +513,40 @@ riscv_hart_m_p::riscv_hart_m_p(feature_config cfg) if(FEAT & FEAT_CLIC) { csr_rd_cb[mtvt] = &this_class::read_csr_reg; csr_wr_cb[mtvt] = &this_class::write_xtvt; -// csr_rd_cb[mxnti] = &this_class::read_csr_reg; -// csr_wr_cb[mxnti] = &this_class::write_csr_reg; + // csr_rd_cb[mxnti] = &this_class::read_csr_reg; + // csr_wr_cb[mxnti] = &this_class::write_csr_reg; csr_rd_cb[mintstatus] = &this_class::read_intstatus; csr_wr_cb[mintstatus] = &this_class::write_null; -// csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg; -// csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg; -// csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg; -// csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg; + // csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg; + // csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg; + // csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg; + // csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg; csr_rd_cb[mintthresh] = &this_class::read_csr_reg; csr_wr_cb[mintthresh] = &this_class::write_intthresh; - clic_int_reg.resize(cfg.clic_num_irq, clic_int_reg_t{.raw=0}); - clic_cfg_reg=0x20; - clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1; - csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1; - insert_mem_range(cfg.clic_base, 0x5000UL, - [this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);}, - [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);}); + clic_int_reg.resize(cfg.clic_num_irq, clic_int_reg_t{.raw = 0}); + clic_cfg_reg = 0x20; + clic_mact_lvl = clic_mprev_lvl = (1 << (cfg.clic_int_ctl_bits)) - 1; + csr[mintthresh] = (1 << (cfg.clic_int_ctl_bits)) - 1; + insert_mem_range( + cfg.clic_base, 0x5000UL, + [this](phys_addr_t addr, unsigned length, uint8_t* const data) { return read_clic(addr.val, length, data); }, + [this](phys_addr_t addr, unsigned length, uint8_t const* const data) { return write_clic(addr.val, length, data); }); } if(FEAT & FEAT_TCM) { tcm.resize(cfg.tcm_size); - std::function read_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t * const data) { - auto offset=addr.val-this->cfg.tcm_base; + std::function read_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t* const data) { + auto offset = addr.val - this->cfg.tcm_base; std::copy(tcm.data() + offset, tcm.data() + offset + length, data); return iss::Ok; }; - std::function write_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t const * const data) { - auto offset=addr.val-this->cfg.tcm_base; + std::function write_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t const* const data) { + auto offset = addr.val - this->cfg.tcm_base; std::copy(data, data + length, tcm.data() + offset); return iss::Ok; }; insert_mem_range(cfg.tcm_base, cfg.tcm_size, read_clic_cb, write_clic_cb); } - if(FEAT & FEAT_DEBUG){ + if(FEAT & FEAT_DEBUG) { csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg; csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg; csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg; @@ -552,158 +556,158 @@ riscv_hart_m_p::riscv_hart_m_p(feature_config cfg) csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr; csr_rd_cb[dcsr] = &this_class::read_dcsr_reg; } - hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { - return this->read_mem(a, l, d); - }; - hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { - return this->write_mem(a, l, d); - }; + hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return this->read_mem(a, l, d); }; + hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return this->write_mem(a, l, d); }; } template std::pair riscv_hart_m_p::load_file(std::string name, int type) { - FILE *fp = fopen(name.c_str(), "r"); - if (fp) { + FILE* fp = fopen(name.c_str(), "r"); + if(fp) { std::array buf; auto n = fread(buf.data(), 1, 4, fp); fclose(fp); - if (n != 4) throw std::runtime_error("input file has insufficient size"); + if(n != 4) + throw std::runtime_error("input file has insufficient size"); buf[4] = 0; - if (strcmp(buf.data() + 1, "ELF") == 0) { + if(strcmp(buf.data() + 1, "ELF") == 0) { // Create elfio reader ELFIO::elfio reader; // Load ELF data - if (!reader.load(name)) throw std::runtime_error("could not process elf file"); + if(!reader.load(name)) + throw std::runtime_error("could not process elf file"); // check elf properties - if (reader.get_class() != ELFCLASS32) - if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file"); - if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file"); - if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file"); + if(reader.get_class() != ELFCLASS32) + if(sizeof(reg_t) == 4) + throw std::runtime_error("wrong elf class in file"); + if(reader.get_type() != ET_EXEC) + throw std::runtime_error("wrong elf type in file"); + if(reader.get_machine() != EM_RISCV) + throw std::runtime_error("wrong elf machine in file"); auto entry = reader.get_entry(); - for (const auto pseg : reader.segments) { + for(const auto pseg : reader.segments) { const auto fsize = pseg->get_file_size(); // 0x42c/0x0 const auto seg_data = pseg->get_data(); - if (fsize > 0) { - auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, - traits::MEM, pseg->get_physical_address(), - fsize, reinterpret_cast(seg_data)); - if (res != iss::Ok) - LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex - << pseg->get_physical_address(); + if(fsize > 0) { + auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits::MEM, + pseg->get_physical_address(), fsize, reinterpret_cast(seg_data)); + if(res != iss::Ok) + LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); } } for(const auto sec : reader.sections) { if(sec->get_name() == ".symtab") { - if ( SHT_SYMTAB == sec->get_type() || - SHT_DYNSYM == sec->get_type() ) { - ELFIO::symbol_section_accessor symbols( reader, sec ); + if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) { + ELFIO::symbol_section_accessor symbols(reader, sec); auto sym_no = symbols.get_symbols_num(); - std::string name; - ELFIO::Elf64_Addr value = 0; - ELFIO::Elf_Xword size = 0; - unsigned char bind = 0; - unsigned char type = 0; - ELFIO::Elf_Half section = 0; - unsigned char other = 0; - for ( auto i = 0U; i < sym_no; ++i ) { - symbols.get_symbol( i, name, value, size, bind, type, section, other ); - if(name=="tohost") { + std::string name; + ELFIO::Elf64_Addr value = 0; + ELFIO::Elf_Xword size = 0; + unsigned char bind = 0; + unsigned char type = 0; + ELFIO::Elf_Half section = 0; + unsigned char other = 0; + for(auto i = 0U; i < sym_no; ++i) { + symbols.get_symbol(i, name, value, size, bind, type, section, other); + if(name == "tohost") { tohost = value; - } else if(name=="fromhost") { + } else if(name == "fromhost") { fromhost = value; } } } - } else if (sec->get_name() == ".tohost") { + } else if(sec->get_name() == ".tohost") { tohost = sec->get_address(); fromhost = tohost + 0x40; } - } return std::make_pair(entry, true); } - throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name)); + throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name)); } throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name)); } -template +template inline void riscv_hart_m_p::insert_mem_range(uint64_t base, uint64_t size, std::function rd_f, - std::function wr_fn) { + std::function wr_fn) { std::tuple entry{base, size}; - auto it = std::upper_bound( memfn_range.begin(), memfn_range.end(), entry, - [](std::tuple const& a, std::tuple const& b){ - return std::get<0>(a)(b); - }); + auto it = std::upper_bound( + memfn_range.begin(), memfn_range.end(), entry, + [](std::tuple const& a, std::tuple const& b) { return std::get<0>(a) < std::get<0>(b); }); auto idx = std::distance(memfn_range.begin(), it); memfn_range.insert(it, entry); - memfn_read.insert(std::begin(memfn_read)+idx, rd_f); - memfn_write.insert(std::begin(memfn_write)+idx, wr_fn); + memfn_read.insert(std::begin(memfn_read) + idx, rd_f); + memfn_write.insert(std::begin(memfn_write) + idx, wr_fn); } template -iss::status riscv_hart_m_p::read(const address_type type, const access_type access, const uint32_t space, - const uint64_t addr, const unsigned length, uint8_t *const data) { +iss::status riscv_hart_m_p::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, + const unsigned length, uint8_t* const data) { #ifndef NDEBUG - if (access && iss::access_type::DEBUG) { + if(access && iss::access_type::DEBUG) { LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; - } else if(access && iss::access_type::FETCH){ + } else if(access && iss::access_type::FETCH) { LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; } else { LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; - } + } #endif try { - switch (space) { + switch(space) { case traits::MEM: { - auto alignment = is_fetch(access)? (has_compressed()? 2 : 4) : length; - if (unlikely(is_fetch(access) && (addr&(alignment-1)))) { + auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : length; + if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) { fault_data = addr; - if (is_debug(access)) throw trap_access(0, addr); + if(is_debug(access)) + throw trap_access(0, addr); this->reg.trap_state = (1UL << 31); // issue trap 0 return iss::Err; } try { - if(!is_debug(access) && (addr&(alignment-1))){ - this->reg.trap_state = (1UL << 31) | 4<<16; - fault_data=addr; + if(!is_debug(access) && (addr & (alignment - 1))) { + this->reg.trap_state = (1UL << 31) | 4 << 16; + fault_data = addr; return iss::Err; } phys_addr_t phys_addr{access, space, addr}; auto res = iss::Err; - if(access != access_type::FETCH && memfn_range.size()){ - auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple const& a){ - return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val; - }); - if(it!=std::end(memfn_range)) { + if(access != access_type::FETCH && memfn_range.size()) { + auto it = + std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple const& a) { + return std::get<0>(a) <= phys_addr.val && (std::get<0>(a) + std::get<1>(a)) > phys_addr.val; + }); + if(it != std::end(memfn_range)) { auto idx = std::distance(std::begin(memfn_range), it); res = memfn_read[idx](phys_addr, length, data); } else - res = hart_mem_rd_delegate( phys_addr, length, data); + res = hart_mem_rd_delegate(phys_addr, length, data); } else { - res = hart_mem_rd_delegate( phys_addr, length, data); + res = hart_mem_rd_delegate(phys_addr, length, data); } - if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)){ + if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) { this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault - fault_data=addr; + fault_data = addr; } return res; - } catch (trap_access &ta) { + } catch(trap_access& ta) { this->reg.trap_state = (1UL << 31) | ta.id; - fault_data=ta.addr; + fault_data = ta.addr; return iss::Err; } } break; case traits::CSR: { - if (length != sizeof(reg_t)) return iss::Err; - return read_csr(addr, *reinterpret_cast(data)); + if(length != sizeof(reg_t)) + return iss::Err; + return read_csr(addr, *reinterpret_cast(data)); } break; case traits::FENCE: { - if ((addr + length) > mem.size()) return iss::Err; + if((addr + length) > mem.size()) + return iss::Err; return iss::Ok; } break; case traits::RES: { auto it = atomic_reservation.find(addr); - if (it != atomic_reservation.end() && it->second != 0) { + if(it != atomic_reservation.end() && it->second != 0) { memset(data, 0xff, length); atomic_reservation.erase(addr); } else @@ -713,85 +717,88 @@ iss::status riscv_hart_m_p::read(const address_type type, const acce return iss::Err; // assert("Not supported"); } return iss::Ok; - } catch (trap_access &ta) { + } catch(trap_access& ta) { this->reg.trap_state = (1UL << 31) | ta.id; - fault_data=ta.addr; + fault_data = ta.addr; return iss::Err; } } template -iss::status riscv_hart_m_p::write(const address_type type, const access_type access, const uint32_t space, - const uint64_t addr, const unsigned length, const uint8_t *const data) { +iss::status riscv_hart_m_p::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, + const unsigned length, const uint8_t* const data) { #ifndef NDEBUG - const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; - switch (length) { + const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; + switch(length) { case 8: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec - << ") @addr 0x" << std::hex << addr; + LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" + << std::hex << addr; break; case 4: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec - << ") @addr 0x" << std::hex << addr; + LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" + << std::hex << addr; break; case 2: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec - << ") @addr 0x" << std::hex << addr; + LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" + << std::hex << addr; break; case 1: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec - << ") @addr 0x" << std::hex << addr; + LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" + << std::hex << addr; break; default: LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; } #endif try { - switch (space) { + switch(space) { case traits::MEM: { - if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) { + if(unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) { fault_data = addr; - if (access && iss::access_type::DEBUG) throw trap_access(0, addr); + if(access && iss::access_type::DEBUG) + throw trap_access(0, addr); this->reg.trap_state = (1UL << 31); // issue trap 0 return iss::Err; } try { - if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){ - this->reg.trap_state = (1UL << 31) | 6<<16; - fault_data=addr; + if(length > 1 && (addr & (length - 1)) && (access & access_type::DEBUG) != access_type::DEBUG) { + this->reg.trap_state = (1UL << 31) | 6 << 16; + fault_data = addr; return iss::Err; } phys_addr_t phys_addr{access, space, addr}; auto res = iss::Err; - if(access != access_type::FETCH && memfn_range.size()){ - auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple const& a){ - return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val; - }); - if(it!=std::end(memfn_range)) { + if(access != access_type::FETCH && memfn_range.size()) { + auto it = + std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple const& a) { + return std::get<0>(a) <= phys_addr.val && (std::get<0>(a) + std::get<1>(a)) > phys_addr.val; + }); + if(it != std::end(memfn_range)) { auto idx = std::distance(std::begin(memfn_range), it); - res = memfn_write[idx]( phys_addr, length, data); + res = memfn_write[idx](phys_addr, length, data); } else - res = write_mem( phys_addr, length, data); + res = write_mem(phys_addr, length, data); } else { - res = write_mem( phys_addr, length, data); + res = write_mem(phys_addr, length, data); } - if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) { + if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) { this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault) - fault_data=addr; + fault_data = addr; } return res; - } catch (trap_access &ta) { + } catch(trap_access& ta) { this->reg.trap_state = (1UL << 31) | ta.id; - fault_data=ta.addr; + fault_data = ta.addr; return iss::Err; } - if ((addr + length) > mem.size()) return iss::Err; - switch (addr) { + if((addr + length) > mem.size()) + return iss::Err; + switch(addr) { case 0x10013000: // UART0 base, TXFIFO reg case 0x10023000: // UART1 base, TXFIFO reg uart_buf << (char)data[0]; - if (((char)data[0]) == '\n' || data[0] == 0) { + if(((char)data[0]) == '\n' || data[0] == 0) { // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send // '"<::write(const address_type type, const acc } return iss::Ok; case 0x10008000: { // HFROSC base, hfrosccfg reg - auto &p = mem(addr / mem.page_size); + auto& p = mem(addr / mem.page_size); auto offs = addr & mem.page_addr_mask; std::copy(data, data + length, p.data() + offs); - auto &x = *(p.data() + offs + 3); - if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1 + auto& x = *(p.data() + offs + 3); + if(x & 0x40) + x |= 0x80; // hfroscrdy = 1 if hfroscen==1 return iss::Ok; } case 0x10008008: { // HFROSC base, pllcfg reg - auto &p = mem(addr / mem.page_size); + auto& p = mem(addr / mem.page_size); auto offs = addr & mem.page_addr_mask; std::copy(data, data + length, p.data() + offs); - auto &x = *(p.data() + offs + 3); + auto& x = *(p.data() + offs + 3); x |= 0x80; // set pll lock upon writing return iss::Ok; } break; @@ -818,12 +826,14 @@ iss::status riscv_hart_m_p::write(const address_type type, const acc } } break; case traits::CSR: { - if (length != sizeof(reg_t)) return iss::Err; - return write_csr(addr, *reinterpret_cast(data)); + if(length != sizeof(reg_t)) + return iss::Err; + return write_csr(addr, *reinterpret_cast(data)); } break; case traits::FENCE: { - if ((addr + length) > mem.size()) return iss::Err; - switch (addr) { + if((addr + length) > mem.size()) + return iss::Err; + switch(addr) { case 2: case 3: { ptw.clear(); @@ -839,43 +849,45 @@ iss::status riscv_hart_m_p::write(const address_type type, const acc return iss::Err; } return iss::Ok; - } catch (trap_access &ta) { + } catch(trap_access& ta) { this->reg.trap_state = (1UL << 31) | ta.id; - fault_data=ta.addr; + fault_data = ta.addr; return iss::Err; } } -template iss::status riscv_hart_m_p::read_csr(unsigned addr, reg_t &val) { - if (addr >= csr.size()) return iss::Err; +template iss::status riscv_hart_m_p::read_csr(unsigned addr, reg_t& val) { + if(addr >= csr.size()) + return iss::Err; auto req_priv_lvl = (addr >> 8) & 0x3; - if (this->reg.PRIV < req_priv_lvl) // not having required privileges + if(this->reg.PRIV < req_priv_lvl) // not having required privileges throw illegal_instruction_fault(this->fault_data); auto it = csr_rd_cb.find(addr); - if (it == csr_rd_cb.end() || !it->second) // non existent register + if(it == csr_rd_cb.end() || !it->second) // non existent register throw illegal_instruction_fault(this->fault_data); return (this->*(it->second))(addr, val); } template iss::status riscv_hart_m_p::write_csr(unsigned addr, reg_t val) { - if (addr >= csr.size()) return iss::Err; + if(addr >= csr.size()) + return iss::Err; auto req_priv_lvl = (addr >> 8) & 0x3; - if (this->reg.PRIV < req_priv_lvl) // not having required privileges + if(this->reg.PRIV < req_priv_lvl) // not having required privileges throw illegal_instruction_fault(this->fault_data); - if((addr&0xc00)==0xc00) // writing to read-only region + if((addr & 0xc00) == 0xc00) // writing to read-only region throw illegal_instruction_fault(this->fault_data); auto it = csr_wr_cb.find(addr); - if (it == csr_wr_cb.end() || !it->second) // non existent register + if(it == csr_wr_cb.end() || !it->second) // non existent register throw illegal_instruction_fault(this->fault_data); return (this->*(it->second))(addr, val); } -template iss::status riscv_hart_m_p::read_csr_reg(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_csr_reg(unsigned addr, reg_t& val) { val = csr[addr]; return iss::Ok; } -template iss::status riscv_hart_m_p::read_null(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_null(unsigned addr, reg_t& val) { val = 0; return iss::Ok; } @@ -885,70 +897,71 @@ template iss::status riscv_hart_m_p return iss::Ok; } -template iss::status riscv_hart_m_p::read_cycle(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_cycle(unsigned addr, reg_t& val) { auto cycle_val = this->reg.icount + cycle_offset; - if (addr == mcycle) { + if(addr == mcycle) { val = static_cast(cycle_val); - } else if (addr == mcycleh) { + } else if(addr == mcycleh) { val = static_cast(cycle_val >> 32); } return iss::Ok; } template iss::status riscv_hart_m_p::write_cycle(unsigned addr, reg_t val) { - if (sizeof(typename traits::reg_t) != 4) { + if(sizeof(typename traits::reg_t) != 4) { mcycle_csr = static_cast(val); } else { - if (addr == mcycle) { + if(addr == mcycle) { mcycle_csr = (mcycle_csr & 0xffffffff00000000) + val; - } else { - mcycle_csr = (static_cast(val)<<32) + (mcycle_csr & 0xffffffff); + } else { + mcycle_csr = (static_cast(val) << 32) + (mcycle_csr & 0xffffffff); } } - cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around + cycle_offset = mcycle_csr - this->reg.icount; // TODO: relying on wrap-around return iss::Ok; } -template iss::status riscv_hart_m_p::read_instret(unsigned addr, reg_t &val) { - if ((addr&0xff) == (minstret&0xff)) { +template iss::status riscv_hart_m_p::read_instret(unsigned addr, reg_t& val) { + if((addr & 0xff) == (minstret & 0xff)) { val = static_cast(this->reg.instret); - } else if ((addr&0xff) == (minstreth&0xff)) { + } else if((addr & 0xff) == (minstreth & 0xff)) { val = static_cast(this->reg.instret >> 32); } return iss::Ok; } template iss::status riscv_hart_m_p::write_instret(unsigned addr, reg_t val) { - if (sizeof(typename traits::reg_t) != 4) { + if(sizeof(typename traits::reg_t) != 4) { this->reg.instret = static_cast(val); } else { - if ((addr&0xff) == (minstret&0xff)) { + if((addr & 0xff) == (minstret & 0xff)) { this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val; - } else { - this->reg.instret = (static_cast(val)<<32) + (this->reg.instret & 0xffffffff); + } else { + this->reg.instret = (static_cast(val) << 32) + (this->reg.instret & 0xffffffff); } } this->reg.instret--; return iss::Ok; } -template iss::status riscv_hart_m_p::read_time(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_time(unsigned addr, reg_t& val) { uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052; - if (addr == time) { + if(addr == time) { val = static_cast(time_val); - } else if (addr == timeh) { - if (sizeof(typename traits::reg_t) != 4) return iss::Err; + } else if(addr == timeh) { + if(sizeof(typename traits::reg_t) != 4) + return iss::Err; val = static_cast(time_val >> 32); } return iss::Ok; } -template iss::status riscv_hart_m_p::read_tvec(unsigned addr, reg_t &val) { - val = FEAT & features_e::FEAT_CLIC? csr[addr] : csr[addr] & ~2; +template iss::status riscv_hart_m_p::read_tvec(unsigned addr, reg_t& val) { + val = FEAT & features_e::FEAT_CLIC ? csr[addr] : csr[addr] & ~2; return iss::Ok; } -template iss::status riscv_hart_m_p::read_status(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_status(unsigned addr, reg_t& val) { val = state.mstatus & hart_state_type::get_mask(); return iss::Ok; } @@ -959,37 +972,37 @@ template iss::status riscv_hart_m_p return iss::Ok; } -template iss::status riscv_hart_m_p::read_cause(unsigned addr, reg_t &val) { - if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) { - val = csr[addr] & ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16)); - val |= clic_mprev_lvl<<16; - val |= state.mstatus.MPIE<<27; - val |= state.mstatus.MPP<<28; +template iss::status riscv_hart_m_p::read_cause(unsigned addr, reg_t& val) { + if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec] & 0x3) == 3) { + val = csr[addr] & ((1UL << (traits::XLEN - 1)) | (mcause_max_irq - 1) | (0xfUL << 16)); + val |= clic_mprev_lvl << 16; + val |= state.mstatus.MPIE << 27; + val |= state.mstatus.MPP << 28; } else - val = csr[addr] & ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1)); + val = csr[addr] & ((1UL << (traits::XLEN - 1)) | (mcause_max_irq - 1)); return iss::Ok; } template iss::status riscv_hart_m_p::write_cause(unsigned addr, reg_t val) { - if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) { - auto mask = ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16)); + if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec] & 0x3) == 3) { + auto mask = ((1UL << (traits::XLEN - 1)) | (mcause_max_irq - 1) | (0xfUL << 16)); csr[addr] = (val & mask) | (csr[addr] & ~mask); - clic_mprev_lvl = ((val>>16)&0xff) | (1<<(8-cfg. clic_int_ctl_bits)) - 1; - state.mstatus.MPIE=(val>>27)&0x1; - state.mstatus.MPP=(val>>28)&0x3; + clic_mprev_lvl = ((val >> 16) & 0xff) | (1 << (8 - cfg.clic_int_ctl_bits)) - 1; + state.mstatus.MPIE = (val >> 27) & 0x1; + state.mstatus.MPP = (val >> 28) & 0x3; } else { - auto mask = ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1)); + auto mask = ((1UL << (traits::XLEN - 1)) | (mcause_max_irq - 1)); csr[addr] = (val & mask) | (csr[addr] & ~mask); } return iss::Ok; } -template iss::status riscv_hart_m_p::read_hartid(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_hartid(unsigned addr, reg_t& val) { val = mhartid_reg; return iss::Ok; } -template iss::status riscv_hart_m_p::read_ie(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_ie(unsigned addr, reg_t& val) { auto mask = get_irq_mask(); val = csr[mie] & mask; return iss::Ok; @@ -1002,7 +1015,7 @@ template iss::status riscv_hart_m_p return iss::Ok; } -template iss::status riscv_hart_m_p::read_ip(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_ip(unsigned addr, reg_t& val) { auto mask = get_irq_mask(); val = csr[mip] & mask; return iss::Ok; @@ -1024,7 +1037,7 @@ template iss::status riscv_hart_m_p return iss::Ok; } -template iss::status riscv_hart_m_p::read_dcsr_reg(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_dcsr_reg(unsigned addr, reg_t& val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); val = csr[addr]; @@ -1038,7 +1051,7 @@ template iss::status riscv_hart_m_p return iss::Ok; } -template iss::status riscv_hart_m_p::read_dpc_reg(unsigned addr, reg_t &val) { +template iss::status riscv_hart_m_p::read_dpc_reg(unsigned addr, reg_t& val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); val = this->reg.DPC; @@ -1052,30 +1065,27 @@ template iss::status riscv_hart_m_p return iss::Ok; } -template -iss::status riscv_hart_m_p::read_intstatus(unsigned addr, reg_t& val) { - val = (clic_mact_lvl&0xff) <<24; +template iss::status riscv_hart_m_p::read_intstatus(unsigned addr, reg_t& val) { + val = (clic_mact_lvl & 0xff) << 24; return iss::Ok; } -template -iss::status riscv_hart_m_p::write_intthresh(unsigned addr, reg_t val) { - csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1; +template iss::status riscv_hart_m_p::write_intthresh(unsigned addr, reg_t val) { + csr[addr] = (val & 0xff) | (1 << (cfg.clic_int_ctl_bits)) - 1; return iss::Ok; } -template -iss::status riscv_hart_m_p::write_xtvt(unsigned addr, reg_t val) { - csr[addr]= val & ~0x3fULL; +template iss::status riscv_hart_m_p::write_xtvt(unsigned addr, reg_t val) { + csr[addr] = val & ~0x3fULL; return iss::Ok; } template -iss::status riscv_hart_m_p::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) { - switch (paddr.val) { +iss::status riscv_hart_m_p::read_mem(phys_addr_t paddr, unsigned length, uint8_t* const data) { + switch(paddr.val) { default: { - for(auto offs=0U; offs::read_mem(phys_addr_t paddr, unsigned len } template -iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) { - switch (paddr.val) { +iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) { + switch(paddr.val) { case 0xFFFF0000: // UART0 base, TXFIFO reg - if (((char)data[0]) == '\n' || data[0] == 0) { - LOG(INFO)<<"UART"<<((paddr.val>>12)&0x3)<<" send '"<> 12) & 0x3) << " send '" << uart_buf.str() << "'"; uart_buf.str(""); } else if(((char)data[0]) != '\r') uart_buf << (char)data[0]; break; default: { - mem_type::page_type &p = mem(paddr.val / mem.page_size); + mem_type::page_type& p = mem(paddr.val / mem.page_size); std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); // tohost handling in case of riscv-test - if (paddr.access && iss::access_type::FUNC) { - auto tohost_upper = (traits::XLEN == 32 && paddr.val == (tohost + 4)) || - (traits::XLEN == 64 && paddr.val == tohost); - auto tohost_lower = - (traits::XLEN == 32 && paddr.val == tohost) || (traits::XLEN == 64 && paddr.val == tohost); - if (tohost_lower || tohost_upper) { - uint64_t hostvar = *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)); - if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) { - switch (hostvar >> 48) { + if(paddr.access && iss::access_type::FUNC) { + auto tohost_upper = + (traits::XLEN == 32 && paddr.val == (tohost + 4)) || (traits::XLEN == 64 && paddr.val == tohost); + auto tohost_lower = (traits::XLEN == 32 && paddr.val == tohost) || (traits::XLEN == 64 && paddr.val == tohost); + if(tohost_lower || tohost_upper) { + uint64_t hostvar = *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)); + if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) { + switch(hostvar >> 48) { case 0: - if (hostvar != 0x1) { + if(hostvar != 0x1) { LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } else { LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } - this->reg.trap_state=std::numeric_limits::max(); - this->interrupt_sim=hostvar; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = hostvar; #ifndef WITH_TCC throw(iss::simulation_stopped(hostvar)); #endif break; case 0x0101: { char c = static_cast(hostvar & 0xff); - if (c == '\n' || c == 0) { + if(c == '\n' || c == 0) { LOG(INFO) << "tohost send '" << uart_buf.str() << "'"; uart_buf.str(""); } else @@ -1131,12 +1140,11 @@ iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned le default: break; } - } else if (tohost_lower) + } else if(tohost_lower) to_host_wr_cnt++; - } else if ((traits::XLEN == 32 && paddr.val == fromhost + 4) || - (traits::XLEN == 64 && paddr.val == fromhost)) { - uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); - *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; + } else if((traits::XLEN == 32 && paddr.val == fromhost + 4) || (traits::XLEN == 64 && paddr.val == fromhost)) { + uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); + *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; } } } @@ -1144,32 +1152,36 @@ iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned le return iss::Ok; } -template -iss::status riscv_hart_m_p::read_clic(uint64_t addr, unsigned length, uint8_t *const data) { - if(addr==cfg.clic_base) { // cliccfg - *data=clic_cfg_reg; - for(auto i=1; i=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig - auto offset = ((addr&0x7fff)-0x40)/4; +template +iss::status riscv_hart_m_p::read_clic(uint64_t addr, unsigned length, uint8_t* const data) { + if(addr == cfg.clic_base) { // cliccfg + *data = clic_cfg_reg; + for(auto i = 1; i < length; ++i) + *(data + i) = 0; + } else if(addr >= (cfg.clic_base + 0x40) && (addr + length) <= (cfg.clic_base + 0x40 + cfg.clic_num_trigger * 4)) { // clicinttrig + auto offset = ((addr & 0x7fff) - 0x40) / 4; read_reg_uint32(addr, clic_inttrig_reg[offset], data, length); - } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl - auto offset = ((addr&0x7fff)-0x1000)/4; + } else if(addr >= (cfg.clic_base + 0x1000) && + (addr + length) <= (cfg.clic_base + 0x1000 + cfg.clic_num_irq * 4)) { // clicintip/clicintie/clicintattr/clicintctl + auto offset = ((addr & 0x7fff) - 0x1000) / 4; read_reg_uint32(addr, clic_int_reg[offset].raw, data, length); } else { - for(auto i = 0U; i -iss::status riscv_hart_m_p::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) { - if(addr==cfg.clic_base) { // cliccfg - clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e); - } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig - auto offset = ((addr&0x7fff)-0x40)/4; +template +iss::status riscv_hart_m_p::write_clic(uint64_t addr, unsigned length, const uint8_t* const data) { + if(addr == cfg.clic_base) { // cliccfg + clic_cfg_reg = (clic_cfg_reg & ~0x1e) | (*data & 0x1e); + } else if(addr >= (cfg.clic_base + 0x40) && (addr + length) <= (cfg.clic_base + 0x40 + cfg.clic_num_trigger * 4)) { // clicinttrig + auto offset = ((addr & 0x7fff) - 0x40) / 4; write_reg_uint32(addr, clic_inttrig_reg[offset], data, length); - } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl - auto offset = ((addr&0x7fff)-0x1000)/4; + } else if(addr >= (cfg.clic_base + 0x1000) && + (addr + length) <= (cfg.clic_base + 0x1000 + cfg.clic_num_irq * 4)) { // clicintip/clicintie/clicintattr/clicintctl + auto offset = ((addr & 0x7fff) - 0x1000) / 4; write_reg_uint32(addr, clic_int_reg[offset].raw, data, length); clic_int_reg[offset].raw &= 0xf0c70101; // clicIntCtlBits->0xf0, clicintattr->0xc7, clicintie->0x1, clicintip->0x1 } @@ -1182,8 +1194,8 @@ template inline void riscv_hart_m_p } template void riscv_hart_m_p::check_interrupt() { - //TODO: Implement CLIC functionality - //auto ideleg = csr[mideleg]; + // TODO: Implement CLIC functionality + // auto ideleg = csr[mideleg]; // Multiple simultaneous interrupts and traps at the same privilege level are // handled in the following decreasing priority order: // external interrupts, software interrupts, timer interrupts, then finally @@ -1194,11 +1206,11 @@ template void riscv_hart_m_p::check auto m_enabled = this->reg.PRIV < PRIV_M || mstatus_mie; auto enabled_interrupts = m_enabled ? ena_irq : 0; - if (enabled_interrupts != 0) { + if(enabled_interrupts != 0) { int res = 0; - while ((enabled_interrupts & 1) == 0) { - enabled_interrupts >>= 1; - res++; + while((enabled_interrupts & 1) == 0) { + enabled_interrupts >>= 1; + res++; } this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id } @@ -1211,8 +1223,9 @@ template uint64_t riscv_hart_m_p::e auto cause = bit_sub<16, 15>(flags); // calculate effective privilege level unsigned new_priv = PRIV_M; - if (trap_id == 0) { // exception - if (cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause + if(trap_id == 0) { // exception + if(cause == 11) + cause = 0x8 + PRIV_M; // adjust environment call cause // store ret addr in xepc register csr[mepc] = static_cast(addr) & get_pc_mask(); // store actual address instruction of exception /* @@ -1222,17 +1235,17 @@ template uint64_t riscv_hart_m_p::e * access, or page-fault exception occurs, mtval is written with the * faulting effective address. */ - switch(cause){ + switch(cause) { case 0: csr[mtval] = static_cast(addr); break; case 2: - csr[mtval] = (!has_compressed() || (instr & 0x3)==3)?instr:instr&0xffff; + csr[mtval] = (!has_compressed() || (instr & 0x3) == 3) ? instr : instr & 0xffff; break; case 3: if((FEAT & FEAT_DEBUG) && (csr[dcsr] & 0x8000)) { this->reg.DPC = addr; - csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi) + csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1 << 6) | PRIV_M; // FIXME: cause should not be 4 (stepi) new_priv = this->reg.PRIV | PRIV_D; } else { csr[mtval] = addr; @@ -1250,7 +1263,7 @@ template uint64_t riscv_hart_m_p::e csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt this->reg.pending_trap = 0; } - csr[mcause] = (trap_id << (traits::XLEN-1)) + cause; + csr[mcause] = (trap_id << (traits::XLEN - 1)) + cause; // update mstatus // xPP field of mstatus is written with the active privilege mode at the time // of the trap; the x PIE field of mstatus @@ -1265,7 +1278,7 @@ template uint64_t riscv_hart_m_p::e // get trap vector auto xtvec = csr[mtvec]; // calculate adds// set NEXT_PC to trap addressess to jump to based on MODE - if((FEAT & features_e::FEAT_CLIC) && trap_id!=0 && (xtvec & 0x3UL)==3UL) { + if((FEAT & features_e::FEAT_CLIC) && trap_id != 0 && (xtvec & 0x3UL) == 3UL) { reg_t data; auto ret = read(address_type::LOGICAL, access_type::READ, 0, csr[mtvt], sizeof(reg_t), reinterpret_cast(&data)); if(ret == iss::Err) @@ -1274,7 +1287,8 @@ template uint64_t riscv_hart_m_p::e } else { // bits in mtvec this->reg.NEXT_PC = xtvec & ~0x3UL; - if ((xtvec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause; + if((xtvec & 0x1) == 1 && trap_id != 0) + this->reg.NEXT_PC += 4 * cause; } // reset trap state this->reg.PRIV = new_priv; @@ -1285,10 +1299,10 @@ template uint64_t riscv_hart_m_p::e #else sprintf(buffer.data(), "0x%016lx", addr); #endif - if((flags&0xffffffff) != 0xffffffff) - CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" - << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")" - << " at address " << buffer.data() << " occurred"; + if((flags & 0xffffffff) != 0xffffffff) + CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" + << cause << ")" + << " at address " << buffer.data() << " occurred"; return this->reg.NEXT_PC; } diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index 56c7209..8355d3c 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -35,22 +35,22 @@ #ifndef _RISCV_HART_MSU_VP_H #define _RISCV_HART_MSU_VP_H -#include "riscv_hart_common.h" #include "iss/arch/traits.h" #include "iss/instrumentation_if.h" #include "iss/log_categories.h" #include "iss/vm_if.h" +#include "riscv_hart_common.h" #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif #include #include #include +#include #include #include #include #include -#include #include #include #include @@ -69,27 +69,28 @@ namespace arch { template class riscv_hart_msu_vp : public BASE { protected: const std::array lvl = {{'U', 'S', 'H', 'M'}}; - const std::array trap_str = {{"" - "Instruction address misaligned", // 0 - "Instruction access fault", // 1 - "Illegal instruction", // 2 - "Breakpoint", // 3 - "Load address misaligned", // 4 - "Load access fault", // 5 - "Store/AMO address misaligned", // 6 - "Store/AMO access fault", // 7 - "Environment call from U-mode", // 8 - "Environment call from S-mode", // 9 - "Reserved", // a - "Environment call from M-mode", // b - "Instruction page fault", // c - "Load page fault", // d - "Reserved", // e - "Store/AMO page fault"}}; - const std::array irq_str = { - {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt", - "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt", - "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; + const std::array trap_str = {{"" + "Instruction address misaligned", // 0 + "Instruction access fault", // 1 + "Illegal instruction", // 2 + "Breakpoint", // 3 + "Load address misaligned", // 4 + "Load access fault", // 5 + "Store/AMO address misaligned", // 6 + "Store/AMO access fault", // 7 + "Environment call from U-mode", // 8 + "Environment call from S-mode", // 9 + "Reserved", // a + "Environment call from M-mode", // b + "Instruction page fault", // c + "Load page fault", // d + "Reserved", // e + "Store/AMO page fault"}}; + const std::array irq_str = {{"User software interrupt", "Supervisor software interrupt", "Reserved", + "Machine software interrupt", "User timer interrupt", "Supervisor timer interrupt", + "Reserved", "Machine timer interrupt", "User external interrupt", + "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; + public: using core = BASE; using this_class = riscv_hart_msu_vp; @@ -98,7 +99,7 @@ public: using reg_t = typename core::reg_t; using addr_t = typename core::addr_t; - using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &); + using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t&); using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t); // primary template @@ -107,7 +108,8 @@ public: template class hart_state::value>::type> { public: BEGIN_BF_DECL(mstatus_t, T); - // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11))) + // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR + // XS==11))) BF_FIELD(SD, 31, 1); // Trap SRET BF_FIELD(TSR, 22, 1); @@ -121,7 +123,8 @@ public: BF_FIELD(SUM, 18, 1); // Modify PRiVilege BF_FIELD(MPRV, 17, 1); - // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty + // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None + // dirty, some clean/Some dirty BF_FIELD(XS, 15, 2); // floating-point unit status Off/Initial/Clean/Dirty BF_FIELD(FS, 13, 2); @@ -161,21 +164,28 @@ public: #if __cplusplus < 201402L return priv_lvl == PRIV_U ? 0x80000011UL : priv_lvl == PRIV_S ? 0x800de133UL : 0x807ff9ddUL; #else - switch (priv_lvl) { - case PRIV_U: return 0x80000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001 - case PRIV_S: return 0x800de133UL; // 0b1000 0000 0000 1101 1110 0001 0011 0011 - default: return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011 + switch(priv_lvl) { + case PRIV_U: + return 0x80000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001 + case PRIV_S: + return 0x800de133UL; // 0b1000 0000 0000 1101 1110 0001 0011 0011 + default: + return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011 } #endif } static inline vm_info decode_vm_info(uint32_t state, T sptbr) { - if (state == PRIV_M) return {0, 0, 0, 0}; - if (state <= PRIV_S) - switch (bit_sub<31, 1>(sptbr)) { - case 0: return {0, 0, 0, 0}; // off - case 1: return {2, 10, 4, bit_sub<0, 22>(sptbr) << PGSHIFT}; // SV32 - default: abort(); + if(state == PRIV_M) + return {0, 0, 0, 0}; + if(state <= PRIV_S) + switch(bit_sub<31, 1>(sptbr)) { + case 0: + return {0, 0, 0, 0}; // off + case 1: + return {2, 10, 4, bit_sub<0, 22>(sptbr) << PGSHIFT}; // SV32 + default: + abort(); } abort(); return {0, 0, 0, 0}; // dummy @@ -185,7 +195,8 @@ public: template class hart_state::value>::type> { public: BEGIN_BF_DECL(mstatus_t, T); - // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11))) + // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR + // XS==11))) BF_FIELD(SD, 63, 1); // value of XLEN for S-mode BF_FIELD(SXL, 34, 2); @@ -203,7 +214,8 @@ public: BF_FIELD(SUM, 18, 1); // Modify PRiVilege BF_FIELD(MPRV, 17, 1); - // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty + // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None + // dirty, some clean/Some dirty BF_FIELD(XS, 15, 2); // floating-point unit status Off/Initial/Clean/Dirty BF_FIELD(FS, 13, 2); @@ -233,10 +245,10 @@ public: T old_val = mstatus; auto mask = get_mask(priv_lvl); auto new_val = (old_val & ~mask) | (val & mask); - if ((new_val & mstatus.SXL.Mask) == 0) { + if((new_val & mstatus.SXL.Mask) == 0) { new_val |= old_val & mstatus.SXL.Mask; } - if ((new_val & mstatus.UXL.Mask) == 0) { + if((new_val & mstatus.UXL.Mask) == 0) { new_val |= old_val & mstatus.UXL.Mask; } mstatus = new_val; @@ -248,24 +260,37 @@ public: static constexpr T get_mask(unsigned priv_lvl) { uint64_t ret; - switch (priv_lvl) { - case PRIV_U: ret = 0x8000000f00000011ULL;break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011 - case PRIV_S: ret = 0x8000000f000de133ULL;break; // 0b1...0 0011 0000 0000 0000 1101 1110 0001 0011 0011 - default: ret = 0x8000000f007ff9ddULL;break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011 + switch(priv_lvl) { + case PRIV_U: + ret = 0x8000000f00000011ULL; + break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011 + case PRIV_S: + ret = 0x8000000f000de133ULL; + break; // 0b1...0 0011 0000 0000 0000 1101 1110 0001 0011 0011 + default: + ret = 0x8000000f007ff9ddULL; + break; // 0b1...0 1111 0000 0000 0111 1111 1111 1001 1011 1011 } return ret; } static inline vm_info decode_vm_info(uint32_t state, T sptbr) { - if (state == PRIV_M) return {0, 0, 0, 0}; - if (state <= PRIV_S) - switch (bit_sub<60, 4>(sptbr)) { - case 0: return {0, 0, 0, 0}; // off - case 8: return {3, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT};// SV39 - case 9: return {4, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT};// SV48 - case 10: return {5, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT};// SV57 - case 11: return {6, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT};// SV64 - default: abort(); + if(state == PRIV_M) + return {0, 0, 0, 0}; + if(state <= PRIV_S) + switch(bit_sub<60, 4>(sptbr)) { + case 0: + return {0, 0, 0, 0}; // off + case 8: + return {3, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT}; // SV39 + case 9: + return {4, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT}; // SV48 + case 10: + return {5, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT}; // SV57 + case 11: + return {6, 9, 8, bit_sub<0, 44>(sptbr) << PGSHIFT}; // SV64 + default: + abort(); } abort(); return {0, 0, 0, 0}; // dummy @@ -293,12 +318,12 @@ public: std::pair load_file(std::string name, int type = -1) override; - phys_addr_t virt2phys(const iss::addr_t &addr) override; + phys_addr_t virt2phys(const iss::addr_t& addr) override; - iss::status read(const address_type type, const access_type access, const uint32_t space, - const uint64_t addr, const unsigned length, uint8_t *const data) override; - iss::status write(const address_type type, const access_type access, const uint32_t space, - const uint64_t addr, const unsigned length, const uint8_t *const data) override; + iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, + uint8_t* const data) override; + iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, + const uint8_t* const data) override; uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); } uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override; @@ -306,23 +331,20 @@ public: void wait_until(uint64_t flags) override; void disass_output(uint64_t pc, const std::string instr) override { - CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", - pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.icount + cycle_offset); + CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, + this->reg.icount + cycle_offset); }; - iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; } + iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; } - void set_csr(unsigned addr, reg_t val){ - csr[addr & csr.page_addr_mask] = val; - } + void set_csr(unsigned addr, reg_t val) { csr[addr & csr.page_addr_mask] = val; } + + void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); } - void set_irq_num(unsigned i) { - mcause_max_irq=1< &arch) + riscv_instrumentation_if(riscv_hart_msu_vp& arch) : arch(arch) {} /** * get the name of this architecture @@ -347,19 +369,19 @@ protected: bool is_branch_taken() override { return arch.reg.last_branch; } - unsigned get_reg_num() override {return traits::NUM_REGS; } + unsigned get_reg_num() override { return traits::NUM_REGS; } - riscv_hart_msu_vp &arch; + riscv_hart_msu_vp& arch; }; friend struct riscv_instrumentation_if; addr_t get_pc() { return this->reg.PC; } addr_t get_next_pc() { return this->reg.NEXT_PC; } - virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data); - virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data); + virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t* const data); + virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t* const data); - virtual iss::status read_csr(unsigned addr, reg_t &val); + virtual iss::status read_csr(unsigned addr, reg_t& val); virtual iss::status write_csr(unsigned addr, reg_t val); hart_state_type state; @@ -388,40 +410,36 @@ protected: std::vector tcm; - iss::status read_csr_reg(unsigned addr, reg_t &val); + iss::status read_csr_reg(unsigned addr, reg_t& val); iss::status write_csr_reg(unsigned addr, reg_t val); - iss::status read_null(unsigned addr, reg_t &val); - iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;} - iss::status read_cycle(unsigned addr, reg_t &val); + iss::status read_null(unsigned addr, reg_t& val); + iss::status write_null(unsigned addr, reg_t val) { return iss::status::Ok; } + iss::status read_cycle(unsigned addr, reg_t& val); iss::status write_cycle(unsigned addr, reg_t val); - iss::status read_instret(unsigned addr, reg_t &val); + iss::status read_instret(unsigned addr, reg_t& val); iss::status write_instret(unsigned addr, reg_t val); - iss::status read_tvec(unsigned addr, reg_t &val); - iss::status read_time(unsigned addr, reg_t &val); - iss::status read_status(unsigned addr, reg_t &val); + iss::status read_tvec(unsigned addr, reg_t& val); + iss::status read_time(unsigned addr, reg_t& val); + iss::status read_status(unsigned addr, reg_t& val); iss::status write_status(unsigned addr, reg_t val); iss::status write_cause(unsigned addr, reg_t val); - iss::status read_ie(unsigned addr, reg_t &val); + iss::status read_ie(unsigned addr, reg_t& val); iss::status write_ie(unsigned addr, reg_t val); - iss::status read_ip(unsigned addr, reg_t &val); + iss::status read_ip(unsigned addr, reg_t& val); iss::status write_ideleg(unsigned addr, reg_t val); iss::status write_edeleg(unsigned addr, reg_t val); - iss::status read_hartid(unsigned addr, reg_t &val); + iss::status read_hartid(unsigned addr, reg_t& val); iss::status write_epc(unsigned addr, reg_t val); - iss::status read_satp(unsigned addr, reg_t &val); + iss::status read_satp(unsigned addr, reg_t& val); iss::status write_satp(unsigned addr, reg_t val); - iss::status read_fcsr(unsigned addr, reg_t &val); + iss::status read_fcsr(unsigned addr, reg_t& val); iss::status write_fcsr(unsigned addr, reg_t val); - virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;}; - virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;}; + virtual iss::status read_custom_csr_reg(unsigned addr, reg_t& val) { return iss::status::Err; }; + virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) { return iss::status::Err; }; - void register_custom_csr_rd(unsigned addr){ - csr_rd_cb[addr] = &this_class::read_custom_csr_reg; - } - void register_custom_csr_wr(unsigned addr){ - csr_wr_cb[addr] = &this_class::write_custom_csr_reg; - } + void register_custom_csr_rd(unsigned addr) { csr_rd_cb[addr] = &this_class::read_custom_csr_reg; } + void register_custom_csr_wr(unsigned addr) { csr_wr_cb[addr] = &this_class::write_custom_csr_reg; } reg_t mhartid_reg{0x0}; @@ -440,52 +458,56 @@ riscv_hart_msu_vp::riscv_hart_msu_vp() csr[mimpid] = 1; uart_buf.str(""); - for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){ + for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) { csr_rd_cb[addr] = &this_class::read_null; csr_wr_cb[addr] = &this_class::write_csr_reg; } - for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){ + for(unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr) { csr_rd_cb[addr] = &this_class::read_null; csr_wr_cb[addr] = &this_class::write_csr_reg; } - for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){ + for(unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr) { csr_rd_cb[addr] = &this_class::read_null; csr_wr_cb[addr] = &this_class::write_csr_reg; } - for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){ + for(unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr) { csr_rd_cb[addr] = &this_class::read_null; } - for (unsigned addr = cycleh; addr <= hpmcounter31h; ++addr){ + for(unsigned addr = cycleh; addr <= hpmcounter31h; ++addr) { csr_rd_cb[addr] = &this_class::read_null; - //csr_wr_cb[addr] = &this_class::write_csr_reg; + // csr_wr_cb[addr] = &this_class::write_csr_reg; } // common regs - const std::array addrs{{ - misa, mvendorid, marchid, mimpid, - mepc, mtvec, mscratch, mcause, mtval, mscratch, - sepc, stvec, sscratch, scause, stval, sscratch, - uepc, utvec, uscratch, ucause, utval, uscratch - }}; - for(auto addr: addrs) { + const std::array addrs{{misa, mvendorid, marchid, mimpid, mepc, mtvec, mscratch, mcause, + mtval, mscratch, sepc, stvec, sscratch, scause, stval, sscratch, + uepc, utvec, uscratch, ucause, utval, uscratch}}; + for(auto addr : addrs) { csr_rd_cb[addr] = &this_class::read_csr_reg; csr_wr_cb[addr] = &this_class::write_csr_reg; } // special handling & overrides csr_rd_cb[time] = &this_class::read_time; - if(traits::XLEN==32) csr_rd_cb[timeh] = &this_class::read_time; + if(traits::XLEN == 32) + csr_rd_cb[timeh] = &this_class::read_time; csr_rd_cb[cycle] = &this_class::read_cycle; - if(traits::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle; + if(traits::XLEN == 32) + csr_rd_cb[cycleh] = &this_class::read_cycle; csr_rd_cb[instret] = &this_class::read_instret; - if(traits::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret; + if(traits::XLEN == 32) + csr_rd_cb[instreth] = &this_class::read_instret; csr_rd_cb[mcycle] = &this_class::read_cycle; csr_wr_cb[mcycle] = &this_class::write_cycle; - if(traits::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle; - if(traits::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle; + if(traits::XLEN == 32) + csr_rd_cb[mcycleh] = &this_class::read_cycle; + if(traits::XLEN == 32) + csr_wr_cb[mcycleh] = &this_class::write_cycle; csr_rd_cb[minstret] = &this_class::read_instret; csr_wr_cb[minstret] = &this_class::write_instret; - if(traits::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret; - if(traits::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret; + if(traits::XLEN == 32) + csr_rd_cb[minstreth] = &this_class::read_instret; + if(traits::XLEN == 32) + csr_wr_cb[minstreth] = &this_class::write_instret; csr_rd_cb[mstatus] = &this_class::read_status; csr_wr_cb[mstatus] = &this_class::write_status; csr_wr_cb[mcause] = &this_class::write_cause; @@ -531,133 +553,137 @@ riscv_hart_msu_vp::riscv_hart_msu_vp() } template std::pair riscv_hart_msu_vp::load_file(std::string name, int type) { - FILE *fp = fopen(name.c_str(), "r"); - if (fp) { + FILE* fp = fopen(name.c_str(), "r"); + if(fp) { std::array buf; auto n = fread(buf.data(), 1, 4, fp); fclose(fp); - if (n != 4) throw std::runtime_error("input file has insufficient size"); + if(n != 4) + throw std::runtime_error("input file has insufficient size"); buf[4] = 0; - if (strcmp(buf.data() + 1, "ELF") == 0) { + if(strcmp(buf.data() + 1, "ELF") == 0) { // Create elfio reader ELFIO::elfio reader; // Load ELF data - if (!reader.load(name)) throw std::runtime_error("could not process elf file"); + if(!reader.load(name)) + throw std::runtime_error("could not process elf file"); // check elf properties - if (reader.get_class() != ELFCLASS32) - if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file"); - if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file"); - if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file"); + if(reader.get_class() != ELFCLASS32) + if(sizeof(reg_t) == 4) + throw std::runtime_error("wrong elf class in file"); + if(reader.get_type() != ET_EXEC) + throw std::runtime_error("wrong elf type in file"); + if(reader.get_machine() != EM_RISCV) + throw std::runtime_error("wrong elf machine in file"); auto entry = reader.get_entry(); - for (const auto pseg : reader.segments) { + for(const auto pseg : reader.segments) { const auto fsize = pseg->get_file_size(); // 0x42c/0x0 const auto seg_data = pseg->get_data(); - if (fsize > 0) { - auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, - traits::MEM, pseg->get_physical_address(), - fsize, reinterpret_cast(seg_data)); - if (res != iss::Ok) - LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex - << pseg->get_physical_address(); + if(fsize > 0) { + auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits::MEM, + pseg->get_physical_address(), fsize, reinterpret_cast(seg_data)); + if(res != iss::Ok) + LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); } } for(const auto sec : reader.sections) { if(sec->get_name() == ".symtab") { - if ( SHT_SYMTAB == sec->get_type() || - SHT_DYNSYM == sec->get_type() ) { - ELFIO::symbol_section_accessor symbols( reader, sec ); + if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) { + ELFIO::symbol_section_accessor symbols(reader, sec); auto sym_no = symbols.get_symbols_num(); - std::string name; - ELFIO::Elf64_Addr value = 0; - ELFIO::Elf_Xword size = 0; - unsigned char bind = 0; - unsigned char type = 0; - ELFIO::Elf_Half section = 0; - unsigned char other = 0; - for ( auto i = 0U; i < sym_no; ++i ) { - symbols.get_symbol( i, name, value, size, bind, type, section, other ); - if(name=="tohost") { + std::string name; + ELFIO::Elf64_Addr value = 0; + ELFIO::Elf_Xword size = 0; + unsigned char bind = 0; + unsigned char type = 0; + ELFIO::Elf_Half section = 0; + unsigned char other = 0; + for(auto i = 0U; i < sym_no; ++i) { + symbols.get_symbol(i, name, value, size, bind, type, section, other); + if(name == "tohost") { tohost = value; - } else if(name=="fromhost") { + } else if(name == "fromhost") { fromhost = value; } } } - } else if (sec->get_name() == ".tohost") { + } else if(sec->get_name() == ".tohost") { tohost = sec->get_address(); fromhost = tohost + 0x40; } - } return std::make_pair(entry, true); } - throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name)); + throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name)); } throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name)); } template -iss::status riscv_hart_msu_vp::read(const address_type type, const access_type access, const uint32_t space, - const uint64_t addr, const unsigned length, uint8_t *const data) { +iss::status riscv_hart_msu_vp::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, + const unsigned length, uint8_t* const data) { #ifndef NDEBUG - if (access && iss::access_type::DEBUG) { + if(access && iss::access_type::DEBUG) { LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; - } else if(access && iss::access_type::FETCH){ + } else if(access && iss::access_type::FETCH) { LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; } else { LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; - } + } #endif try { - switch (space) { + switch(space) { case traits::MEM: { - auto alignment = is_fetch(access)? (traits::MISA_VAL&0x100? 2 : 4) : length; - if (unlikely(is_fetch(access) && (addr&(alignment-1)))) { + auto alignment = is_fetch(access) ? (traits::MISA_VAL & 0x100 ? 2 : 4) : length; + if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) { fault_data = addr; - if (access && iss::access_type::DEBUG) throw trap_access(0, addr); + if(access && iss::access_type::DEBUG) + throw trap_access(0, addr); this->reg.trap_state = (1 << 31); // issue trap 0 return iss::Err; } try { - if(!is_debug(access) && (addr&(alignment-1))){ - this->reg.trap_state = 1<<31 | 4<<16; - fault_data=addr; + if(!is_debug(access) && (addr & (alignment - 1))) { + this->reg.trap_state = 1 << 31 | 4 << 16; + fault_data = addr; return iss::Err; } - if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary + if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary vm_info vm = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp); - if (vm.levels != 0) { // VM is active + if(vm.levels != 0) { // VM is active auto split_addr = (addr + length) & ~PGMASK; auto len1 = split_addr - addr; auto res = read(type, access, space, addr, len1, data); - if (res == iss::Ok) + if(res == iss::Ok) res = read(type, access, space, split_addr, length - len1, data + len1); return res; } } - auto res = read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data); - if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)){ - this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault - fault_data=addr; + auto res = read_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data); + if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) { + this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault + fault_data = addr; } return res; - } catch (trap_access &ta) { + } catch(trap_access& ta) { this->reg.trap_state = (1 << 31) | ta.id; - fault_data=ta.addr; + fault_data = ta.addr; return iss::Err; } } break; case traits::CSR: { - if (length != sizeof(reg_t)) return iss::Err; - return read_csr(addr, *reinterpret_cast(data)); + if(length != sizeof(reg_t)) + return iss::Err; + return read_csr(addr, *reinterpret_cast(data)); } break; case traits::FENCE: { - if ((addr + length) > mem.size()) return iss::Err; - switch (addr) { + if((addr + length) > mem.size()) + return iss::Err; + switch(addr) { case 2: // SFENCE:VMA lower case 3: { // SFENCE:VMA upper auto tvm = state.mstatus.TVM; - if (this->reg.PRIV == PRIV_S & tvm != 0) { + if(this->reg.PRIV == PRIV_S & tvm != 0) { this->reg.trap_state = (1 << 31) | (2 << 16); this->fault_data = this->reg.PC; return iss::Err; @@ -668,7 +694,7 @@ iss::status riscv_hart_msu_vp::read(const address_type type, const access_ } break; case traits::RES: { auto it = atomic_reservation.find(addr); - if (it != atomic_reservation.end() && it->second != 0) { + if(it != atomic_reservation.end() && it->second != 0) { memset(data, 0xff, length); atomic_reservation.erase(addr); } else @@ -678,79 +704,81 @@ iss::status riscv_hart_msu_vp::read(const address_type type, const access_ return iss::Err; // assert("Not supported"); } return iss::Ok; - } catch (trap_access &ta) { + } catch(trap_access& ta) { this->reg.trap_state = (1UL << 31) | ta.id; - fault_data=ta.addr; + fault_data = ta.addr; return iss::Err; } } template -iss::status riscv_hart_msu_vp::write(const address_type type, const access_type access, const uint32_t space, - const uint64_t addr, const unsigned length, const uint8_t *const data) { +iss::status riscv_hart_msu_vp::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, + const unsigned length, const uint8_t* const data) { #ifndef NDEBUG - const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; - switch (length) { + const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; + switch(length) { case 8: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec - << ") @addr 0x" << std::hex << addr; + LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" + << std::hex << addr; break; case 4: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec - << ") @addr 0x" << std::hex << addr; + LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" + << std::hex << addr; break; case 2: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec - << ") @addr 0x" << std::hex << addr; + LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" + << std::hex << addr; break; case 1: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec - << ") @addr 0x" << std::hex << addr; + LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" + << std::hex << addr; break; default: LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; } #endif try { - switch (space) { + switch(space) { case traits::MEM: { - if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) { + if(unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) { fault_data = addr; - if (access && iss::access_type::DEBUG) throw trap_access(0, addr); + if(access && iss::access_type::DEBUG) + throw trap_access(0, addr); this->reg.trap_state = (1 << 31); // issue trap 0 return iss::Err; } phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr}); try { - if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary + if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary vm_info vm = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp); - if (vm.levels != 0) { // VM is active + if(vm.levels != 0) { // VM is active auto split_addr = (addr + length) & ~PGMASK; auto len1 = split_addr - addr; auto res = write(type, access, space, addr, len1, data); - if (res == iss::Ok) + if(res == iss::Ok) res = write(type, access, space, split_addr, length - len1, data + len1); return res; } } auto res = write_mem(paddr, length, data); - if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) { + if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) { this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault) - fault_data=addr; + fault_data = addr; } return res; - } catch (trap_access &ta) { + } catch(trap_access& ta) { this->reg.trap_state = (1UL << 31) | ta.id; - fault_data=ta.addr; + fault_data = ta.addr; return iss::Err; } - if ((paddr.val + length) > mem.size()) return iss::Err; - switch (paddr.val) { + if((paddr.val + length) > mem.size()) + return iss::Err; + switch(paddr.val) { case 0x10013000: // UART0 base, TXFIFO reg case 0x10023000: // UART1 base, TXFIFO reg uart_buf << (char)data[0]; - if (((char)data[0]) == '\n' || data[0] == 0) { + if(((char)data[0]) == '\n' || data[0] == 0) { // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send // '"<::write(const address_type type, const access } return iss::Ok; case 0x10008000: { // HFROSC base, hfrosccfg reg - auto &p = mem(paddr.val / mem.page_size); + auto& p = mem(paddr.val / mem.page_size); auto offs = paddr.val & mem.page_addr_mask; std::copy(data, data + length, p.data() + offs); - auto &x = *(p.data() + offs + 3); - if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1 + auto& x = *(p.data() + offs + 3); + if(x & 0x40) + x |= 0x80; // hfroscrdy = 1 if hfroscen==1 return iss::Ok; } case 0x10008008: { // HFROSC base, pllcfg reg - auto &p = mem(paddr.val / mem.page_size); + auto& p = mem(paddr.val / mem.page_size); auto offs = paddr.val & mem.page_addr_mask; std::copy(data, data + length, p.data() + offs); - auto &x = *(p.data() + offs + 3); + auto& x = *(p.data() + offs + 3); x |= 0x80; // set pll lock upon writing return iss::Ok; } break; @@ -777,17 +806,19 @@ iss::status riscv_hart_msu_vp::write(const address_type type, const access } } break; case traits::CSR: { - if (length != sizeof(reg_t)) return iss::Err; - return write_csr(addr, *reinterpret_cast(data)); + if(length != sizeof(reg_t)) + return iss::Err; + return write_csr(addr, *reinterpret_cast(data)); } break; case traits::FENCE: { - if ((addr + length) > mem.size()) return iss::Err; - switch (addr) { + if((addr + length) > mem.size()) + return iss::Err; + switch(addr) { case 2: case 3: { ptw.clear(); auto tvm = state.mstatus.TVM; - if (this->reg.PRIV == PRIV_S & tvm != 0) { + if(this->reg.PRIV == PRIV_S & tvm != 0) { this->reg.trap_state = (1 << 31) | (2 << 16); this->fault_data = this->reg.PC; return iss::Err; @@ -803,43 +834,45 @@ iss::status riscv_hart_msu_vp::write(const address_type type, const access return iss::Err; } return iss::Ok; - } catch (trap_access &ta) { + } catch(trap_access& ta) { this->reg.trap_state = (1UL << 31) | ta.id; - fault_data=ta.addr; + fault_data = ta.addr; return iss::Err; } } -template iss::status riscv_hart_msu_vp::read_csr(unsigned addr, reg_t &val) { - if (addr >= csr.size()) return iss::Err; +template iss::status riscv_hart_msu_vp::read_csr(unsigned addr, reg_t& val) { + if(addr >= csr.size()) + return iss::Err; auto req_priv_lvl = (addr >> 8) & 0x3; - if (this->reg.PRIV < req_priv_lvl) // not having required privileges - throw illegal_instruction_fault(this->fault_data); + if(this->reg.PRIV < req_priv_lvl) // not having required privileges + throw illegal_instruction_fault(this->fault_data); auto it = csr_rd_cb.find(addr); - if (it == csr_rd_cb.end() || !it->second) // non existent register + if(it == csr_rd_cb.end() || !it->second) // non existent register throw illegal_instruction_fault(this->fault_data); return (this->*(it->second))(addr, val); } template iss::status riscv_hart_msu_vp::write_csr(unsigned addr, reg_t val) { - if (addr >= csr.size()) return iss::Err; + if(addr >= csr.size()) + return iss::Err; auto req_priv_lvl = (addr >> 8) & 0x3; - if (this->reg.PRIV < req_priv_lvl) // not having required privileges + if(this->reg.PRIV < req_priv_lvl) // not having required privileges throw illegal_instruction_fault(this->fault_data); - if((addr&0xc00)==0xc00) // writing to read-only region + if((addr & 0xc00) == 0xc00) // writing to read-only region throw illegal_instruction_fault(this->fault_data); auto it = csr_wr_cb.find(addr); - if (it == csr_wr_cb.end() || !it->second) // non existent register + if(it == csr_wr_cb.end() || !it->second) // non existent register throw illegal_instruction_fault(this->fault_data); return (this->*(it->second))(addr, val); } -template iss::status riscv_hart_msu_vp::read_reg(unsigned addr, reg_t &val) { +template iss::status riscv_hart_msu_vp::read_reg(unsigned addr, reg_t& val) { val = csr[addr]; return iss::Ok; } -template iss::status riscv_hart_msu_vp::read_null(unsigned addr, reg_t &val) { +template iss::status riscv_hart_msu_vp::read_null(unsigned addr, reg_t& val) { val = 0; return iss::Ok; } @@ -849,71 +882,73 @@ template iss::status riscv_hart_msu_vp::write_reg(unsigned return iss::Ok; } -template iss::status riscv_hart_msu_vp::read_cycle(unsigned addr, reg_t &val) { +template iss::status riscv_hart_msu_vp::read_cycle(unsigned addr, reg_t& val) { auto cycle_val = this->reg.icount + cycle_offset; - if (addr == mcycle) { + if(addr == mcycle) { val = static_cast(cycle_val); - } else if (addr == mcycleh) { - if (sizeof(typename traits::reg_t) != 4) return iss::Err; + } else if(addr == mcycleh) { + if(sizeof(typename traits::reg_t) != 4) + return iss::Err; val = static_cast(cycle_val >> 32); } return iss::Ok; } template iss::status riscv_hart_msu_vp::write_cycle(unsigned addr, reg_t val) { - if (sizeof(typename traits::reg_t) != 4) { + if(sizeof(typename traits::reg_t) != 4) { mcycle_csr = static_cast(val); } else { - if (addr == mcycle) { + if(addr == mcycle) { mcycle_csr = (mcycle_csr & 0xffffffff00000000) + val; - } else { - mcycle_csr = (static_cast(val)<<32) + (mcycle_csr & 0xffffffff); + } else { + mcycle_csr = (static_cast(val) << 32) + (mcycle_csr & 0xffffffff); } } - cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around + cycle_offset = mcycle_csr - this->reg.icount; // TODO: relying on wrap-around return iss::Ok; } -template iss::status riscv_hart_msu_vp::read_instret(unsigned addr, reg_t &val) { - if ((addr&0xff) == (minstret&0xff)) { +template iss::status riscv_hart_msu_vp::read_instret(unsigned addr, reg_t& val) { + if((addr & 0xff) == (minstret & 0xff)) { val = static_cast(this->reg.instret); - } else if ((addr&0xff) == (minstreth&0xff)) { + } else if((addr & 0xff) == (minstreth & 0xff)) { val = static_cast(this->reg.instret >> 32); } return iss::Ok; } template iss::status riscv_hart_msu_vp::write_instret(unsigned addr, reg_t val) { - if (sizeof(typename traits::reg_t) != 4) { + if(sizeof(typename traits::reg_t) != 4) { this->reg.instret = static_cast(val); } else { - if ((addr&0xff) == (minstret&0xff)) { + if((addr & 0xff) == (minstret & 0xff)) { this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val; - } else { - this->reg.instret = (static_cast(val)<<32) + (this->reg.instret & 0xffffffff); + } else { + this->reg.instret = (static_cast(val) << 32) + (this->reg.instret & 0xffffffff); } } this->reg.instret--; return iss::Ok; } -template iss::status riscv_hart_msu_vp::read_time(unsigned addr, reg_t &val) { +template iss::status riscv_hart_msu_vp::read_time(unsigned addr, reg_t& val) { uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052; - if (addr == time) { + if(addr == time) { val = static_cast(time_val); - } else if (addr == timeh) { - if (sizeof(typename traits::reg_t) != 4) return iss::Err; + } else if(addr == timeh) { + if(sizeof(typename traits::reg_t) != 4) + return iss::Err; val = static_cast(time_val >> 32); } return iss::Ok; } -template iss::status riscv_hart_msu_vp::read_tvec(unsigned addr, reg_t &val) { +template iss::status riscv_hart_msu_vp::read_tvec(unsigned addr, reg_t& val) { val = csr[addr] & ~2; return iss::Ok; } -template iss::status riscv_hart_msu_vp::read_status(unsigned addr, reg_t &val) { +template iss::status riscv_hart_msu_vp::read_status(unsigned addr, reg_t& val) { auto req_priv_lvl = (addr >> 8) & 0x3; val = state.mstatus & hart_state_type::get_mask(req_priv_lvl); return iss::Ok; @@ -928,18 +963,20 @@ template iss::status riscv_hart_msu_vp::write_status(unsig } template iss::status riscv_hart_msu_vp::write_cause(unsigned addr, reg_t val) { - csr[addr] = val & ((1UL<<(traits::XLEN-1))|0xf); //TODO: make exception code size configurable + csr[addr] = val & ((1UL << (traits::XLEN - 1)) | 0xf); // TODO: make exception code size configurable return iss::Ok; } -template iss::status riscv_hart_msu_vp::read_ie(unsigned addr, reg_t &val) { +template iss::status riscv_hart_msu_vp::read_ie(unsigned addr, reg_t& val) { val = csr[mie]; - if (addr < mie) val &= csr[mideleg]; - if (addr < sie) val &= csr[sideleg]; + if(addr < mie) + val &= csr[mideleg]; + if(addr < sie) + val &= csr[sideleg]; return iss::Ok; } -template iss::status riscv_hart_msu_vp::read_hartid(unsigned addr, reg_t &val) { +template iss::status riscv_hart_msu_vp::read_hartid(unsigned addr, reg_t& val) { val = mhartid_reg; return iss::Ok; } @@ -952,10 +989,12 @@ template iss::status riscv_hart_msu_vp::write_ie(unsigned return iss::Ok; } -template iss::status riscv_hart_msu_vp::read_ip(unsigned addr, reg_t &val) { +template iss::status riscv_hart_msu_vp::read_ip(unsigned addr, reg_t& val) { val = csr[mip]; - if (addr < mip) val &= csr[mideleg]; - if (addr < sip) val &= csr[sideleg]; + if(addr < mip) + val &= csr[mideleg]; + if(addr < sip) + val &= csr[sideleg]; return iss::Ok; } @@ -964,9 +1003,9 @@ template iss::status riscv_hart_msu_vp::write_epc(unsigned return iss::Ok; } -template iss::status riscv_hart_msu_vp::read_satp(unsigned addr, reg_t &val) { +template iss::status riscv_hart_msu_vp::read_satp(unsigned addr, reg_t& val) { reg_t tvm = state.mstatus.TVM; - if (this->reg.PRIV == PRIV_S & tvm != 0) { + if(this->reg.PRIV == PRIV_S & tvm != 0) { this->reg.trap_state = (1 << 31) | (2 << 16); this->fault_data = this->reg.PC; return iss::Err; @@ -977,7 +1016,7 @@ template iss::status riscv_hart_msu_vp::read_satp(unsigned template iss::status riscv_hart_msu_vp::write_satp(unsigned addr, reg_t val) { reg_t tvm = state.mstatus.TVM; - if (this->reg.PRIV == PRIV_S & tvm != 0) { + if(this->reg.PRIV == PRIV_S & tvm != 0) { this->reg.trap_state = (1 << 31) | (2 << 16); this->fault_data = this->reg.PC; return iss::Err; @@ -986,8 +1025,8 @@ template iss::status riscv_hart_msu_vp::write_satp(unsigne update_vm_info(); return iss::Ok; } -template iss::status riscv_hart_msu_vp::read_fcsr(unsigned addr, reg_t &val) { - switch (addr) { +template iss::status riscv_hart_msu_vp::read_fcsr(unsigned addr, reg_t& val) { + switch(addr) { case 1: // fflags, 4:0 val = bit_sub<0, 5>(this->get_fcsr()); break; @@ -1004,7 +1043,7 @@ template iss::status riscv_hart_msu_vp::read_fcsr(unsigned } template iss::status riscv_hart_msu_vp::write_fcsr(unsigned addr, reg_t val) { - switch (addr) { + switch(addr) { case 1: // fflags, 4:0 this->set_fcsr((this->get_fcsr() & 0xffffffe0) | (val & 0x1f)); break; @@ -1020,56 +1059,53 @@ template iss::status riscv_hart_msu_vp::write_fcsr(unsigne return iss::Ok; } -template -iss::status riscv_hart_msu_vp::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) { - switch (paddr.val) { +template iss::status riscv_hart_msu_vp::read_mem(phys_addr_t paddr, unsigned length, uint8_t* const data) { + switch(paddr.val) { default: { - for(auto offs=0U; offs -iss::status riscv_hart_msu_vp::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) { - switch (paddr.val) { +template iss::status riscv_hart_msu_vp::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) { + switch(paddr.val) { case 0xFFFF0000: // UART0 base, TXFIFO reg - if (((char)data[0]) == '\n' || data[0] == 0) { - LOG(INFO)<<"UART"<<((paddr.val>>12)&0x3)<<" send '"<> 12) & 0x3) << " send '" << uart_buf.str() << "'"; uart_buf.str(""); } else if(((char)data[0]) != '\r') uart_buf << (char)data[0]; break; default: { - mem_type::page_type &p = mem(paddr.val / mem.page_size); + mem_type::page_type& p = mem(paddr.val / mem.page_size); std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); // tohost handling in case of riscv-test - if (paddr.access && iss::access_type::FUNC) { - auto tohost_upper = (traits::XLEN == 32 && paddr.val == (tohost + 4)) || - (traits::XLEN == 64 && paddr.val == tohost); - auto tohost_lower = - (traits::XLEN == 32 && paddr.val == tohost) || (traits::XLEN == 64 && paddr.val == tohost); - if (tohost_lower || tohost_upper) { - uint64_t hostvar = *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)); - if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) { - switch (hostvar >> 48) { + if(paddr.access && iss::access_type::FUNC) { + auto tohost_upper = + (traits::XLEN == 32 && paddr.val == (tohost + 4)) || (traits::XLEN == 64 && paddr.val == tohost); + auto tohost_lower = (traits::XLEN == 32 && paddr.val == tohost) || (traits::XLEN == 64 && paddr.val == tohost); + if(tohost_lower || tohost_upper) { + uint64_t hostvar = *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)); + if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) { + switch(hostvar >> 48) { case 0: - if (hostvar != 0x1) { + if(hostvar != 0x1) { LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } else { LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } - this->reg.trap_state=std::numeric_limits::max(); - this->interrupt_sim=hostvar; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = hostvar; break; - //throw(iss::simulation_stopped(hostvar)); + // throw(iss::simulation_stopped(hostvar)); case 0x0101: { char c = static_cast(hostvar & 0xff); - if (c == '\n' || c == 0) { + if(c == '\n' || c == 0) { LOG(INFO) << "tohost send '" << uart_buf.str() << "'"; uart_buf.str(""); } else @@ -1079,12 +1115,11 @@ iss::status riscv_hart_msu_vp::write_mem(phys_addr_t paddr, unsigned lengt default: break; } - } else if (tohost_lower) + } else if(tohost_lower) to_host_wr_cnt++; - } else if ((traits::XLEN == 32 && paddr.val == fromhost + 4) || - (traits::XLEN == 64 && paddr.val == fromhost)) { - uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); - *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; + } else if((traits::XLEN == 32 && paddr.val == fromhost + 4) || (traits::XLEN == 64 && paddr.val == fromhost)) { + uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); + *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; } } } @@ -1100,12 +1135,12 @@ template inline void riscv_hart_msu_vp::reset(uint64_t add template inline void riscv_hart_msu_vp::update_vm_info() { vm[1] = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp); - BASE::addr_mode[3]=BASE::addr_mode[2] = vm[1].is_active()? iss::address_type::VIRTUAL : iss::address_type::PHYSICAL; - if (state.mstatus.MPRV) + BASE::addr_mode[3] = BASE::addr_mode[2] = vm[1].is_active() ? iss::address_type::VIRTUAL : iss::address_type::PHYSICAL; + if(state.mstatus.MPRV) vm[0] = hart_state_type::decode_vm_info(state.mstatus.MPP, state.satp); else vm[0] = vm[1]; - BASE::addr_mode[1] = BASE::addr_mode[0]=vm[0].is_active() ? iss::address_type::VIRTUAL : iss::address_type::PHYSICAL; + BASE::addr_mode[1] = BASE::addr_mode[0] = vm[0].is_active() ? iss::address_type::VIRTUAL : iss::address_type::PHYSICAL; ptw.clear(); } @@ -1124,42 +1159,42 @@ template void riscv_hart_msu_vp::check_interrupt() { auto m_enabled = this->reg.PRIV < PRIV_M || (this->reg.PRIV == PRIV_M && mie); auto enabled_interrupts = m_enabled ? ena_irq & ~ideleg : 0; - if (enabled_interrupts == 0) { + if(enabled_interrupts == 0) { auto sie = state.mstatus.SIE; auto s_enabled = this->reg.PRIV < PRIV_S || (this->reg.PRIV == PRIV_S && sie); enabled_interrupts = s_enabled ? ena_irq & ideleg : 0; } - if (enabled_interrupts != 0) { + if(enabled_interrupts != 0) { int res = 0; - while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++; + while((enabled_interrupts & 1) == 0) + enabled_interrupts >>= 1, res++; this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id } } -template -typename riscv_hart_msu_vp::phys_addr_t riscv_hart_msu_vp::virt2phys(const iss::addr_t &addr) { +template typename riscv_hart_msu_vp::phys_addr_t riscv_hart_msu_vp::virt2phys(const iss::addr_t& addr) { const auto type = addr.access & iss::access_type::FUNC; auto it = ptw.find(addr.val >> PGSHIFT); - if (it != ptw.end()) { + if(it != ptw.end()) { const reg_t pte = it->second; const reg_t ad = PTE_A | (type == iss::access_type::WRITE) * PTE_D; #ifdef RISCV_ENABLE_DIRTY // set accessed and possibly dirty bits. - *(uint32_t *)ppte |= ad; + *(uint32_t*)ppte |= ad; return {addr.getAccessType(), addr.space, (pte & (~PGMASK)) | (addr.val & PGMASK)}; #else // take exception if access or possibly dirty bit is not set. - if ((pte & ad) == ad) + if((pte & ad) == ad) return {addr.access, addr.space, (pte & (~PGMASK)) | (addr.val & PGMASK)}; else ptw.erase(it); // throw an exception #endif } else { uint32_t mode = type != iss::access_type::FETCH && state.mstatus.MPRV ? // MPRV - state.mstatus.MPP : - this->reg.PRIV; + state.mstatus.MPP + : this->reg.PRIV; - const vm_info &vm = this->vm[static_cast(type) / 2]; + const vm_info& vm = this->vm[static_cast(type) / 2]; const bool s_mode = mode == PRIV_S; const bool sum = state.mstatus.SUM; @@ -1172,38 +1207,39 @@ typename riscv_hart_msu_vp::phys_addr_t riscv_hart_msu_vp::virt2phys const int levels = (masked_msbs != 0 && masked_msbs != mask) ? 0 : vm.levels; reg_t base = vm.ptbase; - for (int i = levels - 1; i >= 0; i--) { + for(int i = levels - 1; i >= 0; i--) { const int ptshift = i * vm.idxbits; const reg_t idx = (addr.val >> (PGSHIFT + ptshift)) & ((1 << vm.idxbits) - 1); // check that physical address of PTE is legal reg_t pte = 0; - const uint8_t res = this->read(iss::address_type::PHYSICAL, addr.access, - traits::MEM, base + idx * vm.ptesize, vm.ptesize, (uint8_t *)&pte); - if (res != 0) throw trap_load_access_fault(addr.val); + const uint8_t res = this->read(iss::address_type::PHYSICAL, addr.access, traits::MEM, base + idx * vm.ptesize, vm.ptesize, + (uint8_t*)&pte); + if(res != 0) + throw trap_load_access_fault(addr.val); const reg_t ppn = pte >> PTE_PPN_SHIFT; - if (PTE_TABLE(pte)) { // next level of page table + if(PTE_TABLE(pte)) { // next level of page table base = ppn << PGSHIFT; - } else if ((pte & PTE_U) ? s_mode && (type == iss::access_type::FETCH || !sum) : !s_mode) { + } else if((pte & PTE_U) ? s_mode && (type == iss::access_type::FETCH || !sum) : !s_mode) { break; - } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { + } else if(!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { break; - } else if (type == iss::access_type::FETCH - ? !(pte & PTE_X) - : type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X)) - : !((pte & PTE_R) && (pte & PTE_W))) { + } else if(type == iss::access_type::FETCH ? !(pte & PTE_X) + : type == iss::access_type::READ ? !(pte & PTE_R) && !(mxr && (pte & PTE_X)) + : !((pte & PTE_R) && (pte & PTE_W))) { break; - } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { + } else if((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { break; } else { const reg_t ad = PTE_A | ((type == iss::access_type::WRITE) * PTE_D); #ifdef RISCV_ENABLE_DIRTY // set accessed and possibly dirty bits. - *(uint32_t *)ppte |= ad; + *(uint32_t*)ppte |= ad; #else // take exception if access or possibly dirty bit is not set. - if ((pte & ad) != ad) break; + if((pte & ad) != ad) + break; #endif // for superpage mappings, make a fake leaf PTE for the TLB's benefit. const reg_t vpn = addr.val >> PGSHIFT; @@ -1214,7 +1250,7 @@ typename riscv_hart_msu_vp::phys_addr_t riscv_hart_msu_vp::virt2phys } } } - switch (type) { + switch(type) { case access_type::FETCH: this->fault_data = addr.val; throw trap_instruction_page_fault(addr.val); @@ -1233,14 +1269,16 @@ template uint64_t riscv_hart_msu_vp::enter_trap(uint64_t f auto cur_priv = this->reg.PRIV; // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0] // calculate and write mcause val - if(flags==std::numeric_limits::max()) flags=this->reg.trap_state; + if(flags == std::numeric_limits::max()) + flags = this->reg.trap_state; auto trap_id = bit_sub<0, 16>(flags); auto cause = bit_sub<16, 15>(flags); - if (trap_id == 0 && cause == 11) cause = 0x8 + cur_priv; // adjust environment call cause + if(trap_id == 0 && cause == 11) + cause = 0x8 + cur_priv; // adjust environment call cause // calculate effective privilege level auto new_priv = PRIV_M; - if (trap_id == 0) { // exception - if (cur_priv != PRIV_M && ((csr[medeleg] >> cause) & 0x1) != 0) + if(trap_id == 0) { // exception + if(cur_priv != PRIV_M && ((csr[medeleg] >> cause) & 0x1) != 0) new_priv = (csr[sedeleg] >> cause) & 0x1 ? PRIV_U : PRIV_S; // store ret addr in xepc register csr[uepc | (new_priv << 8)] = static_cast(addr); // store actual address instruction of exception @@ -1251,15 +1289,15 @@ template uint64_t riscv_hart_msu_vp::enter_trap(uint64_t f * access, or page-fault exception occurs, mtval is written with the * faulting effective address. */ - switch(cause){ + switch(cause) { case 0: csr[utval | (new_priv << 8)] = static_cast(addr); break; case 2: - csr[utval | (new_priv << 8)] = (instr & 0x3)==3?instr:instr&0xffff; + csr[utval | (new_priv << 8)] = (instr & 0x3) == 3 ? instr : instr & 0xffff; break; case 3: - //TODO: implement debug mode behavior + // TODO: implement debug mode behavior // csr[dpc] = addr; // csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi) csr[utval | (new_priv << 8)] = addr; @@ -1274,7 +1312,7 @@ template uint64_t riscv_hart_msu_vp::enter_trap(uint64_t f } fault_data = 0; } else { - if (cur_priv != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0) + if(cur_priv != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0) new_priv = (csr[sideleg] >> cause) & 0x1 ? PRIV_U : PRIV_S; csr[uepc | (new_priv << 8)] = this->reg.NEXT_PC; // store next address if interrupt this->reg.pending_trap = 0; @@ -1288,7 +1326,7 @@ template uint64_t riscv_hart_msu_vp::enter_trap(uint64_t f // the trap; and the x IE field of mstatus // is cleared // store the actual privilege level in yPP and store interrupt enable flags - switch (new_priv) { + switch(new_priv) { case PRIV_M: state.mstatus.MPP = cur_priv; state.mstatus.MPIE = state.mstatus.MIE; @@ -1312,14 +1350,15 @@ template uint64_t riscv_hart_msu_vp::enter_trap(uint64_t f // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE // bits in mtvec this->reg.NEXT_PC = ivec & ~0x3UL; - if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause; + if((ivec & 0x1) == 1 && trap_id != 0) + this->reg.NEXT_PC += 4 * cause; std::array buffer; sprintf(buffer.data(), "0x%016lx", addr); - if((flags&0xffffffff) != 0xffffffff) - CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" - << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")" - << " at address " << buffer.data() << " occurred, changing privilege level from " - << lvl[cur_priv] << " to " << lvl[new_priv]; + if((flags & 0xffffffff) != 0xffffffff) + CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" + << cause << ")" + << " at address " << buffer.data() << " occurred, changing privilege level from " << lvl[cur_priv] << " to " + << lvl[new_priv]; // reset trap state this->reg.PRIV = new_priv; this->reg.trap_state = 0; @@ -1333,7 +1372,7 @@ template uint64_t riscv_hart_msu_vp::leave_trap(uint64_t f auto status = state.mstatus; auto tsr = state.mstatus.TSR; - if (cur_priv == PRIV_S && inst_priv == PRIV_S && tsr != 0) { + if(cur_priv == PRIV_S && inst_priv == PRIV_S && tsr != 0) { this->reg.trap_state = (1 << 31) | (2 << 16); this->fault_data = this->reg.PC; return this->reg.PC; @@ -1341,7 +1380,7 @@ template uint64_t riscv_hart_msu_vp::leave_trap(uint64_t f // pop the relevant lower-privilege interrupt enable and privilege mode stack // clear respective yIE - switch (inst_priv) { + switch(inst_priv) { case PRIV_M: this->reg.PRIV = state.mstatus.MPP; state.mstatus.MPP = 0; // clear mpp to U mode @@ -1362,8 +1401,7 @@ template uint64_t riscv_hart_msu_vp::leave_trap(uint64_t f } // sets the pc to the value stored in the x epc register. this->reg.NEXT_PC = csr[uepc | inst_priv << 8]; - CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to " - << lvl[this->reg.PRIV]; + CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to " << lvl[this->reg.PRIV]; update_vm_info(); check_interrupt(); return this->reg.NEXT_PC; @@ -1372,12 +1410,12 @@ template uint64_t riscv_hart_msu_vp::leave_trap(uint64_t f template void riscv_hart_msu_vp::wait_until(uint64_t flags) { auto status = state.mstatus; auto tw = status.TW; - if (this->reg.PRIV == PRIV_S && tw != 0) { + if(this->reg.PRIV == PRIV_S && tw != 0) { this->reg.trap_state = (1 << 31) | (2 << 16); this->fault_data = this->reg.PC; } } -} -} +} // namespace arch +} // namespace iss #endif /* _RISCV_HART_MSU_VP_H */ diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 33089af..7d4f999 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -35,22 +35,22 @@ #ifndef _RISCV_HART_MU_P_H #define _RISCV_HART_MU_P_H -#include "riscv_hart_common.h" #include "iss/arch/traits.h" #include "iss/instrumentation_if.h" #include "iss/log_categories.h" #include "iss/vm_if.h" +#include "riscv_hart_common.h" #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif #include #include #include +#include #include #include #include #include -#include #include #include #include @@ -66,30 +66,31 @@ namespace iss { namespace arch { -template class riscv_hart_mu_p : public BASE { +template class riscv_hart_mu_p : public BASE { protected: const std::array lvl = {{'U', 'S', 'H', 'M'}}; - const std::array trap_str = {{"" - "Instruction address misaligned", // 0 - "Instruction access fault", // 1 - "Illegal instruction", // 2 - "Breakpoint", // 3 - "Load address misaligned", // 4 - "Load access fault", // 5 - "Store/AMO address misaligned", // 6 - "Store/AMO access fault", // 7 - "Environment call from U-mode", // 8 - "Environment call from S-mode", // 9 - "Reserved", // a - "Environment call from M-mode", // b - "Instruction page fault", // c - "Load page fault", // d - "Reserved", // e - "Store/AMO page fault"}}; - const std::array irq_str = { - {"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt", - "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt", - "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; + const std::array trap_str = {{"" + "Instruction address misaligned", // 0 + "Instruction access fault", // 1 + "Illegal instruction", // 2 + "Breakpoint", // 3 + "Load address misaligned", // 4 + "Load access fault", // 5 + "Store/AMO address misaligned", // 6 + "Store/AMO access fault", // 7 + "Environment call from U-mode", // 8 + "Environment call from S-mode", // 9 + "Reserved", // a + "Environment call from M-mode", // b + "Instruction page fault", // c + "Load page fault", // d + "Reserved", // e + "Store/AMO page fault"}}; + const std::array irq_str = {{"User software interrupt", "Supervisor software interrupt", "Reserved", + "Machine software interrupt", "User timer interrupt", "Supervisor timer interrupt", + "Reserved", "Machine timer interrupt", "User external interrupt", + "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; + public: using core = BASE; using this_class = riscv_hart_mu_p; @@ -97,10 +98,10 @@ public: using reg_t = typename core::reg_t; using addr_t = typename core::addr_t; - using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &); - using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t); - using mem_read_f = iss::status(phys_addr_t addr, unsigned, uint8_t *const); - using mem_write_f = iss::status(phys_addr_t addr, unsigned, uint8_t const *const); + using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t&); + using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t); + using mem_read_f = iss::status(phys_addr_t addr, unsigned, uint8_t* const); + using mem_write_f = iss::status(phys_addr_t addr, unsigned, uint8_t const* const); // primary template template struct hart_state {}; @@ -108,7 +109,8 @@ public: template class hart_state::value>::type> { public: BEGIN_BF_DECL(mstatus_t, T); - // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11))) + // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR + // XS==11))) BF_FIELD(SD, 31, 1); // Trap SRET BF_FIELD(TSR, 22, 1); @@ -122,7 +124,8 @@ public: BF_FIELD(SUM, 18, 1); // Modify PRiVilege BF_FIELD(MPRV, 17, 1); - // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty + // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None + // dirty, some clean/Some dirty BF_FIELD(XS, 15, 2); // floating-point unit status Off/Initial/Clean/Dirty BF_FIELD(FS, 13, 2); @@ -158,25 +161,26 @@ public: #if __cplusplus < 201402L return priv_lvl == PRIV_U ? 0x80000011UL : priv_lvl == PRIV_S ? 0x800de133UL : 0x807ff9ddUL; #else - switch (priv_lvl) { - case PRIV_U: return 0x00000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001 + switch(priv_lvl) { + case PRIV_U: + return 0x00000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001 default: - // +-SD - // | +-TSR - // | |+-TW - // | ||+-TVM - // | |||+-MXR - // | ||||+-SUM - // | |||||+-MPRV - // | |||||| +-XS - // | |||||| | +-FS - // | |||||| | | +-MPP - // | |||||| | | | +-SPP - // | |||||| | | | |+-MPIE - // | |||||| | | | || +-UPIE - // | ||||||/|/|/| || |+-MIE - // | ||||||/|/|/| || || +-UIE - return 0b00000000000000000001100010011001; + // +-SD + // | +-TSR + // | |+-TW + // | ||+-TVM + // | |||+-MXR + // | ||||+-SUM + // | |||||+-MPRV + // | |||||| +-XS + // | |||||| | +-FS + // | |||||| | | +-MPP + // | |||||| | | | +-SPP + // | |||||| | | | |+-MPIE + // | |||||| | | | || +-UPIE + // | ||||||/|/|/| || |+-MIE + // | ||||||/|/|/| || || +-UIE + return 0b00000000000000000001100010011001; } #endif } @@ -186,7 +190,8 @@ public: template class hart_state::value>::type> { public: BEGIN_BF_DECL(mstatus_t, T); - // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11))) + // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR + // XS==11))) BF_FIELD(SD, 63, 1); // value of XLEN for S-mode BF_FIELD(SXL, 34, 2); @@ -204,7 +209,8 @@ public: BF_FIELD(SUM, 18, 1); // Modify PRiVilege BF_FIELD(MPRV, 17, 1); - // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None dirty, some clean/Some dirty + // status of additional user-mode extensions and associated state, All off/None dirty or clean, some on/None + // dirty, some clean/Some dirty BF_FIELD(XS, 15, 2); // floating-point unit status Off/Initial/Clean/Dirty BF_FIELD(FS, 13, 2); @@ -240,25 +246,26 @@ public: #if __cplusplus < 201402L return priv_lvl == PRIV_U ? 0x011ULL : priv_lvl == PRIV_S ? 0x000de133ULL : 0x007ff9ddULL; #else - switch (priv_lvl) { - case PRIV_U: return 0x00000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001 + switch(priv_lvl) { + case PRIV_U: + return 0x00000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001 default: - // +-SD - // | +-TSR - // | |+-TW - // | ||+-TVM - // | |||+-MXR - // | ||||+-SUM - // | |||||+-MPRV - // | |||||| +-XS - // | |||||| | +-FS - // | |||||| | | +-MPP - // | |||||| | | | +-SPP - // | |||||| | | | |+-MPIE - // | |||||| | | | || +-UPIE - // | ||||||/|/|/| || |+-MIE - // | ||||||/|/|/| || || +-UIE - return 0b00000000000000000001100010011001; + // +-SD + // | +-TSR + // | |+-TW + // | ||+-TVM + // | |||+-MXR + // | ||||+-SUM + // | |||||+-MPRV + // | |||||| +-XS + // | |||||| | +-FS + // | |||||| | | +-MPP + // | |||||| | | | +-SPP + // | |||||| | | | |+-MPIE + // | |||||| | | | || +-UPIE + // | ||||||/|/|/| || |+-MIE + // | ||||||/|/|/| || || +-UIE + return 0b00000000000000000001100010011001; } #endif } @@ -271,56 +278,49 @@ public: 0b000100010001, // U mode 0b001100110011, // S mode 0, - 0b100110011001 // M mode + 0b100110011001 // M mode }}; return m[mode]; } - constexpr bool has_compressed() { - return traits::MISA_VAL&0b0100; - } - constexpr reg_t get_pc_mask() { - return has_compressed()?~1:~3; - } + constexpr bool has_compressed() { return traits::MISA_VAL & 0b0100; } + constexpr reg_t get_pc_mask() { return has_compressed() ? ~1 : ~3; } riscv_hart_mu_p(feature_config cfg = feature_config{}); - + virtual ~riscv_hart_mu_p() = default; void reset(uint64_t address) override; std::pair load_file(std::string name, int type = -1) override; - iss::status read(const address_type type, const access_type access, const uint32_t space, - const uint64_t addr, const unsigned length, uint8_t *const data) override; - iss::status write(const address_type type, const access_type access, const uint32_t space, - const uint64_t addr, const unsigned length, const uint8_t *const data) override; + iss::status read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, + uint8_t* const data) override; + iss::status write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, const unsigned length, + const uint8_t* const data) override; uint64_t enter_trap(uint64_t flags) override { return riscv_hart_mu_p::enter_trap(flags, fault_data, fault_data); } uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override; uint64_t leave_trap(uint64_t flags) override; - const reg_t& get_mhartid() const { return mhartid_reg; } - void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; }; + const reg_t& get_mhartid() const { return mhartid_reg; } + void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; }; void disass_output(uint64_t pc, const std::string instr) override { - CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", - pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.icount + cycle_offset); + CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, + this->reg.icount + cycle_offset); }; - iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; } + iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; } - void set_csr(unsigned addr, reg_t val){ - csr[addr & csr.page_addr_mask] = val; - } + void set_csr(unsigned addr, reg_t val) { csr[addr & csr.page_addr_mask] = val; } + + void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); } - void set_irq_num(unsigned i) { - mcause_max_irq=1< &arch) + riscv_instrumentation_if(riscv_hart_mu_p& arch) : arch(arch) {} /** * get the name of this architecture @@ -345,20 +345,20 @@ protected: bool is_branch_taken() override { return arch.reg.last_branch; } - unsigned get_reg_num() override {return traits::NUM_REGS; } + unsigned get_reg_num() override { return traits::NUM_REGS; } - riscv_hart_mu_p &arch; + riscv_hart_mu_p& arch; }; friend struct riscv_instrumentation_if; - virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data); - virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data); + virtual iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t* const data); + virtual iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t* const data); - iss::status read_clic(uint64_t addr, unsigned length, uint8_t *const data); - iss::status write_clic(uint64_t addr, unsigned length, const uint8_t *const data); + iss::status read_clic(uint64_t addr, unsigned length, uint8_t* const data); + iss::status write_clic(uint64_t addr, unsigned length, const uint8_t* const data); - virtual iss::status read_csr(unsigned addr, reg_t &val); + virtual iss::status read_csr(unsigned addr, reg_t& val); virtual iss::status write_csr(unsigned addr, reg_t val); hart_state_type state; @@ -385,7 +385,7 @@ protected: uint8_t clic_cfg_reg{0}; std::array clic_inttrig_reg; union clic_int_reg_t { - struct{ + struct { uint8_t ip; uint8_t ie; uint8_t attr; @@ -399,46 +399,42 @@ protected: std::vector tcm; - iss::status read_csr_reg(unsigned addr, reg_t &val); + iss::status read_csr_reg(unsigned addr, reg_t& val); iss::status write_csr_reg(unsigned addr, reg_t val); - iss::status read_null(unsigned addr, reg_t &val); - iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;} - iss::status read_cycle(unsigned addr, reg_t &val); + iss::status read_null(unsigned addr, reg_t& val); + iss::status write_null(unsigned addr, reg_t val) { return iss::status::Ok; } + iss::status read_cycle(unsigned addr, reg_t& val); iss::status write_cycle(unsigned addr, reg_t val); - iss::status read_instret(unsigned addr, reg_t &val); + iss::status read_instret(unsigned addr, reg_t& val); iss::status write_instret(unsigned addr, reg_t val); - iss::status read_tvec(unsigned addr, reg_t &val); - iss::status read_time(unsigned addr, reg_t &val); - iss::status read_status(unsigned addr, reg_t &val); + iss::status read_tvec(unsigned addr, reg_t& val); + iss::status read_time(unsigned addr, reg_t& val); + iss::status read_status(unsigned addr, reg_t& val); iss::status write_status(unsigned addr, reg_t val); - iss::status read_cause(unsigned addr, reg_t &val); + iss::status read_cause(unsigned addr, reg_t& val); iss::status write_cause(unsigned addr, reg_t val); - iss::status read_ie(unsigned addr, reg_t &val); + iss::status read_ie(unsigned addr, reg_t& val); iss::status write_ie(unsigned addr, reg_t val); - iss::status read_ip(unsigned addr, reg_t &val); + iss::status read_ip(unsigned addr, reg_t& val); iss::status write_ideleg(unsigned addr, reg_t val); iss::status write_edeleg(unsigned addr, reg_t val); - iss::status read_hartid(unsigned addr, reg_t &val); + iss::status read_hartid(unsigned addr, reg_t& val); iss::status write_epc(unsigned addr, reg_t val); iss::status read_intstatus(unsigned addr, reg_t& val); iss::status write_intthresh(unsigned addr, reg_t val); iss::status write_xtvt(unsigned addr, reg_t val); iss::status write_dcsr_dcsr(unsigned addr, reg_t val); - iss::status read_dcsr_reg(unsigned addr, reg_t &val); + iss::status read_dcsr_reg(unsigned addr, reg_t& val); iss::status write_dcsr_reg(unsigned addr, reg_t val); - iss::status read_dpc_reg(unsigned addr, reg_t &val); + iss::status read_dpc_reg(unsigned addr, reg_t& val); iss::status write_dpc_reg(unsigned addr, reg_t val); iss::status write_pmpcfg_reg(unsigned addr, reg_t val); - virtual iss::status read_custom_csr_reg(unsigned addr, reg_t &val) {return iss::status::Err;}; - virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) {return iss::status::Err;}; + virtual iss::status read_custom_csr_reg(unsigned addr, reg_t& val) { return iss::status::Err; }; + virtual iss::status write_custom_csr_reg(unsigned addr, reg_t val) { return iss::status::Err; }; - void register_custom_csr_rd(unsigned addr){ - csr_rd_cb[addr] = &this_class::read_custom_csr_reg; - } - void register_custom_csr_wr(unsigned addr){ - csr_wr_cb[addr] = &this_class::write_custom_csr_reg; - } + void register_custom_csr_rd(unsigned addr) { csr_rd_cb[addr] = &this_class::read_custom_csr_reg; } + void register_custom_csr_wr(unsigned addr) { csr_wr_cb[addr] = &this_class::write_custom_csr_reg; } reg_t mhartid_reg{0x0}; @@ -449,11 +445,11 @@ protected: std::vector> memfn_write; void insert_mem_range(uint64_t, uint64_t, std::function, std::function); feature_config cfg; - uint64_t mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16}; - inline bool debug_mode_active() {return this->reg.PRIV&0x4;} + uint64_t mcause_max_irq{(FEAT & features_e::FEAT_CLIC) ? 4096 : 16}; + inline bool debug_mode_active() { return this->reg.PRIV & 0x4; } - std::pair, std::function> - replace_mem_access(std::function rd, std::function wr){ + std::pair, std::function> replace_mem_access(std::function rd, + std::function wr) { std::pair, std::function> ret{hart_mem_rd_delegate, hart_mem_wr_delegate}; hart_mem_rd_delegate = rd; hart_mem_wr_delegate = wr; @@ -475,55 +471,70 @@ riscv_hart_mu_p::riscv_hart_mu_p(feature_config cfg) csr[mimpid] = 1; uart_buf.str(""); - for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){ + for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) { csr_rd_cb[addr] = &this_class::read_null; csr_wr_cb[addr] = &this_class::write_csr_reg; } - if(traits::XLEN==32) for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){ + if(traits::XLEN == 32) + for(unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr) { + csr_rd_cb[addr] = &this_class::read_null; + csr_wr_cb[addr] = &this_class::write_csr_reg; + } + for(unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr) { csr_rd_cb[addr] = &this_class::read_null; csr_wr_cb[addr] = &this_class::write_csr_reg; } - for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){ - csr_rd_cb[addr] = &this_class::read_null; - csr_wr_cb[addr] = &this_class::write_csr_reg; - } - for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){ + for(unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr) { csr_rd_cb[addr] = &this_class::read_null; } - if(traits::XLEN==32) for (unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr){ - csr_rd_cb[addr] = &this_class::read_null; - //csr_wr_cb[addr] = &this_class::write_csr_reg; - } + if(traits::XLEN == 32) + for(unsigned addr = hpmcounter3h; addr <= hpmcounter31h; ++addr) { + csr_rd_cb[addr] = &this_class::read_null; + // csr_wr_cb[addr] = &this_class::write_csr_reg; + } // common regs const std::array roaddrs{{misa, mvendorid, marchid, mimpid}}; - for(auto addr: roaddrs) { + for(auto addr : roaddrs) { csr_rd_cb[addr] = &this_class::read_csr_reg; csr_wr_cb[addr] = &this_class::write_null; } const std::array rwaddrs{{ - mepc, mtvec, mscratch, mtval, - uepc, utvec, uscratch, utval, + mepc, + mtvec, + mscratch, + mtval, + uepc, + utvec, + uscratch, + utval, }}; - for(auto addr: rwaddrs) { + for(auto addr : rwaddrs) { csr_rd_cb[addr] = &this_class::read_csr_reg; csr_wr_cb[addr] = &this_class::write_csr_reg; } // special handling & overrides csr_rd_cb[time] = &this_class::read_time; - if(traits::XLEN==32) csr_rd_cb[timeh] = &this_class::read_time; + if(traits::XLEN == 32) + csr_rd_cb[timeh] = &this_class::read_time; csr_rd_cb[cycle] = &this_class::read_cycle; - if(traits::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle; + if(traits::XLEN == 32) + csr_rd_cb[cycleh] = &this_class::read_cycle; csr_rd_cb[instret] = &this_class::read_instret; - if(traits::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret; + if(traits::XLEN == 32) + csr_rd_cb[instreth] = &this_class::read_instret; csr_rd_cb[mcycle] = &this_class::read_cycle; csr_wr_cb[mcycle] = &this_class::write_cycle; - if(traits::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle; - if(traits::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle; + if(traits::XLEN == 32) + csr_rd_cb[mcycleh] = &this_class::read_cycle; + if(traits::XLEN == 32) + csr_wr_cb[mcycleh] = &this_class::write_cycle; csr_rd_cb[minstret] = &this_class::read_instret; csr_wr_cb[minstret] = &this_class::write_instret; - if(traits::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret; - if(traits::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret; + if(traits::XLEN == 32) + csr_rd_cb[minstreth] = &this_class::read_instret; + if(traits::XLEN == 32) + csr_wr_cb[minstreth] = &this_class::write_instret; csr_rd_cb[mstatus] = &this_class::read_status; csr_wr_cb[mstatus] = &this_class::write_status; csr_rd_cb[mcause] = &this_class::read_cause; @@ -542,17 +553,17 @@ riscv_hart_mu_p::riscv_hart_mu_p(feature_config cfg) csr_wr_cb[marchid] = &this_class::write_null; csr_wr_cb[mimpid] = &this_class::write_null; - if(FEAT & FEAT_PMP){ - for(size_t i=pmpaddr0; i<=pmpaddr15; ++i){ + if(FEAT & FEAT_PMP) { + for(size_t i = pmpaddr0; i <= pmpaddr15; ++i) { csr_rd_cb[i] = &this_class::read_csr_reg; csr_wr_cb[i] = &this_class::write_csr_reg; } - for(size_t i=pmpcfg0; i::riscv_hart_mu_p(feature_config cfg) if(FEAT & FEAT_CLIC) { csr_rd_cb[mtvt] = &this_class::read_csr_reg; csr_wr_cb[mtvt] = &this_class::write_xtvt; -// csr_rd_cb[mxnti] = &this_class::read_csr_reg; -// csr_wr_cb[mxnti] = &this_class::write_csr_reg; + // csr_rd_cb[mxnti] = &this_class::read_csr_reg; + // csr_wr_cb[mxnti] = &this_class::write_csr_reg; csr_rd_cb[mintstatus] = &this_class::read_intstatus; csr_wr_cb[mintstatus] = &this_class::write_null; -// csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg; -// csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg; -// csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg; -// csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg; + // csr_rd_cb[mscratchcsw] = &this_class::read_csr_reg; + // csr_wr_cb[mscratchcsw] = &this_class::write_csr_reg; + // csr_rd_cb[mscratchcswl] = &this_class::read_csr_reg; + // csr_wr_cb[mscratchcswl] = &this_class::write_csr_reg; csr_rd_cb[mintthresh] = &this_class::read_csr_reg; csr_wr_cb[mintthresh] = &this_class::write_intthresh; - if(FEAT & FEAT_EXT_N){ + if(FEAT & FEAT_EXT_N) { csr_rd_cb[utvt] = &this_class::read_csr_reg; csr_wr_cb[utvt] = &this_class::write_xtvt; csr_rd_cb[uintstatus] = &this_class::read_intstatus; @@ -589,31 +600,32 @@ riscv_hart_mu_p::riscv_hart_mu_p(feature_config cfg) csr_rd_cb[uintthresh] = &this_class::read_csr_reg; csr_wr_cb[uintthresh] = &this_class::write_intthresh; } - clic_int_reg.resize(cfg.clic_num_irq, clic_int_reg_t{.raw=0}); - clic_cfg_reg=0x30; - clic_mact_lvl = clic_mprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1; - clic_uact_lvl = clic_uprev_lvl = (1<<(cfg.clic_int_ctl_bits)) - 1; - csr[mintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1; - csr[uintthresh] = (1<<(cfg.clic_int_ctl_bits)) - 1; - insert_mem_range(cfg.clic_base, 0x5000UL, - [this](phys_addr_t addr, unsigned length, uint8_t * const data) { return read_clic(addr.val, length, data);}, - [this](phys_addr_t addr, unsigned length, uint8_t const * const data) {return write_clic(addr.val, length, data);}); + clic_int_reg.resize(cfg.clic_num_irq, clic_int_reg_t{.raw = 0}); + clic_cfg_reg = 0x30; + clic_mact_lvl = clic_mprev_lvl = (1 << (cfg.clic_int_ctl_bits)) - 1; + clic_uact_lvl = clic_uprev_lvl = (1 << (cfg.clic_int_ctl_bits)) - 1; + csr[mintthresh] = (1 << (cfg.clic_int_ctl_bits)) - 1; + csr[uintthresh] = (1 << (cfg.clic_int_ctl_bits)) - 1; + insert_mem_range( + cfg.clic_base, 0x5000UL, + [this](phys_addr_t addr, unsigned length, uint8_t* const data) { return read_clic(addr.val, length, data); }, + [this](phys_addr_t addr, unsigned length, uint8_t const* const data) { return write_clic(addr.val, length, data); }); } if(FEAT & FEAT_TCM) { tcm.resize(cfg.tcm_size); - std::function read_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t * const data) { - auto offset=addr.val-this->cfg.tcm_base; + std::function read_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t* const data) { + auto offset = addr.val - this->cfg.tcm_base; std::copy(tcm.data() + offset, tcm.data() + offset + length, data); return iss::Ok; }; - std::function write_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t const * const data) { - auto offset=addr.val-this->cfg.tcm_base; + std::function write_clic_cb = [this](phys_addr_t addr, unsigned length, uint8_t const* const data) { + auto offset = addr.val - this->cfg.tcm_base; std::copy(data, data + length, tcm.data() + offset); return iss::Ok; }; insert_mem_range(cfg.tcm_base, cfg.tcm_size, read_clic_cb, write_clic_cb); } - if(FEAT & FEAT_DEBUG){ + if(FEAT & FEAT_DEBUG) { csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg; csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg; csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg; @@ -623,255 +635,253 @@ riscv_hart_mu_p::riscv_hart_mu_p(feature_config cfg) csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr; csr_rd_cb[dcsr] = &this_class::read_dcsr_reg; } - hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { - return this->read_mem(a, l, d); - }; - hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { - return this->write_mem(a, l, d); - }; + hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return this->read_mem(a, l, d); }; + hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return this->write_mem(a, l, d); }; } template std::pair riscv_hart_mu_p::load_file(std::string name, int type) { - FILE *fp = fopen(name.c_str(), "r"); - if (fp) { + FILE* fp = fopen(name.c_str(), "r"); + if(fp) { std::array buf; auto n = fread(buf.data(), 1, 4, fp); fclose(fp); - if (n != 4) throw std::runtime_error("input file has insufficient size"); + if(n != 4) + throw std::runtime_error("input file has insufficient size"); buf[4] = 0; - if (strcmp(buf.data() + 1, "ELF") == 0) { + if(strcmp(buf.data() + 1, "ELF") == 0) { // Create elfio reader ELFIO::elfio reader; // Load ELF data - if (!reader.load(name)) throw std::runtime_error("could not process elf file"); + if(!reader.load(name)) + throw std::runtime_error("could not process elf file"); // check elf properties - if (reader.get_class() != ELFCLASS32) - if (sizeof(reg_t) == 4) throw std::runtime_error("wrong elf class in file"); - if (reader.get_type() != ET_EXEC) throw std::runtime_error("wrong elf type in file"); - if (reader.get_machine() != EM_RISCV) throw std::runtime_error("wrong elf machine in file"); + if(reader.get_class() != ELFCLASS32) + if(sizeof(reg_t) == 4) + throw std::runtime_error("wrong elf class in file"); + if(reader.get_type() != ET_EXEC) + throw std::runtime_error("wrong elf type in file"); + if(reader.get_machine() != EM_RISCV) + throw std::runtime_error("wrong elf machine in file"); auto entry = reader.get_entry(); - for (const auto pseg : reader.segments) { + for(const auto pseg : reader.segments) { const auto fsize = pseg->get_file_size(); // 0x42c/0x0 const auto seg_data = pseg->get_data(); - if (fsize > 0) { - auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, - traits::MEM, pseg->get_physical_address(), - fsize, reinterpret_cast(seg_data)); - if (res != iss::Ok) - LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex - << pseg->get_physical_address(); + if(fsize > 0) { + auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits::MEM, + pseg->get_physical_address(), fsize, reinterpret_cast(seg_data)); + if(res != iss::Ok) + LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); } } for(const auto sec : reader.sections) { if(sec->get_name() == ".symtab") { - if ( SHT_SYMTAB == sec->get_type() || - SHT_DYNSYM == sec->get_type() ) { - ELFIO::symbol_section_accessor symbols( reader, sec ); + if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) { + ELFIO::symbol_section_accessor symbols(reader, sec); auto sym_no = symbols.get_symbols_num(); - std::string name; - ELFIO::Elf64_Addr value = 0; - ELFIO::Elf_Xword size = 0; - unsigned char bind = 0; - unsigned char type = 0; - ELFIO::Elf_Half section = 0; - unsigned char other = 0; - for ( auto i = 0U; i < sym_no; ++i ) { - symbols.get_symbol( i, name, value, size, bind, type, section, other ); - if(name=="tohost") { + std::string name; + ELFIO::Elf64_Addr value = 0; + ELFIO::Elf_Xword size = 0; + unsigned char bind = 0; + unsigned char type = 0; + ELFIO::Elf_Half section = 0; + unsigned char other = 0; + for(auto i = 0U; i < sym_no; ++i) { + symbols.get_symbol(i, name, value, size, bind, type, section, other); + if(name == "tohost") { tohost = value; - } else if(name=="fromhost") { + } else if(name == "fromhost") { fromhost = value; } } } - } else if (sec->get_name() == ".tohost") { + } else if(sec->get_name() == ".tohost") { tohost = sec->get_address(); fromhost = tohost + 0x40; } - } return std::make_pair(entry, true); } - throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file",name)); + throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name)); } throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name)); } -template +template inline void riscv_hart_mu_p::insert_mem_range(uint64_t base, uint64_t size, std::function rd_f, - std::function wr_fn) { + std::function wr_fn) { std::tuple entry{base, size}; - auto it = std::upper_bound( memfn_range.begin(), memfn_range.end(), entry, - [](std::tuple const& a, std::tuple const& b){ - return std::get<0>(a)(b); - }); + auto it = std::upper_bound( + memfn_range.begin(), memfn_range.end(), entry, + [](std::tuple const& a, std::tuple const& b) { return std::get<0>(a) < std::get<0>(b); }); auto idx = std::distance(memfn_range.begin(), it); memfn_range.insert(it, entry); - memfn_read.insert(std::begin(memfn_read)+idx, rd_f); - memfn_write.insert(std::begin(memfn_write)+idx, wr_fn); + memfn_read.insert(std::begin(memfn_read) + idx, rd_f); + memfn_write.insert(std::begin(memfn_write) + idx, wr_fn); } -template -inline iss::status riscv_hart_mu_p::write_pmpcfg_reg(unsigned addr, reg_t val) { +template inline iss::status riscv_hart_mu_p::write_pmpcfg_reg(unsigned addr, reg_t val) { csr[addr] = val & 0x9f9f9f9f; return iss::Ok; } -template bool riscv_hart_mu_p::pmp_check(const access_type type, const uint64_t addr, const unsigned len) { - constexpr auto PMP_SHIFT=2U; +template +bool riscv_hart_mu_p::pmp_check(const access_type type, const uint64_t addr, const unsigned len) { + constexpr auto PMP_SHIFT = 2U; constexpr auto PMP_R = 0x1U; constexpr auto PMP_W = 0x2U; constexpr auto PMP_X = 0x4U; constexpr auto PMP_A = 0x18U; constexpr auto PMP_L = 0x80U; - constexpr auto PMP_TOR =0x1U; - constexpr auto PMP_NA4 =0x2U; - constexpr auto PMP_NAPOT =0x3U; + constexpr auto PMP_TOR = 0x1U; + constexpr auto PMP_NA4 = 0x2U; + constexpr auto PMP_NAPOT = 0x3U; reg_t base = 0; auto any_active = false; - auto const cfg_reg_size=sizeof(reg_t); - for (size_t i = 0; i < 16; i++) { - reg_t tor = csr[pmpaddr0+i] << PMP_SHIFT; - uint8_t cfg = csr[pmpcfg0+(i/cfg_reg_size)]>>(i%cfg_reg_size); - if (cfg & PMP_A) { - any_active=true; + auto const cfg_reg_size = sizeof(reg_t); + for(size_t i = 0; i < 16; i++) { + reg_t tor = csr[pmpaddr0 + i] << PMP_SHIFT; + uint8_t cfg = csr[pmpcfg0 + (i / cfg_reg_size)] >> (i % cfg_reg_size); + if(cfg & PMP_A) { + any_active = true; auto pmp_a = (cfg & PMP_A) >> 3; auto is_tor = pmp_a == PMP_TOR; auto is_na4 = pmp_a == PMP_NA4; - reg_t mask = (csr[pmpaddr0+i] << 1) | (!is_na4); + reg_t mask = (csr[pmpaddr0 + i] << 1) | (!is_na4); mask = ~(mask & ~(mask + 1)) << PMP_SHIFT; // Check each 4-byte sector of the access auto any_match = false; auto all_match = true; - for (reg_t offset = 0; offset < len; offset += 1 << PMP_SHIFT) { + for(reg_t offset = 0; offset < len; offset += 1 << PMP_SHIFT) { reg_t cur_addr = addr + offset; auto napot_match = ((cur_addr ^ tor) & mask) == 0; - auto tor_match = base <= (cur_addr+len-1) && cur_addr < tor; + auto tor_match = base <= (cur_addr + len - 1) && cur_addr < tor; auto match = is_tor ? tor_match : napot_match; any_match |= match; all_match &= match; } - if (any_match) { + if(any_match) { // If the PMP matches only a strict subset of the access, fail it - if (!all_match) + if(!all_match) return false; - return (this->reg.PRIV == PRIV_M && !(cfg & PMP_L)) || - (type == access_type::READ && (cfg & PMP_R)) || - (type == access_type::WRITE && (cfg & PMP_W)) || - (type == access_type::FETCH && (cfg & PMP_X)); + return (this->reg.PRIV == PRIV_M && !(cfg & PMP_L)) || (type == access_type::READ && (cfg & PMP_R)) || + (type == access_type::WRITE && (cfg & PMP_W)) || (type == access_type::FETCH && (cfg & PMP_X)); } } base = tor; } -// constexpr auto pmp_num_regs = 16; -// reg_t tor_base = 0; -// auto any_active = false; -// auto lower_addr = addr >>2; -// auto upper_addr = (addr+len-1)>>2; -// for (size_t i = 0; i < pmp_num_regs; i++) { -// uint8_t cfg = csr[pmpcfg0+(i/4)]>>(i%4); -// uint8_t cfg_next = i==(pmp_num_regs-1)? 0 : csr[pmpcfg0+((i+1)/4)]>>((i+1)%4); -// auto pmpaddr = csr[pmpaddr0+i]; -// if (cfg & PMP_A) { -// any_active=true; -// auto is_tor = bit_sub<3, 2>(cfg) == PMP_TOR; -// auto is_napot = bit_sub<4, 1>(cfg) && bit_sub<3, 2>(cfg_next)!= PMP_TOR; -// if(is_napot) { -// reg_t mask = bit_sub<3, 1>(cfg)?~( pmpaddr & ~(pmpaddr + 1)): 0x3fffffff; -// auto mpmpaddr = pmpaddr & mask; -// if((lower_addr&mask) == mpmpaddr && (upper_addr&mask)==mpmpaddr) -// return (this->reg.PRIV == PRIV_M && !(cfg & PMP_L)) || -// (type == access_type::READ && (cfg & PMP_R)) || -// (type == access_type::WRITE && (cfg & PMP_W)) || -// (type == access_type::FETCH && (cfg & PMP_X)); -// } else if(is_tor) { -// if(lower_addr>=tor_base && upper_addr<=pmpaddr) -// return (this->reg.PRIV == PRIV_M && !(cfg & PMP_L)) || -// (type == access_type::READ && (cfg & PMP_R)) || -// (type == access_type::WRITE && (cfg & PMP_W)) || -// (type == access_type::FETCH && (cfg & PMP_X)); -// } -// } -// tor_base = pmpaddr; -// } + // constexpr auto pmp_num_regs = 16; + // reg_t tor_base = 0; + // auto any_active = false; + // auto lower_addr = addr >>2; + // auto upper_addr = (addr+len-1)>>2; + // for (size_t i = 0; i < pmp_num_regs; i++) { + // uint8_t cfg = csr[pmpcfg0+(i/4)]>>(i%4); + // uint8_t cfg_next = i==(pmp_num_regs-1)? 0 : csr[pmpcfg0+((i+1)/4)]>>((i+1)%4); + // auto pmpaddr = csr[pmpaddr0+i]; + // if (cfg & PMP_A) { + // any_active=true; + // auto is_tor = bit_sub<3, 2>(cfg) == PMP_TOR; + // auto is_napot = bit_sub<4, 1>(cfg) && bit_sub<3, 2>(cfg_next)!= PMP_TOR; + // if(is_napot) { + // reg_t mask = bit_sub<3, 1>(cfg)?~( pmpaddr & ~(pmpaddr + 1)): 0x3fffffff; + // auto mpmpaddr = pmpaddr & mask; + // if((lower_addr&mask) == mpmpaddr && (upper_addr&mask)==mpmpaddr) + // return (this->reg.PRIV == PRIV_M && !(cfg & PMP_L)) || + // (type == access_type::READ && (cfg & PMP_R)) || + // (type == access_type::WRITE && (cfg & PMP_W)) || + // (type == access_type::FETCH && (cfg & PMP_X)); + // } else if(is_tor) { + // if(lower_addr>=tor_base && upper_addr<=pmpaddr) + // return (this->reg.PRIV == PRIV_M && !(cfg & PMP_L)) || + // (type == access_type::READ && (cfg & PMP_R)) || + // (type == access_type::WRITE && (cfg & PMP_W)) || + // (type == access_type::FETCH && (cfg & PMP_X)); + // } + // } + // tor_base = pmpaddr; + // } return !any_active || this->reg.PRIV == PRIV_M; } - template -iss::status riscv_hart_mu_p::read(const address_type type, const access_type access, const uint32_t space, - const uint64_t addr, const unsigned length, uint8_t *const data) { +iss::status riscv_hart_mu_p::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, + const unsigned length, uint8_t* const data) { #ifndef NDEBUG - if (access && iss::access_type::DEBUG) { + if(access && iss::access_type::DEBUG) { LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; - } else if(is_fetch(access)){ + } else if(is_fetch(access)) { LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; } else { LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; - } + } #endif try { - switch (space) { + switch(space) { case traits::MEM: { - if(FEAT & FEAT_PMP){ + if(FEAT & FEAT_PMP) { if(!pmp_check(access, addr, length) && !is_debug(access)) { fault_data = addr; - if (is_debug(access)) throw trap_access(0, addr); - this->reg.trap_state = (1UL << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1 + if(is_debug(access)) + throw trap_access(0, addr); + this->reg.trap_state = (1UL << 31) | ((access == access_type::FETCH ? 1 : 5) << 16); // issue trap 1 return iss::Err; } } - auto alignment = is_fetch(access)? (has_compressed()? 2 : 4) : length; - if (unlikely(is_fetch(access) && (addr&(alignment-1)))) { + auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : length; + if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) { fault_data = addr; - if (is_debug(access)) throw trap_access(0, addr); + if(is_debug(access)) + throw trap_access(0, addr); this->reg.trap_state = (1UL << 31); // issue trap 0 return iss::Err; } try { - if(!is_debug(access) && (addr&(alignment-1))){ - this->reg.trap_state = (1UL << 31) | 4<<16; - fault_data=addr; + if(!is_debug(access) && (addr & (alignment - 1))) { + this->reg.trap_state = (1UL << 31) | 4 << 16; + fault_data = addr; return iss::Err; } phys_addr_t phys_addr{access, space, addr}; auto res = iss::Err; - if(!is_fetch(access) && memfn_range.size()){ - auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple const& a){ - return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val; - }); - if(it!=std::end(memfn_range)) { + if(!is_fetch(access) && memfn_range.size()) { + auto it = + std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple const& a) { + return std::get<0>(a) <= phys_addr.val && (std::get<0>(a) + std::get<1>(a)) > phys_addr.val; + }); + if(it != std::end(memfn_range)) { auto idx = std::distance(std::begin(memfn_range), it); res = memfn_read[idx](phys_addr, length, data); } else - res = hart_mem_rd_delegate( phys_addr, length, data); + res = hart_mem_rd_delegate(phys_addr, length, data); } else { - res = hart_mem_rd_delegate( phys_addr, length, data); + res = hart_mem_rd_delegate(phys_addr, length, data); } - if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)){ + if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) { this->reg.trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault - fault_data=addr; + fault_data = addr; } return res; - } catch (trap_access &ta) { + } catch(trap_access& ta) { this->reg.trap_state = (1UL << 31) | ta.id; - fault_data=ta.addr; + fault_data = ta.addr; return iss::Err; } } break; case traits::CSR: { - if (length != sizeof(reg_t)) return iss::Err; - return read_csr(addr, *reinterpret_cast(data)); + if(length != sizeof(reg_t)) + return iss::Err; + return read_csr(addr, *reinterpret_cast(data)); } break; case traits::FENCE: { - if ((addr + length) > mem.size()) return iss::Err; + if((addr + length) > mem.size()) + return iss::Err; return iss::Ok; } break; case traits::RES: { auto it = atomic_reservation.find(addr); - if (it != atomic_reservation.end() && it->second != 0) { + if(it != atomic_reservation.end() && it->second != 0) { memset(data, 0xff, length); atomic_reservation.erase(addr); } else @@ -881,93 +891,97 @@ iss::status riscv_hart_mu_p::read(const address_type type, const acc return iss::Err; // assert("Not supported"); } return iss::Ok; - } catch (trap_access &ta) { + } catch(trap_access& ta) { this->reg.trap_state = (1UL << 31) | ta.id; - fault_data=ta.addr; + fault_data = ta.addr; return iss::Err; } } template -iss::status riscv_hart_mu_p::write(const address_type type, const access_type access, const uint32_t space, - const uint64_t addr, const unsigned length, const uint8_t *const data) { +iss::status riscv_hart_mu_p::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, + const unsigned length, const uint8_t* const data) { #ifndef NDEBUG - const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; - switch (length) { + const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; + switch(length) { case 8: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec - << ") @addr 0x" << std::hex << addr; + LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" + << std::hex << addr; break; case 4: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t *)&data[0] << std::dec - << ") @addr 0x" << std::hex << addr; + LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" + << std::hex << addr; break; case 2: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t *)&data[0] << std::dec - << ") @addr 0x" << std::hex << addr; + LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" + << std::hex << addr; break; case 1: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec - << ") @addr 0x" << std::hex << addr; + LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" + << std::hex << addr; break; default: LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; } #endif try { - switch (space) { + switch(space) { case traits::MEM: { - if(FEAT & FEAT_PMP){ - if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) { + if(FEAT & FEAT_PMP) { + if(!pmp_check(access, addr, length) && (access & access_type::DEBUG) != access_type::DEBUG) { fault_data = addr; - if (access && iss::access_type::DEBUG) throw trap_access(0, addr); + if(access && iss::access_type::DEBUG) + throw trap_access(0, addr); this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 1 return iss::Err; } } - if (unlikely(is_fetch(access) && (addr & 0x1) == 1)) { + if(unlikely(is_fetch(access) && (addr & 0x1) == 1)) { fault_data = addr; - if (access && iss::access_type::DEBUG) throw trap_access(0, addr); + if(access && iss::access_type::DEBUG) + throw trap_access(0, addr); this->reg.trap_state = (1UL << 31); // issue trap 0 return iss::Err; } try { - if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){ - this->reg.trap_state = (1UL << 31) | 6<<16; - fault_data=addr; + if(length > 1 && (addr & (length - 1)) && (access & access_type::DEBUG) != access_type::DEBUG) { + this->reg.trap_state = (1UL << 31) | 6 << 16; + fault_data = addr; return iss::Err; } phys_addr_t phys_addr{access, space, addr}; auto res = iss::Err; - if(!is_fetch(access) && memfn_range.size()){ - auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple const& a){ - return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val; - }); - if(it!=std::end(memfn_range)) { + if(!is_fetch(access) && memfn_range.size()) { + auto it = + std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple const& a) { + return std::get<0>(a) <= phys_addr.val && (std::get<0>(a) + std::get<1>(a)) > phys_addr.val; + }); + if(it != std::end(memfn_range)) { auto idx = std::distance(std::begin(memfn_range), it); - res = memfn_write[idx]( phys_addr, length, data); + res = memfn_write[idx](phys_addr, length, data); } else - res = hart_mem_wr_delegate( phys_addr, length, data); + res = hart_mem_wr_delegate(phys_addr, length, data); } else { - res = hart_mem_wr_delegate( phys_addr, length, data); + res = hart_mem_wr_delegate(phys_addr, length, data); } - if (unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) { + if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) { this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault) - fault_data=addr; + fault_data = addr; } return res; - } catch (trap_access &ta) { + } catch(trap_access& ta) { this->reg.trap_state = (1UL << 31) | ta.id; - fault_data=ta.addr; + fault_data = ta.addr; return iss::Err; } - if ((addr + length) > mem.size()) return iss::Err; - switch (addr) { + if((addr + length) > mem.size()) + return iss::Err; + switch(addr) { case 0x10013000: // UART0 base, TXFIFO reg case 0x10023000: // UART1 base, TXFIFO reg uart_buf << (char)data[0]; - if (((char)data[0]) == '\n' || data[0] == 0) { + if(((char)data[0]) == '\n' || data[0] == 0) { // LOG(INFO)<<"UART"<<((addr>>16)&0x3)<<" send // '"<::write(const address_type type, const ac } return iss::Ok; case 0x10008000: { // HFROSC base, hfrosccfg reg - auto &p = mem(addr / mem.page_size); + auto& p = mem(addr / mem.page_size); auto offs = addr & mem.page_addr_mask; std::copy(data, data + length, p.data() + offs); - auto &x = *(p.data() + offs + 3); - if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1 + auto& x = *(p.data() + offs + 3); + if(x & 0x40) + x |= 0x80; // hfroscrdy = 1 if hfroscen==1 return iss::Ok; } case 0x10008008: { // HFROSC base, pllcfg reg - auto &p = mem(addr / mem.page_size); + auto& p = mem(addr / mem.page_size); auto offs = addr & mem.page_addr_mask; std::copy(data, data + length, p.data() + offs); - auto &x = *(p.data() + offs + 3); + auto& x = *(p.data() + offs + 3); x |= 0x80; // set pll lock upon writing return iss::Ok; } break; @@ -994,12 +1009,14 @@ iss::status riscv_hart_mu_p::write(const address_type type, const ac } } break; case traits::CSR: { - if (length != sizeof(reg_t)) return iss::Err; - return write_csr(addr, *reinterpret_cast(data)); + if(length != sizeof(reg_t)) + return iss::Err; + return write_csr(addr, *reinterpret_cast(data)); } break; case traits::FENCE: { - if ((addr + length) > mem.size()) return iss::Err; - switch (addr) { + if((addr + length) > mem.size()) + return iss::Err; + switch(addr) { case 2: case 3: { ptw.clear(); @@ -1015,43 +1032,45 @@ iss::status riscv_hart_mu_p::write(const address_type type, const ac return iss::Err; } return iss::Ok; - } catch (trap_access &ta) { + } catch(trap_access& ta) { this->reg.trap_state = (1UL << 31) | ta.id; - fault_data=ta.addr; + fault_data = ta.addr; return iss::Err; } } -template iss::status riscv_hart_mu_p::read_csr(unsigned addr, reg_t &val) { - if (addr >= csr.size()) return iss::Err; +template iss::status riscv_hart_mu_p::read_csr(unsigned addr, reg_t& val) { + if(addr >= csr.size()) + return iss::Err; auto req_priv_lvl = (addr >> 8) & 0x3; - if (this->reg.PRIV < req_priv_lvl) // not having required privileges + if(this->reg.PRIV < req_priv_lvl) // not having required privileges throw illegal_instruction_fault(this->fault_data); auto it = csr_rd_cb.find(addr); - if (it == csr_rd_cb.end() || !it->second) // non existent register + if(it == csr_rd_cb.end() || !it->second) // non existent register throw illegal_instruction_fault(this->fault_data); return (this->*(it->second))(addr, val); } template iss::status riscv_hart_mu_p::write_csr(unsigned addr, reg_t val) { - if (addr >= csr.size()) return iss::Err; + if(addr >= csr.size()) + return iss::Err; auto req_priv_lvl = (addr >> 8) & 0x3; - if (this->reg.PRIV < req_priv_lvl) // not having required privileges + if(this->reg.PRIV < req_priv_lvl) // not having required privileges throw illegal_instruction_fault(this->fault_data); - if((addr&0xc00)==0xc00) // writing to read-only region + if((addr & 0xc00) == 0xc00) // writing to read-only region throw illegal_instruction_fault(this->fault_data); auto it = csr_wr_cb.find(addr); - if (it == csr_wr_cb.end() || !it->second) // non existent register + if(it == csr_wr_cb.end() || !it->second) // non existent register throw illegal_instruction_fault(this->fault_data); return (this->*(it->second))(addr, val); } -template iss::status riscv_hart_mu_p::read_csr_reg(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_csr_reg(unsigned addr, reg_t& val) { val = csr[addr]; return iss::Ok; } -template iss::status riscv_hart_mu_p::read_null(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_null(unsigned addr, reg_t& val) { val = 0; return iss::Ok; } @@ -1061,69 +1080,70 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_mu_p::read_cycle(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_cycle(unsigned addr, reg_t& val) { auto cycle_val = this->reg.icount + cycle_offset; - if (addr == mcycle) { + if(addr == mcycle) { val = static_cast(cycle_val); - } else if (addr == mcycleh) { + } else if(addr == mcycleh) { val = static_cast(cycle_val >> 32); } return iss::Ok; } template iss::status riscv_hart_mu_p::write_cycle(unsigned addr, reg_t val) { - if (sizeof(typename traits::reg_t) != 4) { + if(sizeof(typename traits::reg_t) != 4) { mcycle_csr = static_cast(val); } else { - if (addr == mcycle) { + if(addr == mcycle) { mcycle_csr = (mcycle_csr & 0xffffffff00000000) + val; - } else { - mcycle_csr = (static_cast(val)<<32) + (mcycle_csr & 0xffffffff); + } else { + mcycle_csr = (static_cast(val) << 32) + (mcycle_csr & 0xffffffff); } } - cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around + cycle_offset = mcycle_csr - this->reg.icount; // TODO: relying on wrap-around return iss::Ok; } -template iss::status riscv_hart_mu_p::read_instret(unsigned addr, reg_t &val) { - if ((addr&0xff) == (minstret&0xff)) { +template iss::status riscv_hart_mu_p::read_instret(unsigned addr, reg_t& val) { + if((addr & 0xff) == (minstret & 0xff)) { val = static_cast(this->reg.instret); - } else if ((addr&0xff) == (minstreth&0xff)) { + } else if((addr & 0xff) == (minstreth & 0xff)) { val = static_cast(this->reg.instret >> 32); } return iss::Ok; } template iss::status riscv_hart_mu_p::write_instret(unsigned addr, reg_t val) { - if (sizeof(typename traits::reg_t) != 4) { + if(sizeof(typename traits::reg_t) != 4) { this->reg.instret = static_cast(val); } else { - if ((addr&0xff) == (minstret&0xff)) { + if((addr & 0xff) == (minstret & 0xff)) { this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val; - } else { - this->reg.instret = (static_cast(val)<<32) + (this->reg.instret & 0xffffffff); + } else { + this->reg.instret = (static_cast(val) << 32) + (this->reg.instret & 0xffffffff); } } this->reg.instret--; return iss::Ok; } -template iss::status riscv_hart_mu_p::read_time(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_time(unsigned addr, reg_t& val) { uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052; - if (addr == time) { + if(addr == time) { val = static_cast(time_val); - } else if (addr == timeh) { - if (sizeof(typename traits::reg_t) != 4) return iss::Err; + } else if(addr == timeh) { + if(sizeof(typename traits::reg_t) != 4) + return iss::Err; val = static_cast(time_val >> 32); } return iss::Ok; } -template iss::status riscv_hart_mu_p::read_tvec(unsigned addr, reg_t &val) { - val = FEAT & features_e::FEAT_CLIC? csr[addr] : csr[addr] & ~2; +template iss::status riscv_hart_mu_p::read_tvec(unsigned addr, reg_t& val) { + val = FEAT & features_e::FEAT_CLIC ? csr[addr] : csr[addr] & ~2; return iss::Ok; } -template iss::status riscv_hart_mu_p::read_status(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_status(unsigned addr, reg_t& val) { val = state.mstatus & hart_state_type::get_mask((addr >> 8) & 0x3); return iss::Ok; } @@ -1134,58 +1154,58 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_mu_p::read_cause(unsigned addr, reg_t &val) { - if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) { - val = csr[addr] & ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16)); +template iss::status riscv_hart_mu_p::read_cause(unsigned addr, reg_t& val) { + if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec] & 0x3) == 3) { + val = csr[addr] & ((1UL << (traits::XLEN - 1)) | (mcause_max_irq - 1) | (0xfUL << 16)); auto mode = (addr >> 8) & 0x3; switch(mode) { case 0: - val |= clic_uprev_lvl<<16; - val |= state.mstatus.UPIE<<27; + val |= clic_uprev_lvl << 16; + val |= state.mstatus.UPIE << 27; break; default: - val |= clic_mprev_lvl<<16; - val |= state.mstatus.MPIE<<27; - val |= state.mstatus.MPP<<28; + val |= clic_mprev_lvl << 16; + val |= state.mstatus.MPIE << 27; + val |= state.mstatus.MPP << 28; break; } } else - val = csr[addr] & ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1)); + val = csr[addr] & ((1UL << (traits::XLEN - 1)) | (mcause_max_irq - 1)); return iss::Ok; } template iss::status riscv_hart_mu_p::write_cause(unsigned addr, reg_t val) { - if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) { - auto mask = ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16)); + if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec] & 0x3) == 3) { + auto mask = ((1UL << (traits::XLEN - 1)) | (mcause_max_irq - 1) | (0xfUL << 16)); csr[addr] = (val & mask) | (csr[addr] & ~mask); auto mode = (addr >> 8) & 0x3; switch(mode) { case 0: - clic_uprev_lvl = ((val>>16)&0xff) | (1<<(8-cfg. clic_int_ctl_bits)) - 1; - state.mstatus.UPIE=(val>>27)&0x1; + clic_uprev_lvl = ((val >> 16) & 0xff) | (1 << (8 - cfg.clic_int_ctl_bits)) - 1; + state.mstatus.UPIE = (val >> 27) & 0x1; break; default: - clic_mprev_lvl = ((val>>16)&0xff) | (1<<(8-cfg. clic_int_ctl_bits)) - 1; - state.mstatus.MPIE=(val>>27)&0x1; - state.mstatus.MPP=(val>>28)&0x3; + clic_mprev_lvl = ((val >> 16) & 0xff) | (1 << (8 - cfg.clic_int_ctl_bits)) - 1; + state.mstatus.MPIE = (val >> 27) & 0x1; + state.mstatus.MPP = (val >> 28) & 0x3; break; } } else { - auto mask = ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1)); + auto mask = ((1UL << (traits::XLEN - 1)) | (mcause_max_irq - 1)); csr[addr] = (val & mask) | (csr[addr] & ~mask); } return iss::Ok; } -template iss::status riscv_hart_mu_p::read_hartid(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_hartid(unsigned addr, reg_t& val) { val = mhartid_reg; return iss::Ok; } -template iss::status riscv_hart_mu_p::read_ie(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_ie(unsigned addr, reg_t& val) { auto mask = get_irq_mask((addr >> 8) & 0x3); val = csr[mie] & mask; - if(this->reg.PRIV!=3) + if(this->reg.PRIV != 3) val &= csr[mideleg]; return iss::Ok; } @@ -1197,10 +1217,10 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_mu_p::read_ip(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_ip(unsigned addr, reg_t& val) { auto mask = get_irq_mask((addr >> 8) & 0x3); val = csr[mip] & mask; - if(this->reg.PRIV!=3) + if(this->reg.PRIV != 3) val &= csr[mideleg]; return iss::Ok; } @@ -1233,7 +1253,7 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_mu_p::read_dcsr_reg(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_dcsr_reg(unsigned addr, reg_t& val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); val = csr[addr]; @@ -1247,7 +1267,7 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_mu_p::read_dpc_reg(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_dpc_reg(unsigned addr, reg_t& val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); val = this->reg.DPC; @@ -1261,33 +1281,30 @@ template iss::status riscv_hart_mu_p -iss::status riscv_hart_mu_p::read_intstatus(unsigned addr, reg_t& val) { +template iss::status riscv_hart_mu_p::read_intstatus(unsigned addr, reg_t& val) { auto mode = (addr >> 8) & 0x3; - val = clic_uact_lvl&0xff; - if(mode==0x3) - val += (clic_mact_lvl&0xff) <<24; + val = clic_uact_lvl & 0xff; + if(mode == 0x3) + val += (clic_mact_lvl & 0xff) << 24; return iss::Ok; } -template -iss::status riscv_hart_mu_p::write_intthresh(unsigned addr, reg_t val) { - csr[addr]= (val &0xff) | (1<<(cfg.clic_int_ctl_bits)) - 1; +template iss::status riscv_hart_mu_p::write_intthresh(unsigned addr, reg_t val) { + csr[addr] = (val & 0xff) | (1 << (cfg.clic_int_ctl_bits)) - 1; return iss::Ok; } -template -iss::status riscv_hart_mu_p::write_xtvt(unsigned addr, reg_t val) { - csr[addr]= val & ~0x3fULL; +template iss::status riscv_hart_mu_p::write_xtvt(unsigned addr, reg_t val) { + csr[addr] = val & ~0x3fULL; return iss::Ok; } template -iss::status riscv_hart_mu_p::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) { - switch (paddr.val) { +iss::status riscv_hart_mu_p::read_mem(phys_addr_t paddr, unsigned length, uint8_t* const data) { + switch(paddr.val) { default: { - for(auto offs=0U; offs::read_mem(phys_addr_t paddr, unsigned le } template -iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned length, const uint8_t *const data) { - switch (paddr.val) { +iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) { + switch(paddr.val) { case 0xFFFF0000: // UART0 base, TXFIFO reg - if (((char)data[0]) == '\n' || data[0] == 0) { - LOG(INFO)<<"UART"<<((paddr.val>>12)&0x3)<<" send '"<> 12) & 0x3) << " send '" << uart_buf.str() << "'"; uart_buf.str(""); } else if(((char)data[0]) != '\r') uart_buf << (char)data[0]; break; default: { - mem_type::page_type &p = mem(paddr.val / mem.page_size); + mem_type::page_type& p = mem(paddr.val / mem.page_size); std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); // tohost handling in case of riscv-test - if (paddr.access && iss::access_type::FUNC) { - auto tohost_upper = (traits::XLEN == 32 && paddr.val == (tohost + 4)) || - (traits::XLEN == 64 && paddr.val == tohost); - auto tohost_lower = - (traits::XLEN == 32 && paddr.val == tohost) || (traits::XLEN == 64 && paddr.val == tohost); - if (tohost_lower || tohost_upper) { - uint64_t hostvar = *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)); - if (tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) { - switch (hostvar >> 48) { + if(paddr.access && iss::access_type::FUNC) { + auto tohost_upper = + (traits::XLEN == 32 && paddr.val == (tohost + 4)) || (traits::XLEN == 64 && paddr.val == tohost); + auto tohost_lower = (traits::XLEN == 32 && paddr.val == tohost) || (traits::XLEN == 64 && paddr.val == tohost); + if(tohost_lower || tohost_upper) { + uint64_t hostvar = *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)); + if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) { + switch(hostvar >> 48) { case 0: - if (hostvar != 0x1) { + if(hostvar != 0x1) { LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } else { LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } - this->reg.trap_state=std::numeric_limits::max(); - this->interrupt_sim=hostvar; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = hostvar; break; - //throw(iss::simulation_stopped(hostvar)); + // throw(iss::simulation_stopped(hostvar)); case 0x0101: { char c = static_cast(hostvar & 0xff); - if (c == '\n' || c == 0) { + if(c == '\n' || c == 0) { LOG(INFO) << "tohost send '" << uart_buf.str() << "'"; uart_buf.str(""); } else @@ -1341,12 +1357,11 @@ iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned l default: break; } - } else if (tohost_lower) + } else if(tohost_lower) to_host_wr_cnt++; - } else if ((traits::XLEN == 32 && paddr.val == fromhost + 4) || - (traits::XLEN == 64 && paddr.val == fromhost)) { - uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); - *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; + } else if((traits::XLEN == 32 && paddr.val == fromhost + 4) || (traits::XLEN == 64 && paddr.val == fromhost)) { + uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); + *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; } } } @@ -1354,32 +1369,36 @@ iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned l return iss::Ok; } -template -iss::status riscv_hart_mu_p::read_clic(uint64_t addr, unsigned length, uint8_t *const data) { - if(addr==cfg.clic_base) { // cliccfg - *data=clic_cfg_reg; - for(auto i=1; i=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig - auto offset = ((addr&0x7fff)-0x40)/4; +template +iss::status riscv_hart_mu_p::read_clic(uint64_t addr, unsigned length, uint8_t* const data) { + if(addr == cfg.clic_base) { // cliccfg + *data = clic_cfg_reg; + for(auto i = 1; i < length; ++i) + *(data + i) = 0; + } else if(addr >= (cfg.clic_base + 0x40) && (addr + length) <= (cfg.clic_base + 0x40 + cfg.clic_num_trigger * 4)) { // clicinttrig + auto offset = ((addr & 0x7fff) - 0x40) / 4; read_reg_uint32(addr, clic_inttrig_reg[offset], data, length); - } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl - auto offset = ((addr&0x7fff)-0x1000)/4; + } else if(addr >= (cfg.clic_base + 0x1000) && + (addr + length) <= (cfg.clic_base + 0x1000 + cfg.clic_num_irq * 4)) { // clicintip/clicintie/clicintattr/clicintctl + auto offset = ((addr & 0x7fff) - 0x1000) / 4; read_reg_uint32(addr, clic_int_reg[offset].raw, data, length); } else { - for(auto i = 0U; i -iss::status riscv_hart_mu_p::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) { - if(addr==cfg.clic_base) { // cliccfg - clic_cfg_reg = (clic_cfg_reg&~0x1e) | (*data&0x1e); - } else if(addr>=(cfg.clic_base+0x40) && (addr+length)<=(cfg.clic_base+0x40+cfg.clic_num_trigger*4)){ // clicinttrig - auto offset = ((addr&0x7fff)-0x40)/4; +template +iss::status riscv_hart_mu_p::write_clic(uint64_t addr, unsigned length, const uint8_t* const data) { + if(addr == cfg.clic_base) { // cliccfg + clic_cfg_reg = (clic_cfg_reg & ~0x1e) | (*data & 0x1e); + } else if(addr >= (cfg.clic_base + 0x40) && (addr + length) <= (cfg.clic_base + 0x40 + cfg.clic_num_trigger * 4)) { // clicinttrig + auto offset = ((addr & 0x7fff) - 0x40) / 4; write_reg_uint32(addr, clic_inttrig_reg[offset], data, length); - } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl - auto offset = ((addr&0x7fff)-0x1000)/4; + } else if(addr >= (cfg.clic_base + 0x1000) && + (addr + length) <= (cfg.clic_base + 0x1000 + cfg.clic_num_irq * 4)) { // clicintip/clicintie/clicintattr/clicintctl + auto offset = ((addr & 0x7fff) - 0x1000) / 4; write_reg_uint32(addr, clic_int_reg[offset].raw, data, length); clic_int_reg[offset].raw &= 0xf0c70101; // clicIntCtlBits->0xf0, clicintattr->0xc7, clicintie->0x1, clicintip->0x1 } @@ -1392,7 +1411,7 @@ template inline void riscv_hart_mu_p void riscv_hart_mu_p::check_interrupt() { - //TODO: Implement CLIC functionality + // TODO: Implement CLIC functionality auto ideleg = csr[mideleg]; // Multiple simultaneous interrupts and traps at the same privilege level are // handled in the following decreasing priority order: @@ -1404,11 +1423,11 @@ template void riscv_hart_mu_p::chec auto m_enabled = this->reg.PRIV < PRIV_M || mstatus_mie; auto enabled_interrupts = m_enabled ? ena_irq & ~ideleg : 0; - if (enabled_interrupts != 0) { + if(enabled_interrupts != 0) { int res = 0; - while ((enabled_interrupts & 1) == 0) { - enabled_interrupts >>= 1; - res++; + while((enabled_interrupts & 1) == 0) { + enabled_interrupts >>= 1; + res++; } this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id } @@ -1417,14 +1436,16 @@ template void riscv_hart_mu_p::chec template uint64_t riscv_hart_mu_p::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) { // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0] // calculate and write mcause val - if(flags==std::numeric_limits::max()) flags=this->reg.trap_state; + if(flags == std::numeric_limits::max()) + flags = this->reg.trap_state; auto trap_id = bit_sub<0, 16>(flags); auto cause = bit_sub<16, 15>(flags); - if (trap_id == 0 && cause == 11) cause = 0x8 + this->reg.PRIV; // adjust environment call cause + if(trap_id == 0 && cause == 11) + cause = 0x8 + this->reg.PRIV; // adjust environment call cause // calculate effective privilege level unsigned new_priv = PRIV_M; - if (trap_id == 0) { // exception - if (this->reg.PRIV != PRIV_M && ((csr[medeleg] >> cause) & 0x1) != 0) + if(trap_id == 0) { // exception + if(this->reg.PRIV != PRIV_M && ((csr[medeleg] >> cause) & 0x1) != 0) new_priv = PRIV_U; // store ret addr in xepc register csr[uepc | (new_priv << 8)] = static_cast(addr); // store actual address instruction of exception @@ -1435,17 +1456,17 @@ template uint64_t riscv_hart_mu_p:: * access, or page-fault exception occurs, mtval is written with the * faulting effective address. */ - switch(cause){ + switch(cause) { case 0: csr[utval | (new_priv << 8)] = static_cast(addr); break; case 2: - csr[utval | (new_priv << 8)] = (!has_compressed() || (instr & 0x3)==3)?instr:instr&0xffff; + csr[utval | (new_priv << 8)] = (!has_compressed() || (instr & 0x3) == 3) ? instr : instr & 0xffff; break; case 3: if((FEAT & FEAT_DEBUG) && (csr[dcsr] & 0x8000)) { this->reg.DPC = addr; - csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi) + csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1 << 6) | PRIV_M; // FIXME: cause should not be 4 (stepi) new_priv = this->reg.PRIV | PRIV_D; } else { csr[utval | (new_priv << 8)] = addr; @@ -1461,13 +1482,13 @@ template uint64_t riscv_hart_mu_p:: } fault_data = 0; } else { - if (this->reg.PRIV != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0) + if(this->reg.PRIV != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0) new_priv = PRIV_U; csr[uepc | (new_priv << 8)] = this->reg.NEXT_PC; // store next address if interrupt this->reg.pending_trap = 0; } size_t adr = ucause | (new_priv << 8); - csr[adr] = (trap_id << (traits::XLEN-1)) + cause; + csr[adr] = (trap_id << (traits::XLEN - 1)) + cause; // update mstatus // xPP field of mstatus is written with the active privilege mode at the time // of the trap; the x PIE field of mstatus @@ -1475,11 +1496,11 @@ template uint64_t riscv_hart_mu_p:: // the trap; and the x IE field of mstatus // is cleared // store the actual privilege level in yPP and store interrupt enable flags - switch (new_priv) { + switch(new_priv) { case PRIV_M: state.mstatus.MPP = this->reg.PRIV; - state.mstatus.MPIE = state.mstatus.MIE; - state.mstatus.MIE = false; + state.mstatus.MPIE = state.mstatus.MIE; + state.mstatus.MIE = false; break; case PRIV_U: state.mstatus.UPIE = state.mstatus.UIE; @@ -1493,7 +1514,7 @@ template uint64_t riscv_hart_mu_p:: auto xtvec = csr[utvec | (new_priv << 8)]; // calculate addr// set NEXT_PC to trap addressess to jump to based on MODE // bits in mtvec - if((FEAT & features_e::FEAT_CLIC) && trap_id!=0 && (xtvec & 0x3UL)==3UL) { + if((FEAT & features_e::FEAT_CLIC) && trap_id != 0 && (xtvec & 0x3UL) == 3UL) { reg_t data; auto ret = read(address_type::LOGICAL, access_type::READ, 0, csr[mtvt], sizeof(reg_t), reinterpret_cast(&data)); if(ret == iss::Err) @@ -1501,7 +1522,7 @@ template uint64_t riscv_hart_mu_p:: this->reg.NEXT_PC = data; } else { this->reg.NEXT_PC = xtvec & ~0x3UL; - if ((xtvec & 0x1) == 1 && trap_id != 0) + if((xtvec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause; } std::array buffer; @@ -1510,11 +1531,11 @@ template uint64_t riscv_hart_mu_p:: #else sprintf(buffer.data(), "0x%016lx", addr); #endif - if((flags&0xffffffff) != 0xffffffff) - CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" - << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")" - << " at address " << buffer.data() << " occurred, changing privilege level from " - << lvl[this->reg.PRIV] << " to " << lvl[new_priv]; + if((flags & 0xffffffff) != 0xffffffff) + CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" + << cause << ")" + << " at address " << buffer.data() << " occurred, changing privilege level from " << lvl[this->reg.PRIV] + << " to " << lvl[new_priv]; // reset trap state this->reg.PRIV = new_priv; this->reg.trap_state = 0; @@ -1523,16 +1544,16 @@ template uint64_t riscv_hart_mu_p:: template uint64_t riscv_hart_mu_p::leave_trap(uint64_t flags) { auto cur_priv = this->reg.PRIV; - auto inst_priv = (flags & 0x3)? 3:0; - if(inst_priv>cur_priv){ - auto trap_val = 0x80ULL << 24 | (2 << 16); // illegal instruction + auto inst_priv = (flags & 0x3) ? 3 : 0; + if(inst_priv > cur_priv) { + auto trap_val = 0x80ULL << 24 | (2 << 16); // illegal instruction this->reg.trap_state = trap_val; this->reg.NEXT_PC = std::numeric_limits::max(); } else { auto status = state.mstatus; // pop the relevant lower-privilege interrupt enable and privilege mode stack // clear respective yIE - switch (inst_priv) { + switch(inst_priv) { case PRIV_M: this->reg.PRIV = state.mstatus.MPP; state.mstatus.MPP = 0; // clear mpp to U mode @@ -1547,8 +1568,7 @@ template uint64_t riscv_hart_mu_p:: } // sets the pc to the value stored in the x epc register. this->reg.NEXT_PC = csr[uepc | inst_priv << 8]; - CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to " - << lvl[this->reg.PRIV]; + CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to " << lvl[this->reg.PRIV]; check_interrupt(); } return this->reg.NEXT_PC; diff --git a/src/iss/arch/tgc5c.cpp b/src/iss/arch/tgc5c.cpp index 6996cb8..eab100d 100644 --- a/src/iss/arch/tgc5c.cpp +++ b/src/iss/arch/tgc5c.cpp @@ -32,38 +32,35 @@ #include "tgc5c.h" #include "util/ities.h" -#include #include #include #include +#include using namespace iss::arch; -constexpr std::array iss::arch::traits::reg_names; -constexpr std::array iss::arch::traits::reg_aliases; +constexpr std::array iss::arch::traits::reg_names; +constexpr std::array iss::arch::traits::reg_aliases; constexpr std::array iss::arch::traits::reg_bit_widths; constexpr std::array iss::arch::traits::reg_byte_offsets; -tgc5c::tgc5c() = default; +tgc5c::tgc5c() = default; tgc5c::~tgc5c() = default; void tgc5c::reset(uint64_t address) { auto base_ptr = reinterpret_cast::reg_t*>(get_regs_base_ptr()); - for(size_t i=0; i::NUM_REGS; ++i) - *(base_ptr+i)=0; - reg.PC=address; - reg.NEXT_PC=reg.PC; - reg.PRIV=0x3; - reg.trap_state=0; - reg.icount=0; + for(size_t i = 0; i < traits::NUM_REGS; ++i) + *(base_ptr + i) = 0; + reg.PC = address; + reg.NEXT_PC = reg.PC; + reg.PRIV = 0x3; + reg.trap_state = 0; + reg.icount = 0; } -uint8_t *tgc5c::get_regs_base_ptr() { - return reinterpret_cast(®); -} +uint8_t* tgc5c::get_regs_base_ptr() { return reinterpret_cast(®); } -tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t &addr) { - return phys_addr_t(addr.access, addr.space, addr.val&traits::addr_mask); +tgc5c::phys_addr_t tgc5c::virt2phys(const iss::addr_t& addr) { + return phys_addr_t(addr.access, addr.space, addr.val & traits::addr_mask); } - diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index 2dddbb3..ee712b7 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -46,43 +46,103 @@ struct tgc5c; template <> struct traits { constexpr static char const* const core_type = "TGC5C"; - - static constexpr std::array reg_names{ - {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}}; - - static constexpr std::array reg_aliases{ - {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}}; - enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL}; + static constexpr std::array reg_names{{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", + "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", + "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", + "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}}; + + static constexpr std::array reg_aliases{ + {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", + "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}}; + + enum constants { + MISA_VAL = 1073746180ULL, + MARCHID_VAL = 2147483651ULL, + XLEN = 32ULL, + INSTR_ALIGNMENT = 2ULL, + RFS = 32ULL, + fence = 0ULL, + fencei = 1ULL, + fencevmal = 2ULL, + fencevmau = 3ULL, + CSR_SIZE = 4096ULL, + MUL_LEN = 64ULL + }; constexpr static unsigned FP_REGS_SIZE = 0; enum reg_e { - X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH + X0, + X1, + X2, + X3, + X4, + X5, + X6, + X7, + X8, + X9, + X10, + X11, + X12, + X13, + X14, + X15, + X16, + X17, + X18, + X19, + X20, + X21, + X22, + X23, + X24, + X25, + X26, + X27, + X28, + X29, + X30, + X31, + PC, + NEXT_PC, + PRIV, + DPC, + NUM_REGS, + TRAP_STATE = NUM_REGS, + PENDING_TRAP, + ICOUNT, + CYCLE, + INSTRET, + INSTRUCTION, + LAST_BRANCH }; using reg_t = uint32_t; using addr_t = uint32_t; - using code_word_t = uint32_t; //TODO: check removal + using code_word_t = uint32_t; // TODO: check removal using virt_addr_t = iss::typed_addr_t; using phys_addr_t = iss::typed_addr_t; - static constexpr std::array reg_bit_widths{ - {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}}; + static constexpr std::array reg_bit_widths{{32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 8, 32, 32, 32, 64, 64, 64, 32, 32}}; static constexpr std::array reg_byte_offsets{ - {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}}; + {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, + 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 137, 141, 145, 149, 157, 165, 173, 177}}; static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); enum sreg_flag_e { FLAGS }; enum mem_type_e { MEM, FENCE, RES, CSR }; - + enum class opcode_e { LUI = 0, AUIPC = 1, @@ -175,17 +235,17 @@ template <> struct traits { }; }; -struct tgc5c: public arch_if { +struct tgc5c : public arch_if { using virt_addr_t = typename traits::virt_addr_t; using phys_addr_t = typename traits::phys_addr_t; - using reg_t = typename traits::reg_t; + using reg_t = typename traits::reg_t; using addr_t = typename traits::addr_t; tgc5c(); ~tgc5c(); - void reset(uint64_t address=0) override; + void reset(uint64_t address = 0) override; uint8_t* get_regs_base_ptr() override; @@ -201,44 +261,43 @@ struct tgc5c: public arch_if { inline uint32_t get_last_branch() { return reg.last_branch; } - #pragma pack(push, 1) - struct TGC5C_regs { - uint32_t X0 = 0; - uint32_t X1 = 0; - uint32_t X2 = 0; - uint32_t X3 = 0; - uint32_t X4 = 0; - uint32_t X5 = 0; - uint32_t X6 = 0; - uint32_t X7 = 0; - uint32_t X8 = 0; - uint32_t X9 = 0; - uint32_t X10 = 0; - uint32_t X11 = 0; - uint32_t X12 = 0; - uint32_t X13 = 0; - uint32_t X14 = 0; - uint32_t X15 = 0; - uint32_t X16 = 0; - uint32_t X17 = 0; - uint32_t X18 = 0; - uint32_t X19 = 0; - uint32_t X20 = 0; - uint32_t X21 = 0; - uint32_t X22 = 0; - uint32_t X23 = 0; - uint32_t X24 = 0; - uint32_t X25 = 0; - uint32_t X26 = 0; - uint32_t X27 = 0; - uint32_t X28 = 0; - uint32_t X29 = 0; - uint32_t X30 = 0; - uint32_t X31 = 0; - uint32_t PC = 0; - uint32_t NEXT_PC = 0; - uint8_t PRIV = 0; + struct TGC5C_regs { + uint32_t X0 = 0; + uint32_t X1 = 0; + uint32_t X2 = 0; + uint32_t X3 = 0; + uint32_t X4 = 0; + uint32_t X5 = 0; + uint32_t X6 = 0; + uint32_t X7 = 0; + uint32_t X8 = 0; + uint32_t X9 = 0; + uint32_t X10 = 0; + uint32_t X11 = 0; + uint32_t X12 = 0; + uint32_t X13 = 0; + uint32_t X14 = 0; + uint32_t X15 = 0; + uint32_t X16 = 0; + uint32_t X17 = 0; + uint32_t X18 = 0; + uint32_t X19 = 0; + uint32_t X20 = 0; + uint32_t X21 = 0; + uint32_t X22 = 0; + uint32_t X23 = 0; + uint32_t X24 = 0; + uint32_t X25 = 0; + uint32_t X26 = 0; + uint32_t X27 = 0; + uint32_t X28 = 0; + uint32_t X29 = 0; + uint32_t X30 = 0; + uint32_t X31 = 0; + uint32_t PC = 0; + uint32_t NEXT_PC = 0; + uint8_t PRIV = 0; uint32_t DPC = 0; uint32_t trap_state = 0, pending_trap = 0; uint64_t icount = 0; @@ -249,14 +308,13 @@ struct tgc5c: public arch_if { } reg; #pragma pack(pop) std::array addr_mode; - - uint64_t interrupt_sim=0; - uint32_t get_fcsr(){return 0;} - void set_fcsr(uint32_t val){} + uint64_t interrupt_sim = 0; + uint32_t get_fcsr() { return 0; } + void set_fcsr(uint32_t val) {} }; -} -} +} // namespace arch +} // namespace iss #endif /* _TGC5C_H_ */ diff --git a/src/iss/arch/tgc_mapper.h b/src/iss/arch/tgc_mapper.h index 83f82da..02ebacc 100644 --- a/src/iss/arch/tgc_mapper.h +++ b/src/iss/arch/tgc_mapper.h @@ -15,36 +15,43 @@ using tgc5a_plat_type = iss::arch::riscv_hart_m_p; using tgc5b_plat_type = iss::arch::riscv_hart_m_p; #endif #ifdef CORE_TGC5C_XRB_NN -#include "riscv_hart_m_p.h" #include "hwl.h" +#include "riscv_hart_m_p.h" #include using tgc5c_xrb_nn_plat_type = iss::arch::hwl>; #endif #ifdef CORE_TGC5D #include "riscv_hart_mu_p.h" #include -using tgc5d_plat_type = iss::arch::riscv_hart_mu_p; +using tgc5d_plat_type = iss::arch::riscv_hart_mu_p; #endif #ifdef CORE_TGC5D_XRB_MAC #include "riscv_hart_mu_p.h" #include -using tgc5d_xrb_mac_plat_type = iss::arch::riscv_hart_mu_p; +using tgc5d_xrb_mac_plat_type = + iss::arch::riscv_hart_mu_p; #endif #ifdef CORE_TGC5D_XRB_NN -#include "riscv_hart_mu_p.h" #include "hwl.h" +#include "riscv_hart_mu_p.h" #include -using tgc5d_xrb_nn_plat_type = iss::arch::hwl>; +using tgc5d_xrb_nn_plat_type = + iss::arch::hwl>; #endif #ifdef CORE_TGC5E #include "riscv_hart_mu_p.h" #include -using tgc5e_plat_type = iss::arch::riscv_hart_mu_p; +using tgc5e_plat_type = iss::arch::riscv_hart_mu_p; #endif #ifdef CORE_TGC5X #include "riscv_hart_mu_p.h" #include -using tgc5x_plat_type = iss::arch::riscv_hart_mu_p; +using tgc5x_plat_type = iss::arch::riscv_hart_mu_p; #endif #endif diff --git a/src/iss/arch/wt_cache.h b/src/iss/arch/wt_cache.h index 7108b9d..e762f22 100644 --- a/src/iss/arch/wt_cache.h +++ b/src/iss/arch/wt_cache.h @@ -36,25 +36,27 @@ #define _RISCV_HART_M_P_WT_CACHE_H #include -#include -#include #include #include +#include +#include namespace iss { namespace arch { namespace cache { -enum class state { INVALID, VALID}; +enum class state { INVALID, VALID }; struct line { uint64_t tag_addr{0}; state st{state::INVALID}; std::vector data; - line(unsigned line_sz): data(line_sz) {} + line(unsigned line_sz) + : data(line_sz) {} }; struct set { std::vector ways; - set(unsigned ways_count, line const& l): ways(ways_count, l) {} + set(unsigned ways_count, line const& l) + : ways(ways_count, l) {} }; struct cache { std::vector sets; @@ -62,14 +64,14 @@ struct cache { cache(unsigned size, unsigned line_sz, unsigned ways) { line const ref_line{line_sz}; set const ref_set{ways, ref_line}; - sets.resize(size/(ways*line_sz), ref_set); + sets.resize(size / (ways * line_sz), ref_set); } }; struct wt_policy { - bool is_cacheline_hit(cache& c ); + bool is_cacheline_hit(cache& c); }; -} +} // namespace cache // write thru, allocate on read, direct mapped or set-associative with round-robin replacement policy template class wt_cache : public BASE { @@ -89,78 +91,73 @@ public: unsigned ways{1}; uint64_t io_address{0xf0000000}; uint64_t io_addr_mask{0xf0000000}; + protected: - iss::status read_cache(phys_addr_t addr, unsigned, uint8_t *const); - iss::status write_cache(phys_addr_t addr, unsigned, uint8_t const *const); + iss::status read_cache(phys_addr_t addr, unsigned, uint8_t* const); + iss::status write_cache(phys_addr_t addr, unsigned, uint8_t const* const); std::function cache_mem_rd_delegate; std::function cache_mem_wr_delegate; std::unique_ptr dcache_ptr; std::unique_ptr icache_ptr; - size_t get_way_select() { - return 0; - } + size_t get_way_select() { return 0; } }; - -template +template inline wt_cache::wt_cache(feature_config cfg) -:BASE(cfg) +: BASE(cfg) , io_address{cfg.io_address} -, io_addr_mask{cfg.io_addr_mask} -{ +, io_addr_mask{cfg.io_addr_mask} { auto cb = base_class::replace_mem_access( - [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l,d);}, - [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l,d);}); + [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status { return read_cache(a, l, d); }, + [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return write_cache(a, l, d); }); cache_mem_rd_delegate = cb.first; cache_mem_wr_delegate = cb.second; } -template -iss::status iss::arch::wt_cache::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) { +template iss::status iss::arch::wt_cache::read_cache(phys_addr_t a, unsigned l, uint8_t* const d) { if(!icache_ptr) { icache_ptr.reset(new cache::cache(size, line_sz, ways)); dcache_ptr.reset(new cache::cache(size, line_sz, ways)); } - if((a.val&io_addr_mask) != io_address) { - auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways); - auto tag_addr=a.val>>util::ilog2(line_sz); - auto& set = (is_fetch(a.access)?icache_ptr:dcache_ptr)->sets[set_addr]; - for(auto& cl: set.ways) { - if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) { - auto start_addr = a.val&(line_sz-1); - for(auto i = 0U; i> util::ilog2(line_sz * ways); + auto tag_addr = a.val >> util::ilog2(line_sz); + auto& set = (is_fetch(a.access) ? icache_ptr : dcache_ptr)->sets[set_addr]; + for(auto& cl : set.ways) { + if(cl.st == cache::state::VALID && cl.tag_addr == tag_addr) { + auto start_addr = a.val & (line_sz - 1); + for(auto i = 0U; i < l; ++i) + d[i] = cl.data[start_addr + i]; return iss::Ok; } } auto& cl = set.ways[get_way_select()]; phys_addr_t cl_addr{a}; - cl_addr.val=tag_addr< -iss::status iss::arch::wt_cache::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) { +template iss::status iss::arch::wt_cache::write_cache(phys_addr_t a, unsigned l, const uint8_t* const d) { if(!dcache_ptr) dcache_ptr.reset(new cache::cache(size, line_sz, ways)); auto res = cache_mem_wr_delegate(a, l, d); - if(res == iss::Ok && ((a.val&io_addr_mask) != io_address)) { - auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways); - auto tag_addr=a.val>>util::ilog2(line_sz); + if(res == iss::Ok && ((a.val & io_addr_mask) != io_address)) { + auto set_addr = (a.val & (size - 1)) >> util::ilog2(line_sz * ways); + auto tag_addr = a.val >> util::ilog2(line_sz); auto& set = dcache_ptr->sets[set_addr]; - for(auto& cl: set.ways) { - if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) { - auto start_addr = a.val&(line_sz-1); - for(auto i = 0U; i::write_cache(phys_addr_t a, unsigned l, co return res; } - - } // namespace arch } // namespace iss diff --git a/src/iss/debugger/riscv_target_adapter.h b/src/iss/debugger/riscv_target_adapter.h index d8d105e..6a2a527 100644 --- a/src/iss/debugger/riscv_target_adapter.h +++ b/src/iss/debugger/riscv_target_adapter.h @@ -53,20 +53,20 @@ using namespace iss::debugger; template class riscv_target_adapter : public target_adapter_base { public: - riscv_target_adapter(server_if *srv, iss::arch_if *core) + riscv_target_adapter(server_if* srv, iss::arch_if* core) : target_adapter_base(srv) , core(core) {} /*============== Thread Control ===============================*/ /* Set generic thread */ - status set_gen_thread(rp_thread_ref &thread) override; + status set_gen_thread(rp_thread_ref& thread) override; /* Set control thread */ - status set_ctrl_thread(rp_thread_ref &thread) override; + status set_ctrl_thread(rp_thread_ref& thread) override; /* Get thread status */ - status is_thread_alive(rp_thread_ref &thread, bool &alive) override; + status is_thread_alive(rp_thread_ref& thread, bool& alive) override; /*============= Register Access ================================*/ @@ -74,79 +74,77 @@ public: target byte order. If register is not available corresponding bytes in avail_buf are 0, otherwise avail buf is 1 */ - status read_registers(std::vector &data, std::vector &avail) override; + status read_registers(std::vector& data, std::vector& avail) override; /* Write all registers. buf is 4-byte aligned and it is in target byte order */ - status write_registers(const std::vector &data) override; + status write_registers(const std::vector& data) override; /* Read one register. buf is 4-byte aligned and it is in target byte order. If register is not available corresponding bytes in avail_buf are 0, otherwise avail buf is 1 */ - status read_single_register(unsigned int reg_no, std::vector &buf, - std::vector &avail_buf) override; + status read_single_register(unsigned int reg_no, std::vector& buf, std::vector& avail_buf) override; /* Write one register. buf is 4-byte aligned and it is in target byte order */ - status write_single_register(unsigned int reg_no, const std::vector &buf) override; + status write_single_register(unsigned int reg_no, const std::vector& buf) override; /*=================== Memory Access =====================*/ /* Read memory, buf is 4-bytes aligned and it is in target byte order */ - status read_mem(uint64_t addr, std::vector &buf) override; + status read_mem(uint64_t addr, std::vector& buf) override; /* Write memory, buf is 4-bytes aligned and it is in target byte order */ - status write_mem(uint64_t addr, const std::vector &buf) override; + status write_mem(uint64_t addr, const std::vector& buf) override; - status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override; + status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override; - status thread_list_query(int first, const rp_thread_ref &arg, std::vector &result, size_t max_num, - size_t &num, bool &done) override; + status thread_list_query(int first, const rp_thread_ref& arg, std::vector& result, size_t max_num, size_t& num, + bool& done) override; - status current_thread_query(rp_thread_ref &thread) override; + status current_thread_query(rp_thread_ref& thread) override; - status offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) override; + status offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) override; - status crc_query(uint64_t addr, size_t len, uint32_t &val) override; + status crc_query(uint64_t addr, size_t len, uint32_t& val) override; - status raw_query(std::string in_buf, std::string &out_buf) override; + status raw_query(std::string in_buf, std::string& out_buf) override; - status threadinfo_query(int first, std::string &out_buf) override; + status threadinfo_query(int first, std::string& out_buf) override; - status threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) override; + status threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) override; - status packetsize_query(std::string &out_buf) override; + status packetsize_query(std::string& out_buf) override; status add_break(break_type type, uint64_t addr, unsigned int length) override; status remove_break(break_type type, uint64_t addr, unsigned int length) override; - status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, - std::function stop_callback) override; + status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, std::function stop_callback) override; - status target_xml_query(std::string &out_buf) override; + status target_xml_query(std::string& out_buf) override; protected: - static inline constexpr addr_t map_addr(const addr_t &i) { return i; } + static inline constexpr addr_t map_addr(const addr_t& i) { return i; } - iss::arch_if *core; + iss::arch_if* core; rp_thread_ref thread_idx; }; -template status riscv_target_adapter::set_gen_thread(rp_thread_ref &thread) { +template status riscv_target_adapter::set_gen_thread(rp_thread_ref& thread) { thread_idx = thread; return Ok; } -template status riscv_target_adapter::set_ctrl_thread(rp_thread_ref &thread) { +template status riscv_target_adapter::set_ctrl_thread(rp_thread_ref& thread) { thread_idx = thread; return Ok; } -template status riscv_target_adapter::is_thread_alive(rp_thread_ref &thread, bool &alive) { +template status riscv_target_adapter::is_thread_alive(rp_thread_ref& thread, bool& alive) { alive = 1; return Ok; } @@ -158,10 +156,9 @@ template status riscv_target_adapter::is_thread_alive(rp_t * set if all threads are processed. */ template -status riscv_target_adapter::thread_list_query(int first, const rp_thread_ref &arg, - std::vector &result, size_t max_num, size_t &num, - bool &done) { - if (first == 0) { +status riscv_target_adapter::thread_list_query(int first, const rp_thread_ref& arg, std::vector& result, + size_t max_num, size_t& num, bool& done) { + if(first == 0) { result.clear(); result.push_back(thread_idx); num = 1; @@ -171,23 +168,22 @@ status riscv_target_adapter::thread_list_query(int first, const rp_thread_ return NotSupported; } -template status riscv_target_adapter::current_thread_query(rp_thread_ref &thread) { +template status riscv_target_adapter::current_thread_query(rp_thread_ref& thread) { thread = thread_idx; return Ok; } -template -status riscv_target_adapter::read_registers(std::vector &data, std::vector &avail) { +template status riscv_target_adapter::read_registers(std::vector& data, std::vector& avail) { LOG(TRACE) << "reading target registers"; // return idx<0?:; data.clear(); avail.clear(); - const uint8_t *reg_base = core->get_regs_base_ptr(); - auto start_reg=arch::traits::X0; - for (size_t reg_no = start_reg; reg_no < start_reg+33/*arch::traits::NUM_REGS*/; ++reg_no) { + const uint8_t* reg_base = core->get_regs_base_ptr(); + auto start_reg = arch::traits::X0; + for(size_t reg_no = start_reg; reg_no < start_reg + 33 /*arch::traits::NUM_REGS*/; ++reg_no) { auto reg_width = arch::traits::reg_bit_widths[reg_no] / 8; unsigned offset = traits::reg_byte_offsets[reg_no]; - for (size_t j = 0; j < reg_width; ++j) { + for(size_t j = 0; j < reg_width; ++j) { data.push_back(*(reg_base + offset + j)); avail.push_back(0xff); } @@ -210,19 +206,19 @@ status riscv_target_adapter::read_registers(std::vector &data, st return Ok; } -template status riscv_target_adapter::write_registers(const std::vector &data) { - auto start_reg=arch::traits::X0; - auto *reg_base = core->get_regs_base_ptr(); +template status riscv_target_adapter::write_registers(const std::vector& data) { + auto start_reg = arch::traits::X0; + auto* reg_base = core->get_regs_base_ptr(); auto iter = data.data(); - bool e_ext = arch::traits::PC<32; - for (size_t reg_no = 0; reg_no < start_reg+33/*arch::traits::NUM_REGS*/; ++reg_no) { - if(e_ext && reg_no>15){ - if(reg_no==32){ + bool e_ext = arch::traits::PC < 32; + for(size_t reg_no = 0; reg_no < start_reg + 33 /*arch::traits::NUM_REGS*/; ++reg_no) { + if(e_ext && reg_no > 15) { + if(reg_no == 32) { auto reg_width = arch::traits::reg_bit_widths[arch::traits::PC] / 8; auto offset = traits::reg_byte_offsets[arch::traits::PC]; std::copy(iter, iter + reg_width, reg_base); } else { - const uint64_t zero_val=0; + const uint64_t zero_val = 0; auto reg_width = arch::traits::reg_bit_widths[15] / 8; auto iter = (uint8_t*)&zero_val; std::copy(iter, iter + reg_width, reg_base); @@ -239,12 +235,11 @@ template status riscv_target_adapter::write_registers(cons } template -status riscv_target_adapter::read_single_register(unsigned int reg_no, std::vector &data, - std::vector &avail) { - if (reg_no < 65) { +status riscv_target_adapter::read_single_register(unsigned int reg_no, std::vector& data, std::vector& avail) { + if(reg_no < 65) { // auto reg_size = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; - auto *reg_base = core->get_regs_base_ptr(); + auto* reg_base = core->get_regs_base_ptr(); auto reg_width = arch::traits::reg_bit_widths[reg_no] / 8; data.resize(reg_width); avail.resize(reg_width); @@ -261,10 +256,9 @@ status riscv_target_adapter::read_single_register(unsigned int reg_no, std return data.size() > 0 ? Ok : Err; } -template -status riscv_target_adapter::write_single_register(unsigned int reg_no, const std::vector &data) { - if (reg_no < 65) { - auto *reg_base = core->get_regs_base_ptr(); +template status riscv_target_adapter::write_single_register(unsigned int reg_no, const std::vector& data) { + if(reg_no < 65) { + auto* reg_base = core->get_regs_base_ptr(); auto reg_width = arch::traits::reg_bit_widths[static_cast::reg_e>(reg_no)] / 8; auto offset = traits::reg_byte_offsets[reg_no]; std::copy(data.begin(), data.begin() + reg_width, reg_base + offset); @@ -275,41 +269,36 @@ status riscv_target_adapter::write_single_register(unsigned int reg_no, co return Ok; } -template status riscv_target_adapter::read_mem(uint64_t addr, std::vector &data) { +template status riscv_target_adapter::read_mem(uint64_t addr, std::vector& data) { auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr}); auto f = [&]() -> status { return core->read(a, data.size(), data.data()); }; return srv->execute_syncronized(f); } -template status riscv_target_adapter::write_mem(uint64_t addr, const std::vector &data) { +template status riscv_target_adapter::write_mem(uint64_t addr, const std::vector& data) { auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr}); auto f = [&]() -> status { return core->write(a, data.size(), data.data()); }; return srv->execute_syncronized(f); } template -status riscv_target_adapter::process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) { +status riscv_target_adapter::process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) { return NotSupported; } -template -status riscv_target_adapter::offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) { +template status riscv_target_adapter::offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) { text = 0; data = 0; bss = 0; return Ok; } -template status riscv_target_adapter::crc_query(uint64_t addr, size_t len, uint32_t &val) { - return NotSupported; -} +template status riscv_target_adapter::crc_query(uint64_t addr, size_t len, uint32_t& val) { return NotSupported; } -template status riscv_target_adapter::raw_query(std::string in_buf, std::string &out_buf) { - return NotSupported; -} +template status riscv_target_adapter::raw_query(std::string in_buf, std::string& out_buf) { return NotSupported; } -template status riscv_target_adapter::threadinfo_query(int first, std::string &out_buf) { - if (first) { +template status riscv_target_adapter::threadinfo_query(int first, std::string& out_buf) { + if(first) { out_buf = fmt::format("m{:x}", thread_idx.val); } else { out_buf = "l"; @@ -317,8 +306,7 @@ template status riscv_target_adapter::threadinfo_query(int return Ok; } -template -status riscv_target_adapter::threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) { +template status riscv_target_adapter::threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) { std::array buf; memset(buf.data(), 0, 20); sprintf(buf.data(), "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0); @@ -326,7 +314,7 @@ status riscv_target_adapter::threadextrainfo_query(const rp_thread_ref &th return Ok; } -template status riscv_target_adapter::packetsize_query(std::string &out_buf) { +template status riscv_target_adapter::packetsize_query(std::string& out_buf) { out_buf = "PacketSize=1000"; return Ok; } @@ -340,8 +328,8 @@ template status riscv_target_adapter::add_break(break_type auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr}); auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length}); target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val); - LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex - << saddr.val << std::dec; + LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val + << std::dec; LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; return Ok; } @@ -356,9 +344,8 @@ template status riscv_target_adapter::remove_break(break_t case HW_EXEC: { auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr}); unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val); - if (handle) { - LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val - << std::dec; + if(handle) { + LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec; // TODO: check length of addr range target_adapter_base::bp_lut.removeEntry(handle); LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; @@ -372,53 +359,53 @@ template status riscv_target_adapter::remove_break(break_t template status riscv_target_adapter::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, - std::function stop_callback) { - auto *reg_base = core->get_regs_base_ptr(); + std::function stop_callback) { + auto* reg_base = core->get_regs_base_ptr(); auto reg_width = arch::traits::reg_bit_widths[arch::traits::PC] / 8; auto offset = traits::reg_byte_offsets[arch::traits::PC]; - const uint8_t *iter = reinterpret_cast(&addr); + const uint8_t* iter = reinterpret_cast(&addr); std::copy(iter, iter + reg_width, reg_base); return resume_from_current(step, sig, thread, stop_callback); } -template status riscv_target_adapter::target_xml_query(std::string &out_buf) { +template status riscv_target_adapter::target_xml_query(std::string& out_buf) { const std::string res{"" - "riscv:rv32" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - //" \n" - ""}; + "riscv:rv32" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + //" \n" + ""}; out_buf = res; return Ok; } @@ -468,7 +455,7 @@ template status riscv_target_adapter::target_xml_query(std */ -} -} +} // namespace debugger +} // namespace iss #endif /* _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */ diff --git a/src/iss/factory.h b/src/iss/factory.h index c24fefb..a2a1943 100644 --- a/src/iss/factory.h +++ b/src/iss/factory.h @@ -33,21 +33,20 @@ #ifndef _ISS_FACTORY_H_ #define _ISS_FACTORY_H_ +#include +#include #include #include -#include -#include #include -#include +#include #include namespace iss { using cpu_ptr = std::unique_ptr; -using vm_ptr= std::unique_ptr; +using vm_ptr = std::unique_ptr; -template -std::tuple create_cpu(std::string const& backend, unsigned gdb_port){ +template std::tuple create_cpu(std::string const& backend, unsigned gdb_port) { using core_type = typename PLAT::core; core_type* lcpu = new PLAT(); if(backend == "interp") @@ -63,44 +62,45 @@ std::tuple create_cpu(std::string const& backend, unsigned gdb_ return {nullptr, nullptr}; } - class core_factory { using cpu_ptr = std::unique_ptr; - using vm_ptr= std::unique_ptr; + using vm_ptr = std::unique_ptr; using base_t = std::tuple; - using create_fn = std::function; - using registry_t = std::unordered_map ; + using create_fn = std::function; + using registry_t = std::unordered_map; registry_t registry; core_factory() = default; - core_factory(const core_factory &) = delete; - core_factory & operator=(const core_factory &) = delete; + core_factory(const core_factory&) = delete; + core_factory& operator=(const core_factory&) = delete; public: - static core_factory & instance() { static core_factory bf; return bf; } + static core_factory& instance() { + static core_factory bf; + return bf; + } - bool register_creator(const std::string & className, create_fn const& fn) { + bool register_creator(const std::string& className, create_fn const& fn) { registry[className] = fn; return true; } - base_t create(std::string const& className, unsigned gdb_port=0, void* init_data=nullptr) const { + base_t create(std::string const& className, unsigned gdb_port = 0, void* init_data = nullptr) const { registry_t::const_iterator regEntry = registry.find(className); - if (regEntry != registry.end()) + if(regEntry != registry.end()) return regEntry->second(gdb_port, init_data); return {nullptr, nullptr}; } std::vector get_names() { std::vector keys{registry.size()}; - std::transform(std::begin(registry), std::end(registry), std::begin(keys), [](std::pair const& p){ - return p.first; - }); + std::transform(std::begin(registry), std::end(registry), std::begin(keys), + [](std::pair const& p) { return p.first; }); return keys; } }; -} +} // namespace iss #endif /* _ISS_FACTORY_H_ */ diff --git a/src/iss/plugin/cycle_estimate.cpp b/src/iss/plugin/cycle_estimate.cpp index f5bac69..69e466a 100644 --- a/src/iss/plugin/cycle_estimate.cpp +++ b/src/iss/plugin/cycle_estimate.cpp @@ -36,17 +36,15 @@ #include #include +#include #include #include -#include using namespace std; iss::plugin::cycle_estimate::cycle_estimate(string const& config_file_name) : instr_if(nullptr) -, config_file_name(config_file_name) -{ -} +, config_file_name(config_file_name) {} iss::plugin::cycle_estimate::~cycle_estimate() = default; @@ -54,23 +52,24 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& instr_if = vm.get_arch()->get_instrumentation_if(); assert(instr_if && "No instrumentation interface available but callback executed"); reg_base_ptr = reinterpret_cast(vm.get_arch()->get_regs_base_ptr()); - if(!instr_if) return false; - const string core_name = instr_if->core_type_name(); - if (config_file_name.length() > 0) { + if(!instr_if) + return false; + const string core_name = instr_if->core_type_name(); + if(config_file_name.length() > 0) { std::ifstream is(config_file_name); - if (is.is_open()) { + if(is.is_open()) { try { auto root = YAML::LoadAll(is); - if(root.size()!=1) { + if(root.size() != 1) { LOG(ERR) << "Too many root nodes in YAML file " << config_file_name; } - for (auto p : root[0]) { + for(auto p : root[0]) { auto isa_subset = p.first; auto instructions = p.second; - for (auto const& instr : instructions) { + for(auto const& instr : instructions) { auto idx = instr.second["index"].as(); - if(delays.size()<=idx) - delays.resize(idx+1); + if(delays.size() <= idx) + delays.resize(idx + 1); auto& res = delays[idx]; res.is_branch = instr.second["branch"].as(); auto delay = instr.second["delay"]; @@ -81,13 +80,13 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& try { res.not_taken = delay.as(); res.taken = res.not_taken; - } catch (const YAML::BadConversion& e) { + } catch(const YAML::BadConversion& e) { res.f = iss::plugin::calculator(reg_base_ptr, delay.as()); } } } } - } catch (YAML::ParserException &e) { + } catch(YAML::ParserException& e) { LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); return false; } @@ -101,14 +100,14 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) { size_t instr_id = instr_info.instr_id; - auto& entry = instr_idget_instr_word()); } else { if(!entry.f) - current_delay = instr_if->is_branch_taken()? entry.taken: entry.not_taken; - if(current_delay>1) + current_delay = instr_if->is_branch_taken() ? entry.taken : entry.not_taken; + if(current_delay > 1) instr_if->update_last_instr_cycles(current_delay); current_delay = 1; } diff --git a/src/iss/plugin/cycle_estimate.h b/src/iss/plugin/cycle_estimate.h index 07cdd61..c2f6d13 100644 --- a/src/iss/plugin/cycle_estimate.h +++ b/src/iss/plugin/cycle_estimate.h @@ -37,16 +37,16 @@ #include "iss/instrumentation_if.h" #include "iss/vm_plugin.h" +#include #include #include #include -#include namespace iss { namespace plugin { -class cycle_estimate: public vm_plugin { +class cycle_estimate : public vm_plugin { struct instr_desc { size_t size{0}; bool is_branch{false}; @@ -58,32 +58,32 @@ class cycle_estimate: public vm_plugin { public: cycle_estimate() = delete; - cycle_estimate(const cycle_estimate &) = delete; + cycle_estimate(const cycle_estimate&) = delete; - cycle_estimate(const cycle_estimate &&) = delete; + cycle_estimate(const cycle_estimate&&) = delete; cycle_estimate(std::string const& config_file_name); virtual ~cycle_estimate(); - cycle_estimate &operator=(const cycle_estimate &) = delete; + cycle_estimate& operator=(const cycle_estimate&) = delete; - cycle_estimate &operator=(const cycle_estimate &&) = delete; + cycle_estimate& operator=(const cycle_estimate&&) = delete; - bool registration(const char *const version, vm_if &arch) override; + bool registration(const char* const version, vm_if& arch) override; sync_type get_sync() override { return ALL_SYNC; }; void callback(instr_info_t instr_info) override; private: - iss::instrumentation_if *instr_if{nullptr}; - uint32_t* reg_base_ptr {nullptr}; + iss::instrumentation_if* instr_if{nullptr}; + uint32_t* reg_base_ptr{nullptr}; instr_desc illegal_desc{}; std::vector delays; unsigned current_delay{0}; struct pair_hash { - size_t operator()(const std::pair &p) const { + size_t operator()(const std::pair& p) const { std::hash hash; return hash(p.first) + hash(p.second); } @@ -91,7 +91,7 @@ private: std::unordered_map, uint64_t, pair_hash> blocks; std::string config_file_name; }; -} -} +} // namespace plugin +} // namespace iss #endif /* _ISS_PLUGIN_CYCLE_ESTIMATE_H_ */ diff --git a/src/iss/plugin/instruction_count.cpp b/src/iss/plugin/instruction_count.cpp index 01fb45c..bb47e53 100644 --- a/src/iss/plugin/instruction_count.cpp +++ b/src/iss/plugin/instruction_count.cpp @@ -36,26 +36,26 @@ #include #include +#include #include #include -#include iss::plugin::instruction_count::instruction_count(std::string config_file_name) { - if (config_file_name.length() > 0) { + if(config_file_name.length() > 0) { std::ifstream is(config_file_name); - if (is.is_open()) { + if(is.is_open()) { try { auto root = YAML::LoadAll(is); - if(root.size()!=1) { + if(root.size() != 1) { LOG(ERR) << "Too many rro nodes in YAML file " << config_file_name; } - for (auto p : root[0]) { + for(auto p : root[0]) { auto isa_subset = p.first; auto instructions = p.second; - for (auto const& instr : instructions) { + for(auto const& instr : instructions) { instr_delay res; res.instr_name = instr.first.as(); - res.size = instr.second["encoding"].as().size()-2; // not counting 0b + res.size = instr.second["encoding"].as().size() - 2; // not counting 0b auto delay = instr.second["delay"]; if(delay.IsSequence()) { res.not_taken_delay = delay[0].as(); @@ -68,30 +68,29 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name) } } rep_counts.resize(delays.size()); - } catch (YAML::ParserException &e) { - LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); + } catch(YAML::ParserException& e) { + LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); } } else { - LOG(ERR) << "Could not open input file " << config_file_name; + LOG(ERR) << "Could not open input file " << config_file_name; } } } iss::plugin::instruction_count::~instruction_count() { - size_t idx=0; - for(auto it:delays){ - if(rep_counts[idx]>0 && it.instr_name.find("__"!=0)) - LOG(INFO)< 0 && it.instr_name.find("__" != 0)) + LOG(INFO) << it.instr_name << ";" << rep_counts[idx]; + idx++; + } } bool iss::plugin::instruction_count::registration(const char* const version, vm_if& vm) { auto instr_if = vm.get_arch()->get_instrumentation_if(); - if(!instr_if) return false; - return true; + if(!instr_if) + return false; + return true; } -void iss::plugin::instruction_count::callback(instr_info_t instr_info) { - rep_counts[instr_info.instr_id]++; -} +void iss::plugin::instruction_count::callback(instr_info_t instr_info) { rep_counts[instr_info.instr_id]++; } diff --git a/src/iss/plugin/instruction_count.h b/src/iss/plugin/instruction_count.h index 38c7f05..b31979c 100644 --- a/src/iss/plugin/instruction_count.h +++ b/src/iss/plugin/instruction_count.h @@ -53,19 +53,19 @@ class instruction_count : public iss::vm_plugin { public: instruction_count() = delete; - instruction_count(const instruction_count &) = delete; + instruction_count(const instruction_count&) = delete; - instruction_count(const instruction_count &&) = delete; + instruction_count(const instruction_count&&) = delete; instruction_count(std::string config_file_name); virtual ~instruction_count(); - instruction_count &operator=(const instruction_count &) = delete; + instruction_count& operator=(const instruction_count&) = delete; - instruction_count &operator=(const instruction_count &&) = delete; + instruction_count& operator=(const instruction_count&&) = delete; - bool registration(const char *const version, vm_if &arch) override; + bool registration(const char* const version, vm_if& arch) override; sync_type get_sync() override { return POST_SYNC; }; @@ -75,7 +75,7 @@ private: std::vector delays; std::vector rep_counts; }; -} -} +} // namespace plugin +} // namespace iss #endif /* _ISS_PLUGIN_INSTRUCTION_COUNTER_H_ */ diff --git a/src/main.cpp b/src/main.cpp index 03a68d0..61f3947 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -30,20 +30,20 @@ * *******************************************************************************/ -#include -#include #include +#include #include +#include +#include "iss/arch/tgc_mapper.h" #include #include -#include "iss/arch/tgc_mapper.h" #ifdef WITH_LLVM #include #endif -#include #include "iss/plugin/cycle_estimate.h" #include "iss/plugin/instruction_count.h" +#include #ifndef WIN32 #include #endif @@ -53,7 +53,7 @@ namespace po = boost::program_options; -int main(int argc, char *argv[]) { +int main(int argc, char* argv[]) { /* * Define and parse the program options */ @@ -79,12 +79,12 @@ int main(int argc, char *argv[]) { try { po::store(parsed, clim); // can throw // --help option - if (clim.count("help")) { + if(clim.count("help")) { std::cout << "DBT-RISE-TGC simulator for TGC RISC-V cores" << std::endl << desc << std::endl; return 0; } po::notify(clim); // throws on error, so do after help in case - } catch (po::error &e) { + } catch(po::error& e) { // there are problems std::cerr << "ERROR: " << e.what() << std::endl << std::endl; std::cerr << desc << std::endl; @@ -97,14 +97,14 @@ int main(int argc, char *argv[]) { auto l = logging::as_log_level(clim["verbose"].as()); LOGGER(DEFAULT)::reporting_level() = l; LOGGER(connection)::reporting_level() = l; - if (clim.count("logfile")) { + if(clim.count("logfile")) { // configure the connection logger auto f = fopen(clim["logfile"].as().c_str(), "w"); LOG_OUTPUT(DEFAULT)::stream() = f; LOG_OUTPUT(connection)::stream() = f; } - std::vector plugin_list; + std::vector plugin_list; auto res = 0; try { #ifdef WITH_LLVM @@ -112,51 +112,51 @@ int main(int argc, char *argv[]) { iss::init_jit_debug(argc, argv); #endif bool dump = clim.count("dump-ir"); - auto & f = iss::core_factory::instance(); + auto& f = iss::core_factory::instance(); // instantiate the simulator iss::vm_ptr vm{nullptr}; iss::cpu_ptr cpu{nullptr}; std::string isa_opt(clim["isa"].as()); - if(isa_opt.size()==0 || isa_opt == "?") { + if(isa_opt.size() == 0 || isa_opt == "?") { auto list = f.get_names(); std::sort(std::begin(list), std::end(list)); - std::cout<<"Available implementations (core|platform|backend):\n - "<(), clim["gdb-port"].as()); + } else if(isa_opt.find('|') != std::string::npos) { + std::tie(cpu, vm) = f.create(isa_opt + "|" + clim["backend"].as(), clim["gdb-port"].as()); } else { auto base_isa = isa_opt.substr(0, 5); - if(base_isa=="tgc5d" || base_isa=="tgc5e") { - isa_opt += "|mu_p_clic_pmp|"+clim["backend"].as(); + if(base_isa == "tgc5d" || base_isa == "tgc5e") { + isa_opt += "|mu_p_clic_pmp|" + clim["backend"].as(); } else { - isa_opt += "|m_p|"+clim["backend"].as(); + isa_opt += "|m_p|" + clim["backend"].as(); } std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as()); } - if(!cpu ){ - LOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " <()<< std::endl; + if(!cpu) { + LOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as() << std::endl; return 127; } - if(!vm ){ - LOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " <()<< std::endl; + if(!vm) { + LOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " << clim["backend"].as() << std::endl; return 127; } - if (clim.count("plugin")) { - for (std::string const& opt_val : clim["plugin"].as>()) { - std::string plugin_name=opt_val; + if(clim.count("plugin")) { + for(std::string const& opt_val : clim["plugin"].as>()) { + std::string plugin_name = opt_val; std::string arg{""}; std::size_t found = opt_val.find('='); - if (found != std::string::npos) { + if(found != std::string::npos) { plugin_name = opt_val.substr(0, found); arg = opt_val.substr(found + 1, opt_val.size()); } #if defined(WITH_PLUGINS) - if (plugin_name == "ic") { - auto *ic_plugin = new iss::plugin::instruction_count(arg); + if(plugin_name == "ic") { + auto* ic_plugin = new iss::plugin::instruction_count(arg); vm->register_plugin(*ic_plugin); plugin_list.push_back(ic_plugin); - } else if (plugin_name == "ce") { - auto *ce_plugin = new iss::plugin::cycle_estimate(arg); + } else if(plugin_name == "ce") { + auto* ce_plugin = new iss::plugin::cycle_estimate(arg); vm->register_plugin(*ce_plugin); plugin_list.push_back(ce_plugin); } else @@ -168,7 +168,7 @@ int main(int argc, char *argv[]) { a.push_back({arg.c_str()}); iss::plugin::loader l(plugin_name, {{"initPlugin"}}); auto* plugin = l.call_function("initPlugin", a.size(), a.data()); - if(plugin){ + if(plugin) { vm->register_plugin(*plugin); plugin_list.push_back(plugin); } else @@ -180,42 +180,43 @@ int main(int argc, char *argv[]) { } } } - if (clim.count("disass")) { + if(clim.count("disass")) { vm->setDisassEnabled(true); LOGGER(disass)::reporting_level() = logging::INFO; LOGGER(disass)::print_time() = false; auto file_name = clim["disass"].as(); - if (file_name.length() > 0) { + if(file_name.length() > 0) { LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w"); LOGGER(disass)::print_severity() = false; } } uint64_t start_address = 0; - if (clim.count("mem")) + if(clim.count("mem")) vm->get_arch()->load_file(clim["mem"].as()); - if (clim.count("elf")) - for (std::string input : clim["elf"].as>()) { + if(clim.count("elf")) + for(std::string input : clim["elf"].as>()) { auto start_addr = vm->get_arch()->load_file(input); - if (start_addr.second) start_address = start_addr.first; + if(start_addr.second) + start_address = start_addr.first; } - for (std::string input : args) { + for(std::string input : args) { auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files - if (start_addr.second) start_address = start_addr.first; + if(start_addr.second) + start_address = start_addr.first; } - if (clim.count("reset")) { + if(clim.count("reset")) { auto str = clim["reset"].as(); start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), nullptr, 16) : std::stoull(str, nullptr, 10); } vm->reset(start_address); auto cycles = clim["instructions"].as(); res = vm->start(cycles, dump); - } catch (std::exception &e) { - LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" - << std::endl; + } catch(std::exception& e) { + LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl; res = 2; } // cleanup to let plugins report of needed - for (auto *p : plugin_list) { + for(auto* p : plugin_list) { delete p; } return res; diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp index 051b0d7..e7cfbbc 100644 --- a/src/sysc/core_complex.cpp +++ b/src/sysc/core_complex.cpp @@ -55,8 +55,10 @@ // clang-format on #define STR(X) #X -#define CREATE_CORE(CN) \ -if (type == STR(CN)) { std::tie(cpu, vm) = create_core(backend, gdb_port, hart_id); } else +#define CREATE_CORE(CN) \ + if(type == STR(CN)) { \ + std::tie(cpu, vm) = create_core(backend, gdb_port, hart_id); \ + } else #ifdef HAS_SCV #include @@ -87,23 +89,22 @@ using namespace sc_core; namespace { iss::debugger::encoder_decoder encdec; std::array lvl = {{'U', 'S', 'H', 'M'}}; -} +} // namespace -int cmd_sysc(int argc, char *argv[], debugger::out_func of, debugger::data_func df, - debugger::target_adapter_if *tgt_adapter) { - if (argc > 1) { - if (strcasecmp(argv[1], "print_time") == 0) { +int cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func df, debugger::target_adapter_if* tgt_adapter) { + if(argc > 1) { + if(strcasecmp(argv[1], "print_time") == 0) { std::string t = sc_time_stamp().to_string(); of(t.c_str()); std::array buf; encdec.enc_string(t.c_str(), buf.data(), 63); df(buf.data()); return Ok; - } else if (strcasecmp(argv[1], "break") == 0) { + } else if(strcasecmp(argv[1], "break") == 0) { sc_time t; - if (argc == 4) { + if(argc == 4) { t = scc::parse_from_string(argv[2], argv[3]); - } else if (argc == 3) { + } else if(argc == 3) { t = scc::parse_from_string(argv[2]); } else return Err; @@ -120,17 +121,19 @@ int cmd_sysc(int argc, char *argv[], debugger::out_func of, debugger::data_func } using cpu_ptr = std::unique_ptr; -using vm_ptr= std::unique_ptr; +using vm_ptr = std::unique_ptr; class core_wrapper { public: - core_wrapper(core_complex *owner) : owner(owner) { } + core_wrapper(core_complex* owner) + : owner(owner) {} - void reset(uint64_t addr){vm->reset(addr);} - inline void start(bool dump = false){vm->start(std::numeric_limits::max(), dump);} - inline std::pair load_file(std::string const& name){ + void reset(uint64_t addr) { vm->reset(addr); } + inline void start(bool dump = false) { vm->start(std::numeric_limits::max(), dump); } + inline std::pair load_file(std::string const& name) { iss::arch_if* cc = cpu->get_arch_if(); - return cc->load_file(name);}; + return cc->load_file(name); + }; std::function get_mode; std::function get_state; @@ -138,26 +141,26 @@ public: std::function set_interrupt_execution; std::function local_irq; - void create_cpu(std::string const& type, std::string const& backend, unsigned gdb_port, uint32_t hart_id){ - auto & f = sysc::iss_factory::instance(); - if(type.size()==0 || type == "?") { - std::cout<<"Available cores: "<(cpu.get()); sc_cpu_if->set_mhartid(hart_id); @@ -167,59 +170,59 @@ public: set_interrupt_execution = [sc_cpu_if](bool b) { return sc_cpu_if->set_interrupt_execution(b); }; local_irq = [sc_cpu_if](short s, bool b) { return sc_cpu_if->local_irq(s, b); }; - auto *srv = debugger::server::get(); - if (srv) tgt_adapter = srv->get_target(); - if (tgt_adapter) - tgt_adapter->add_custom_command( - {"sysc", [this](int argc, char *argv[], debugger::out_func of, - debugger::data_func df) -> int { return cmd_sysc(argc, argv, of, df, tgt_adapter); }, - "SystemC sub-commands: break