From 71b976811b43557fa0610aef01989d54df841a2c Mon Sep 17 00:00:00 2001
From: eyck <eyck@minres.com>
Date: Thu, 18 Jun 2020 09:58:43 +0200
Subject: [PATCH] add backend selection

---
 incl/sysc/core_complex.h  | 26 ++++++++++++++------------
 src/sysc/core_complex.cpp | 28 +++++++++++++++-------------
 2 files changed, 29 insertions(+), 25 deletions(-)

diff --git a/incl/sysc/core_complex.h b/incl/sysc/core_complex.h
index bef6804..21bb219 100644
--- a/incl/sysc/core_complex.h
+++ b/incl/sysc/core_complex.h
@@ -75,31 +75,33 @@ class core_wrapper;
 
 class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
-    scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator;
+    scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator{"intor"};
 
-    sc_core::sc_in<sc_core::sc_time> clk_i;
+    sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
 
-    sc_core::sc_in<bool> rst_i;
+    sc_core::sc_in<bool> rst_i{"rst_i"};
 
-    sc_core::sc_in<bool> global_irq_i;
+    sc_core::sc_in<bool> global_irq_i{"global_irq_i"};
 
-    sc_core::sc_in<bool> timer_irq_i;
+    sc_core::sc_in<bool> timer_irq_i{"timer_irq_i"};
 
-    sc_core::sc_in<bool> sw_irq_i;
+    sc_core::sc_in<bool> sw_irq_i{"sw_irq_i"};
 
-    sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i;
+    sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i{"local_irq_i", 16};
 
     sc_core::sc_port<tlm::tlm_peek_if<uint64_t>, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o;
 
-    cci::cci_param<std::string> elf_file;
+    cci::cci_param<std::string> elf_file{"elf_file", ""};
 
-    cci::cci_param<bool> enable_disass;
+    cci::cci_param<bool> enable_disass{"enable_disass", false};
 
-    cci::cci_param<uint64_t> reset_address;
+    cci::cci_param<uint64_t> reset_address{"reset_address", 0ULL};
 
-    cci::cci_param<unsigned short> gdb_server_port;
+    cci::cci_param<std::string> backend{"backend", "tcc"};
 
-    cci::cci_param<bool> dump_ir;
+    cci::cci_param<unsigned short> gdb_server_port{"gdb_server_port", 0};
+
+    cci::cci_param<bool> dump_ir{"dump_ir", false};
 
     core_complex(sc_core::sc_module_name name);
 
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 12b8ec9..713f3cc 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -234,17 +234,6 @@ int cmd_sysc(int argc, char *argv[], debugger::out_func of, debugger::data_func
 
 core_complex::core_complex(sc_module_name name)
 : sc_module(name)
-, NAMED(initiator)
-, NAMED(clk_i)
-, NAMED(rst_i)
-, NAMED(global_irq_i)
-, NAMED(timer_irq_i)
-, NAMED(local_irq_i, 16)
-, NAMED(elf_file, "")
-, NAMED(enable_disass, false)
-, NAMED(reset_address, 0ULL)
-, NAMED(gdb_server_port, 0)
-, NAMED(dump_ir, false)
 , read_lut(tlm_dmi_ext())
 , write_lut(tlm_dmi_ext())
 , tgt_adapter(nullptr)
@@ -284,10 +273,23 @@ core_complex::~core_complex() = default;
 
 void core_complex::trace(sc_trace_file *trf) const {}
 
+using vm_ptr= std::unique_ptr<iss::vm_if>;
+vm_ptr create_cpu(core_wrapper* cpu, std::string const& backend, unsigned gdb_port){
+    if(backend == "interp")
+        return vm_ptr{iss::interp::create<core_type>(cpu, gdb_port)};
+#ifdef WITH_LLVM
+    if(backend == "llvm")
+        return vm_ptr{iss::llvm::create(lcpu, gdb_port)};
+#endif
+    if(backend == "tcc")
+        return vm_ptr{iss::tcc::create<core_type>(cpu, gdb_port)};
+    return {nullptr};
+}
+
 void core_complex::before_end_of_elaboration() {
+    SCCDEBUG(SCMOD)<<"instantiating iss::arch::mnrv32 with "<<backend.get_value()<<" backend";
     cpu = scc::make_unique<core_wrapper>(this);
-    //vm = tcc::create<core_type>(cpu.get(), gdb_server_port.get_value(), dump_ir.get_value());
-    vm = interp::create<core_type>(cpu.get(), gdb_server_port.get_value(), dump_ir.get_value());
+    vm = create_cpu(cpu.get(), backend.get_value(), gdb_server_port.get_value());
 #ifdef WITH_SCV
     vm->setDisassEnabled(enable_disass.get_value() || m_db != nullptr);
 #else