From 710d61e30451ccb6511e8e53b6274b142bac8a26 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Mon, 25 Sep 2017 20:38:40 +0200 Subject: [PATCH] Fixed target adapter to properly handle register reading --- CMakeLists.txt | 5 ++-- cmake/FindTcmalloc.cmake | 38 ++++++++++++++++++++++++ dbt-core | 2 +- riscv.sc/src/CMakeLists.txt | 3 ++ riscv/src/CMakeLists.txt | 3 ++ riscv/src/internal/vm_riscv.in.cpp | 44 +++++++++++++++------------- riscv/src/internal/vm_rv32imac.cpp | 47 +++++++++++++++++------------- sc-components | 2 +- 8 files changed, 99 insertions(+), 45 deletions(-) create mode 100644 cmake/FindTcmalloc.cmake diff --git a/CMakeLists.txt b/CMakeLists.txt index 916d87b..13b253b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -17,8 +17,8 @@ include(cmake/Submodules.cmake) if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" OR "${CMAKE_CXX_COMPILER_ID}" STREQUAL "Clang") set(warnings "-Wall -Wextra -Werror") - set(CMAKE_CXX_FLAG_RELEASE "-O2 -DNDEBUG") - set(CMAKE_C_FLAG_RELEASE "-O2 -DNDEBUG") + set(CMAKE_CXX_FLAG_RELEASE "-O3 -DNDEBUG") + set(CMAKE_C_FLAG_RELEASE "-O3 -DNDEBUG") set(CMAKE_CXX_FLAG_DEBUG "-Og") set(CMAKE_C_FLAG_DEBUG "-Og") elseif ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC") @@ -26,6 +26,7 @@ elseif ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC") endif() FIND_PACKAGE(Threads) +FIND_PACKAGE(Tcmalloc) set(PROJECT_3PARTY_DIRS external sr_report sr_signal) include(sc-components/cmake/clang-format.cmake) diff --git a/cmake/FindTcmalloc.cmake b/cmake/FindTcmalloc.cmake new file mode 100644 index 0000000..24c2600 --- /dev/null +++ b/cmake/FindTcmalloc.cmake @@ -0,0 +1,38 @@ +# - Find Tcmalloc +# Find the native Tcmalloc library +# +# Tcmalloc_LIBRARIES - List of libraries when using Tcmalloc. +# Tcmalloc_FOUND - True if Tcmalloc found. + +if (USE_TCMALLOC) + set(Tcmalloc_NAMES tcmalloc) +else () + set(Tcmalloc_NAMES tcmalloc_minimal tcmalloc) +endif () + +find_library(Tcmalloc_LIBRARY NO_DEFAULT_PATH + NAMES ${Tcmalloc_NAMES} + PATHS ${HT_DEPENDENCY_LIB_DIR} /lib /usr/lib /usr/local/lib /opt/local/lib +) + +if (Tcmalloc_LIBRARY) + set(Tcmalloc_FOUND TRUE) + set( Tcmalloc_LIBRARIES ${Tcmalloc_LIBRARY} ) +else () + set(Tcmalloc_FOUND FALSE) + set( Tcmalloc_LIBRARIES ) +endif () + +if (Tcmalloc_FOUND) + message(STATUS "Found Tcmalloc: ${Tcmalloc_LIBRARY}") +else () + message(STATUS "Not Found Tcmalloc: ${Tcmalloc_LIBRARY}") + if (Tcmalloc_FIND_REQUIRED) + message(STATUS "Looked for Tcmalloc libraries named ${Tcmalloc_NAMES}.") + message(FATAL_ERROR "Could NOT find Tcmalloc library") + endif () +endif () + +mark_as_advanced( + Tcmalloc_LIBRARY +) \ No newline at end of file diff --git a/dbt-core b/dbt-core index f8b8425..743e314 160000 --- a/dbt-core +++ b/dbt-core @@ -1 +1 @@ -Subproject commit f8b842549e961d88cd7122c9d210ebe198283c85 +Subproject commit 743e314de55023df0942c5de146c109a0b8b1513 diff --git a/riscv.sc/src/CMakeLists.txt b/riscv.sc/src/CMakeLists.txt index 871c18e..beb930c 100644 --- a/riscv.sc/src/CMakeLists.txt +++ b/riscv.sc/src/CMakeLists.txt @@ -44,6 +44,9 @@ if(SCV_FOUND) target_link_libraries (${APPLICATION_NAME} ${SCV_LIBRARIES}) endif() target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} ) +if (Tcmalloc_FOUND) + target_link_libraries(${APPLICATION_NAME} ${Tcmalloc_LIBRARIES}) +endif(Tcmalloc_FOUND) # Says how and where to install software # Targets: diff --git a/riscv/src/CMakeLists.txt b/riscv/src/CMakeLists.txt index 206d25c..927436b 100644 --- a/riscv/src/CMakeLists.txt +++ b/riscv/src/CMakeLists.txt @@ -36,6 +36,9 @@ target_link_libraries(${APPLICATION_NAME} sc-components) target_link_libraries(${APPLICATION_NAME} external) target_link_libraries(${APPLICATION_NAME} ${llvm_libs}) target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} ) +if (Tcmalloc_FOUND) + target_link_libraries(${APPLICATION_NAME} ${Tcmalloc_LIBRARIES}) +endif(Tcmalloc_FOUND) # Says how and where to install software # Targets: diff --git a/riscv/src/internal/vm_riscv.in.cpp b/riscv/src/internal/vm_riscv.in.cpp index c878a15..362ec61 100644 --- a/riscv/src/internal/vm_riscv.in.cpp +++ b/riscv/src/internal/vm_riscv.in.cpp @@ -485,14 +485,12 @@ status target_adapter::read_registers(std::vector &data, std::vec // return idx<0?:; data.clear(); avail.clear(); - std::vector reg_data; + const uint8_t* reg_base = vm->get_arch()->get_regs_base_ptr(); for (size_t reg_no = 0; reg_no < arch::traits::NUM_REGS; ++reg_no) { - auto reg_bit_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no)); - auto reg_width = reg_bit_width / 8; - reg_data.resize(reg_width); - vm->get_arch()->get_reg(reg_no, reg_data); - for (size_t j = 0; j < reg_data.size(); ++j) { - data.push_back(reg_data[j]); + auto reg_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; + unsigned offset = traits::reg_byte_offset(reg_no); + for (size_t j = 0; j < reg_width; ++j) { + data.push_back(*(reg_base+offset+j)); avail.push_back(0xff); } } @@ -510,15 +508,15 @@ status target_adapter::read_registers(std::vector &data, std::vec } template status target_adapter::write_registers(const std::vector &data) { - size_t data_index = 0; auto reg_count = arch::traits::NUM_REGS; - std::vector reg_data; + auto* reg_base = vm->get_arch()->get_regs_base_ptr(); + auto iter = data.data(); for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) { - auto reg_bit_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no)); - auto reg_width = reg_bit_width / 8; - vm->get_arch()->set_reg(reg_no, - std::vector(data.begin() + data_index, data.begin() + data_index + reg_width)); - data_index += reg_width; + auto reg_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; + auto offset = traits::reg_byte_offset(reg_no); + std::copy(iter , iter + reg_width, reg_base); + iter+=4; + reg_base+=offset; } return Ok; } @@ -529,9 +527,12 @@ status target_adapter::read_single_register(unsigned int reg_no, std::vect if (reg_no < 65) { // auto reg_size = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; - data.resize(0); - vm->get_arch()->get_reg(reg_no, data); - avail.resize(data.size()); + auto* reg_base = vm->get_arch()->get_regs_base_ptr(); + auto reg_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; + data.resize(reg_width); + avail.resize(reg_width); + auto offset = traits::reg_byte_offset(reg_no); + std::copy(reg_base+offset, reg_base+offset+reg_width, data.begin()); std::fill(avail.begin(), avail.end(), 0xff); } else { typed_addr_t a(iss::DEBUG_READ, traits::CSR, reg_no - 65); @@ -545,9 +546,12 @@ status target_adapter::read_single_register(unsigned int reg_no, std::vect template status target_adapter::write_single_register(unsigned int reg_no, const std::vector &data) { - if (reg_no < 65) - vm->get_arch()->set_reg(reg_no, data); - else { + if (reg_no < 65){ + auto* reg_base = vm->get_arch()->get_regs_base_ptr(); + auto reg_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; + auto offset = traits::reg_byte_offset(reg_no); + std::copy(data.begin(), data.begin() + reg_width, reg_base+offset); + } else { typed_addr_t a(iss::DEBUG_WRITE, traits::CSR, reg_no - 65); vm->get_arch()->write(a, data.size(), data.data()); } diff --git a/riscv/src/internal/vm_rv32imac.cpp b/riscv/src/internal/vm_rv32imac.cpp index 9464eef..1d69c8d 100644 --- a/riscv/src/internal/vm_rv32imac.cpp +++ b/riscv/src/internal/vm_rv32imac.cpp @@ -4094,7 +4094,8 @@ template inline void vm_impl::gen_trap_check(llvm::BasicBl #define CREATE_FUNCS(ARCH) \ template <> std::unique_ptr create(ARCH * core, unsigned short port, bool dump) { \ - std::unique_ptr> ret = std::make_unique>(*core, dump); \ + std::unique_ptr> ret = \ + std::make_unique>(*core, dump); \ debugger::server::run_server(ret.get(), port); \ return ret; \ } \ @@ -4157,14 +4158,12 @@ status target_adapter::read_registers(std::vector &data, std::vec // return idx<0?:; data.clear(); avail.clear(); - std::vector reg_data; + const uint8_t* reg_base = vm->get_arch()->get_regs_base_ptr(); for (size_t reg_no = 0; reg_no < arch::traits::NUM_REGS; ++reg_no) { - auto reg_bit_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no)); - auto reg_width = reg_bit_width / 8; - reg_data.resize(reg_width); - vm->get_arch()->get_reg(reg_no, reg_data); - for (size_t j = 0; j < reg_data.size(); ++j) { - data.push_back(reg_data[j]); + auto reg_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; + unsigned offset = traits::reg_byte_offset(reg_no); + for (size_t j = 0; j < reg_width; ++j) { + data.push_back(*(reg_base+offset+j)); avail.push_back(0xff); } } @@ -4182,15 +4181,15 @@ status target_adapter::read_registers(std::vector &data, std::vec } template status target_adapter::write_registers(const std::vector &data) { - size_t data_index = 0; auto reg_count = arch::traits::NUM_REGS; - std::vector reg_data; + auto* reg_base = vm->get_arch()->get_regs_base_ptr(); + auto iter = data.data(); for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) { - auto reg_bit_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no)); - auto reg_width = reg_bit_width / 8; - vm->get_arch()->set_reg(reg_no, - std::vector(data.begin() + data_index, data.begin() + data_index + reg_width)); - data_index += reg_width; + auto reg_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; + auto offset = traits::reg_byte_offset(reg_no); + std::copy(iter , iter + reg_width, reg_base); + iter+=4; + reg_base+=offset; } return Ok; } @@ -4201,9 +4200,12 @@ status target_adapter::read_single_register(unsigned int reg_no, std::vect if (reg_no < 65) { // auto reg_size = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; - data.resize(0); - vm->get_arch()->get_reg(reg_no, data); - avail.resize(data.size()); + auto* reg_base = vm->get_arch()->get_regs_base_ptr(); + auto reg_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; + data.resize(reg_width); + avail.resize(reg_width); + auto offset = traits::reg_byte_offset(reg_no); + std::copy(reg_base+offset, reg_base+offset+reg_width, data.begin()); std::fill(avail.begin(), avail.end(), 0xff); } else { typed_addr_t a(iss::DEBUG_READ, traits::CSR, reg_no - 65); @@ -4217,9 +4219,12 @@ status target_adapter::read_single_register(unsigned int reg_no, std::vect template status target_adapter::write_single_register(unsigned int reg_no, const std::vector &data) { - if (reg_no < 65) - vm->get_arch()->set_reg(reg_no, data); - else { + if (reg_no < 65){ + auto* reg_base = vm->get_arch()->get_regs_base_ptr(); + auto reg_width = arch::traits::reg_bit_width(static_cast::reg_e>(reg_no))/8; + auto offset = traits::reg_byte_offset(reg_no); + std::copy(data.begin(), data.begin() + reg_width, reg_base+offset); + } else { typed_addr_t a(iss::DEBUG_WRITE, traits::CSR, reg_no - 65); vm->get_arch()->write(a, data.size(), data.data()); } diff --git a/sc-components b/sc-components index 8272a27..c852e82 160000 --- a/sc-components +++ b/sc-components @@ -1 +1 @@ -Subproject commit 8272a27a0ef24d8b7b596ae8dc5adeb6f422f1b2 +Subproject commit c852e8228d4351ea672a2367fd36ce8965ff3347