From d7bddd825c131e1f6de0bf55886c5e6f5e3a15ee Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Tue, 27 Jul 2021 10:47:48 +0200
Subject: [PATCH] add clic CSRs

---
 incl/iss/arch/riscv_hart_common.h |  7 +++++++
 incl/iss/arch/riscv_hart_mu_p.h   | 18 +++++++++++++++++-
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/incl/iss/arch/riscv_hart_common.h b/incl/iss/arch/riscv_hart_common.h
index ee87b45..7cd6f72 100644
--- a/incl/iss/arch/riscv_hart_common.h
+++ b/incl/iss/arch/riscv_hart_common.h
@@ -104,12 +104,19 @@ enum riscv_csr {
     mie = 0x304,
     mtvec = 0x305,
     mcounteren = 0x306,
+    mtvt = 0x307, //CLIC
     // Machine Trap Handling
     mscratch = 0x340,
     mepc = 0x341,
     mcause = 0x342,
     mtval = 0x343,
     mip = 0x344,
+    mxnti = 0x345, //CLIC
+    mintstatus   = 0x346, // MRW Current interrupt levels (CLIC) - addr subject to change
+    mscratchcsw  = 0x348, // MRW Conditional scratch swap on priv mode change (CLIC)
+    mscratchcswl = 0x349, // MRW Conditional scratch swap on level change (CLIC)
+    mintthresh   = 0x350, // MRW Interrupt-level threshold (CLIC) - addr subject to change
+    mclicbase    = 0x351, // MRW Base address for CLIC memory mapped registers (CLIC) - addr subject to change
     // Physical Memory Protection
     pmpcfg0 = 0x3A0,
     pmpcfg1 = 0x3A1,
diff --git a/incl/iss/arch/riscv_hart_mu_p.h b/incl/iss/arch/riscv_hart_mu_p.h
index 7a7267a..2215eeb 100644
--- a/incl/iss/arch/riscv_hart_mu_p.h
+++ b/incl/iss/arch/riscv_hart_mu_p.h
@@ -66,7 +66,7 @@
 namespace iss {
 namespace arch {
 
-enum features_e{FEAT_NONE, FEAT_PMP, FEAT_EXT_N};
+enum features_e{FEAT_NONE, FEAT_PMP, FEAT_EXT_N, FEAT_CLIC};
 
 template <typename BASE, features_e FEAT=FEAT_NONE> class riscv_hart_mu_p : public BASE {
 protected:
@@ -406,6 +406,22 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p()
         csr_rd_cb[medeleg] = &this_class::read_reg;
         csr_wr_cb[medeleg] = &this_class::write_reg;
     }
+    if(FEAT & FEAT_CLIC) {
+        csr_rd_cb[mtvt] = &this_class::read_reg;
+        csr_wr_cb[mtvt] = &this_class::write_reg;
+        csr_rd_cb[mxnti] = &this_class::read_reg;
+        csr_wr_cb[mxnti] = &this_class::write_reg;
+        csr_rd_cb[mintstatus] = &this_class::read_reg;
+        csr_wr_cb[mintstatus] = &this_class::write_reg;
+        csr_rd_cb[mscratchcsw] = &this_class::read_reg;
+        csr_wr_cb[mscratchcsw] = &this_class::write_reg;
+        csr_rd_cb[mscratchcswl] = &this_class::read_reg;
+        csr_wr_cb[mscratchcswl] = &this_class::write_reg;
+        csr_rd_cb[mintthresh] = &this_class::read_reg;
+        csr_wr_cb[mintthresh] = &this_class::write_reg;
+        csr_rd_cb[mclicbase] = &this_class::read_reg;
+        csr_wr_cb[mclicbase] = &this_class::write_reg;
+    }
 }
 
 template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_mu_p<BASE, FEAT>::load_file(std::string name, int type) {