From 57347ae4d9fc87bc6412c5afbe295299752fd369 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sat, 23 Jul 2022 13:48:55 +0200 Subject: [PATCH] fixes cppcheck flagged issues --- src/iss/arch/riscv_hart_m_p.h | 22 +++++++++++----------- src/iss/arch/riscv_hart_mu_p.h | 26 +++++++++++++------------- 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index c0059b2..8365a5d 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -477,10 +477,10 @@ template std::pair riscv_hart_m if (fp) { std::array buf; auto n = fread(buf.data(), 1, 4, fp); + fclose(fp); if (n != 4) throw std::runtime_error("input file has insufficient size"); buf[4] = 0; if (strcmp(buf.data() + 1, "ELF") == 0) { - fclose(fp); // Create elfio reader ELFIO::elfio reader; // Load ELF data @@ -571,12 +571,12 @@ iss::status riscv_hart_m_p::read(const address_type type, const acce if (unlikely(is_fetch(access) && (addr&(alignment-1)))) { fault_data = addr; if (is_debug(access)) throw trap_access(0, addr); - this->trap_state = (1 << 31); // issue trap 0 + this->trap_state = (1UL << 31); // issue trap 0 return iss::Err; } try { if(!is_debug(access) && (addr&(alignment-1))){ - this->trap_state = 1<<31 | 4<<16; + this->trap_state = (1UL << 31) | 4<<16; fault_data=addr; return iss::Err; } @@ -595,12 +595,12 @@ iss::status riscv_hart_m_p::read(const address_type type, const acce res = read_mem( phys_addr, length, data); } if (unlikely(res != iss::Ok)){ - this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault + this->trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault fault_data=addr; } return res; } catch (trap_access &ta) { - this->trap_state = (1 << 31) | ta.id; + this->trap_state = (1UL << 31) | ta.id; fault_data=ta.addr; return iss::Err; } @@ -626,7 +626,7 @@ iss::status riscv_hart_m_p::read(const address_type type, const acce } return iss::Ok; } catch (trap_access &ta) { - this->trap_state = (1 << 31) | ta.id; + this->trap_state = (1UL << 31) | ta.id; fault_data=ta.addr; return iss::Err; } @@ -664,12 +664,12 @@ iss::status riscv_hart_m_p::write(const address_type type, const acc if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) { fault_data = addr; if (access && iss::access_type::DEBUG) throw trap_access(0, addr); - this->trap_state = (1 << 31); // issue trap 0 + this->trap_state = (1UL << 31); // issue trap 0 return iss::Err; } try { if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){ - this->trap_state = 1<<31 | 6<<16; + this->trap_state = (1UL << 31) | 6<<16; fault_data=addr; return iss::Err; } @@ -688,12 +688,12 @@ iss::status riscv_hart_m_p::write(const address_type type, const acc res = write_mem( phys_addr, length, data); } if (unlikely(res != iss::Ok)) { - this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault) + this->trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault) fault_data=addr; } return res; } catch (trap_access &ta) { - this->trap_state = (1 << 31) | ta.id; + this->trap_state = (1UL << 31) | ta.id; fault_data=ta.addr; return iss::Err; } @@ -753,7 +753,7 @@ iss::status riscv_hart_m_p::write(const address_type type, const acc } return iss::Ok; } catch (trap_access &ta) { - this->trap_state = (1 << 31) | ta.id; + this->trap_state = (1UL << 31) | ta.id; fault_data=ta.addr; return iss::Err; } diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 1cf8484..87ff8b9 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -526,10 +526,10 @@ template std::pair riscv_hart_m if (fp) { std::array buf; auto n = fread(buf.data(), 1, 4, fp); + fclose(fp); if (n != 4) throw std::runtime_error("input file has insufficient size"); buf[4] = 0; if (strcmp(buf.data() + 1, "ELF") == 0) { - fclose(fp); // Create elfio reader ELFIO::elfio reader; // Load ELF data @@ -708,7 +708,7 @@ iss::status riscv_hart_mu_p::read(const address_type type, const acc if(!pmp_check(access, addr, length) && !is_debug(access)) { fault_data = addr; if (is_debug(access)) throw trap_access(0, addr); - this->trap_state = (1 << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1 + this->trap_state = (1UL << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1 return iss::Err; } } @@ -716,12 +716,12 @@ iss::status riscv_hart_mu_p::read(const address_type type, const acc if (unlikely(is_fetch(access) && (addr&(alignment-1)))) { fault_data = addr; if (is_debug(access)) throw trap_access(0, addr); - this->trap_state = (1 << 31); // issue trap 0 + this->trap_state = (1UL << 31); // issue trap 0 return iss::Err; } try { if(!is_debug(access) && (addr&(alignment-1))){ - this->trap_state = 1<<31 | 4<<16; + this->trap_state = (1UL << 31) | 4<<16; fault_data=addr; return iss::Err; } @@ -740,12 +740,12 @@ iss::status riscv_hart_mu_p::read(const address_type type, const acc res = read_mem( phys_addr, length, data); } if (unlikely(res != iss::Ok)){ - this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault + this->trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault fault_data=addr; } return res; } catch (trap_access &ta) { - this->trap_state = (1 << 31) | ta.id; + this->trap_state = (1UL << 31) | ta.id; fault_data=ta.addr; return iss::Err; } @@ -771,7 +771,7 @@ iss::status riscv_hart_mu_p::read(const address_type type, const acc } return iss::Ok; } catch (trap_access &ta) { - this->trap_state = (1 << 31) | ta.id; + this->trap_state = (1UL << 31) | ta.id; fault_data=ta.addr; return iss::Err; } @@ -810,19 +810,19 @@ iss::status riscv_hart_mu_p::write(const address_type type, const ac if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) { fault_data = addr; if (access && iss::access_type::DEBUG) throw trap_access(0, addr); - this->trap_state = (1 << 31) | (7 << 16); // issue trap 1 + this->trap_state = (1UL << 31) | (7 << 16); // issue trap 1 return iss::Err; } } if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) { fault_data = addr; if (access && iss::access_type::DEBUG) throw trap_access(0, addr); - this->trap_state = (1 << 31); // issue trap 0 + this->trap_state = (1UL << 31); // issue trap 0 return iss::Err; } try { if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){ - this->trap_state = 1<<31 | 6<<16; + this->trap_state = (1UL << 31) | 6<<16; fault_data=addr; return iss::Err; } @@ -841,12 +841,12 @@ iss::status riscv_hart_mu_p::write(const address_type type, const ac res = write_mem( phys_addr, length, data); } if (unlikely(res != iss::Ok)) { - this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault) + this->trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault) fault_data=addr; } return res; } catch (trap_access &ta) { - this->trap_state = (1 << 31) | ta.id; + this->trap_state = (1UL << 31) | ta.id; fault_data=ta.addr; return iss::Err; } @@ -906,7 +906,7 @@ iss::status riscv_hart_mu_p::write(const address_type type, const ac } return iss::Ok; } catch (trap_access &ta) { - this->trap_state = (1 << 31) | ta.id; + this->trap_state = (1UL << 31) | ta.id; fault_data=ta.addr; return iss::Err; }