diff --git a/.cproject b/.cproject index 0f174bb..c53663e 100644 --- a/.cproject +++ b/.cproject @@ -2,7 +2,7 @@ - + @@ -17,7 +17,7 @@ - + @@ -82,317 +82,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/dbt-core b/dbt-core index 7902b61..f8b8425 160000 --- a/dbt-core +++ b/dbt-core @@ -1 +1 @@ -Subproject commit 7902b61b2cb504defdbb48baf74c7facfa7c249c +Subproject commit f8b842549e961d88cd7122c9d210ebe198283c85 diff --git a/riscv.sc/incl/sysc/SiFive/core_complex.h b/riscv.sc/incl/sysc/SiFive/core_complex.h index 3d47de5..52835b9 100644 --- a/riscv.sc/incl/sysc/SiFive/core_complex.h +++ b/riscv.sc/incl/sysc/SiFive/core_complex.h @@ -51,7 +51,7 @@ public: sc_core::sc_in rst_i; core_complex(sc_core::sc_module_name name); - virtual ~core_complex(); + virtual ~core_complex() = default; }; } /* namespace SiFive */ diff --git a/riscv.sc/incl/sysc/SiFive/gpio.h b/riscv.sc/incl/sysc/SiFive/gpio.h index 04e1f07..25426c0 100644 --- a/riscv.sc/incl/sysc/SiFive/gpio.h +++ b/riscv.sc/incl/sysc/SiFive/gpio.h @@ -29,7 +29,7 @@ public: sc_core::sc_in clk_i; sc_core::sc_in rst_i; gpio(sc_core::sc_module_name nm); - virtual ~gpio(); + virtual ~gpio() override; // need to keep it in source file because of fwd declaration of gpio_regs protected: void clock_cb(); diff --git a/riscv.sc/incl/sysc/SiFive/plic.h b/riscv.sc/incl/sysc/SiFive/plic.h index 5ae5f25..7b0ec3c 100644 --- a/riscv.sc/incl/sysc/SiFive/plic.h +++ b/riscv.sc/incl/sysc/SiFive/plic.h @@ -29,7 +29,7 @@ public: sc_core::sc_in clk_i; sc_core::sc_in rst_i; plic(sc_core::sc_module_name nm); - virtual ~plic(); + virtual ~plic() override; protected: void clock_cb(); diff --git a/riscv.sc/incl/sysc/SiFive/spi.h b/riscv.sc/incl/sysc/SiFive/spi.h index cdf5aee..e896fc6 100644 --- a/riscv.sc/incl/sysc/SiFive/spi.h +++ b/riscv.sc/incl/sysc/SiFive/spi.h @@ -29,7 +29,7 @@ public: sc_core::sc_in clk_i; sc_core::sc_in rst_i; spi(sc_core::sc_module_name nm); - virtual ~spi(); + virtual ~spi() override; protected: void clock_cb(); diff --git a/riscv.sc/incl/sysc/SiFive/uart.h b/riscv.sc/incl/sysc/SiFive/uart.h index 6c80fc0..d119605 100644 --- a/riscv.sc/incl/sysc/SiFive/uart.h +++ b/riscv.sc/incl/sysc/SiFive/uart.h @@ -29,7 +29,7 @@ public: sc_core::sc_in clk_i; sc_core::sc_in rst_i; uart(sc_core::sc_module_name nm); - virtual ~uart(); + virtual ~uart() override; protected: void clock_cb(); diff --git a/riscv.sc/src/sysc/core_complex.cpp b/riscv.sc/src/sysc/core_complex.cpp index de360b0..e01bbdb 100644 --- a/riscv.sc/src/sysc/core_complex.cpp +++ b/riscv.sc/src/sysc/core_complex.cpp @@ -43,9 +43,6 @@ core_complex::core_complex(sc_core::sc_module_name name) : sc_core::sc_module(na // TODO Auto-generated constructor stub } -core_complex::~core_complex() { - // TODO Auto-generated destructor stub -} } /* namespace SiFive */ } /* namespace sysc */ diff --git a/riscv.sc/src/sysc/gpio.cpp b/riscv.sc/src/sysc/gpio.cpp index c449ef2..52509f1 100644 --- a/riscv.sc/src/sysc/gpio.cpp +++ b/riscv.sc/src/sysc/gpio.cpp @@ -29,10 +29,11 @@ gpio::gpio(sc_core::sc_module_name nm) sensitive << rst_i; } -gpio::~gpio() {} - void gpio::clock_cb() {} +gpio::~gpio() { +} + void gpio::reset_cb() { if (rst_i.read()) regs->reset_start(); diff --git a/riscv/incl/iss/arch/riscv_hart_msu_vp.h b/riscv/incl/iss/arch/riscv_hart_msu_vp.h index 086e111..bad36d8 100644 --- a/riscv/incl/iss/arch/riscv_hart_msu_vp.h +++ b/riscv/incl/iss/arch/riscv_hart_msu_vp.h @@ -240,7 +240,7 @@ struct trap_store_page_fault : public trap_access { }; } -typedef union { +using mstatus32_t = union { uint32_t val; struct /*mstatus*/ { uint32_t SD : 1, // SD bit is read-only and is set when either the FS or XS @@ -277,9 +277,9 @@ typedef union { uint32_t SD : 1, _WPRI4 : 11, MXR : 1, SUM : 1, _WPRI3 : 1, XS : 2, FS : 2, _WPRI2 : 8, UPIE : 1, _WPRI0 : 3, UIE : 1; } u; -} mstatus32_t; +} ; -typedef union { +using mstatus64_t = union { uint64_t val; struct /*mstatus*/ { uint64_t SD : 1, // SD bit is read-only and is set when either the FS or XS @@ -324,7 +324,7 @@ typedef union { UXL : 2, // value of XLEN for U-mode _WPRI3 : 12, MXR : 1, SUM : 1, _WPRI2 : 1, XS : 2, FS : 2, _WPRI1 : 8, UPIE : 1, _WPRI0 : 3, UIE : 1; } u; -} mstatus64_t; +} ; template inline vm_info decode_vm_info(uint32_t state, uint64_t sptbr); @@ -424,19 +424,19 @@ template struct riscv_hart_msu_vp : public BASE { } riscv_hart_msu_vp(); - virtual ~riscv_hart_msu_vp(); + virtual ~riscv_hart_msu_vp() = default; virtual void load_file(std::string name, int type = -1); virtual phys_addr_t v2p(const iss::addr_t &addr); - virtual iss::status read(const iss::addr_t &addr, unsigned length, uint8_t *const data) override; - virtual iss::status write(const iss::addr_t &addr, unsigned length, const uint8_t *const data) override; + iss::status read(const iss::addr_t &addr, unsigned length, uint8_t *const data) override; + iss::status write(const iss::addr_t &addr, unsigned length, const uint8_t *const data) override; virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data); } virtual uint64_t enter_trap(uint64_t flags, uint64_t addr) override; virtual uint64_t leave_trap(uint64_t flags) override; - virtual void wait_until(uint64_t flags) override; + void wait_until(uint64_t flags) override; virtual std::string get_additional_disass_info() { std::stringstream s; @@ -517,8 +517,6 @@ template riscv_hart_msu_vp::riscv_hart_msu_vp() : mstatus_ csr_wr_cb[satp] = &riscv_hart_msu_vp::write_satp; } -template riscv_hart_msu_vp::~riscv_hart_msu_vp() {} - template void riscv_hart_msu_vp::load_file(std::string name, int type) { FILE *fp = fopen(name.c_str(), "r"); if (fp) { @@ -941,7 +939,7 @@ typename riscv_hart_msu_vp::phys_addr_t riscv_hart_msu_vp::v2p(const return ret; } - const access_type type = (access_type)(addr.getAccessType() & ~iss::DEBUG); + const auto type = (access_type)(addr.getAccessType() & ~iss::DEBUG); uint32_t mode = type != iss::FETCH && bit_sub<17, 1>(mstatus_r) ? // MPRV mode = bit_sub<11, 2>(mstatus_r) : // MPV diff --git a/riscv/src/main.cpp b/riscv/src/main.cpp index 5b687bd..75a6a97 100644 --- a/riscv/src/main.cpp +++ b/riscv/src/main.cpp @@ -67,7 +67,7 @@ int main(int argc, char *argv[]) { iss::init_jit(argc, argv); bool dump = vm.count("dump-ir"); // instantiate the simulator - std::unique_ptr cpu = nullptr; + std::unique_ptr cpu{nullptr}; if (vm.count("rv64") == 1) { if (vm.count("gdb-port") == 1) cpu = iss::create("rv64ia", vm["gdb-port"].as(), dump); @@ -102,7 +102,9 @@ int main(int argc, char *argv[]) { } else { cpu->reset(); } - return cpu->start(vm["cycles"].as()); + int64_t cycles = -1; + cycles = vm["cycles"].as(); + return cpu->start(cycles); } catch (std::exception &e) { LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl; diff --git a/sc-components b/sc-components index a5c9101..8272a27 160000 --- a/sc-components +++ b/sc-components @@ -1 +1 @@ -Subproject commit a5c9101b71da3824af4a54322232de270c5547de +Subproject commit 8272a27a0ef24d8b7b596ae8dc5adeb6f422f1b2