From 49d09a05d77adb7602ea1ed7200e649edc7c7f83 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sun, 7 Nov 2021 16:45:10 +0100 Subject: [PATCH] fix access rights to debug CSR register (#268) --- incl/iss/arch/riscv_hart_m_p.h | 44 ++++++++++++++++++++++++--------- incl/iss/arch/riscv_hart_mu_p.h | 43 +++++++++++++++++++++++--------- 2 files changed, 63 insertions(+), 24 deletions(-) diff --git a/incl/iss/arch/riscv_hart_m_p.h b/incl/iss/arch/riscv_hart_m_p.h index 9133285..1d69f9a 100644 --- a/incl/iss/arch/riscv_hart_m_p.h +++ b/incl/iss/arch/riscv_hart_m_p.h @@ -287,7 +287,6 @@ protected: }; std::vector clic_int_reg; -private: iss::status read_csr_reg(unsigned addr, reg_t &val); iss::status write_csr_reg(unsigned addr, reg_t val); iss::status read_null(unsigned addr, reg_t &val); @@ -307,18 +306,23 @@ private: iss::status write_ip(unsigned addr, reg_t val); iss::status read_hartid(unsigned addr, reg_t &val); iss::status write_epc(unsigned addr, reg_t val); - iss::status write_dcsr(unsigned addr, reg_t val); + iss::status write_intstatus(unsigned addr, reg_t val); + iss::status write_intthresh(unsigned addr, reg_t val); + iss::status write_dcsr_dcsr(unsigned addr, reg_t val); + iss::status read_dcsr_reg(unsigned addr, reg_t &val); + iss::status write_dcsr_reg(unsigned addr, reg_t val); + reg_t mhartid_reg{0x0}; std::functionmem_read_cb; std::function mem_write_cb; -protected: void check_interrupt(); bool pmp_check(const access_type type, const uint64_t addr, const unsigned len); uint64_t clic_base_addr{0}; unsigned clic_num_irq{0}; unsigned clic_num_trigger{0}; unsigned mcause_max_irq{16}; + bool debug_mode_active{false}; }; template @@ -389,14 +393,14 @@ riscv_hart_m_p::riscv_hart_m_p() csr_wr_cb[marchid] = &this_class::write_null; csr_wr_cb[mimpid] = &this_class::write_null; if(FEAT & FEAT_DEBUG){ - csr_wr_cb[dscratch0] = &this_class::write_csr_reg; - csr_rd_cb[dscratch0] = &this_class::read_csr_reg; - csr_wr_cb[dscratch1] = &this_class::write_csr_reg; - csr_rd_cb[dscratch1] = &this_class::read_csr_reg; - csr_wr_cb[dpc] = &this_class::write_csr_reg; - csr_rd_cb[dpc] = &this_class::read_csr_reg; - csr_wr_cb[dcsr] = &this_class::write_dcsr; - csr_rd_cb[dcsr] = &this_class::read_csr_reg; + csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg; + csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg; + csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg; + csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg; + csr_wr_cb[dpc] = &this_class::write_dcsr_reg; + csr_rd_cb[dpc] = &this_class::read_dcsr_reg; + csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr; + csr_rd_cb[dcsr] = &this_class::read_dcsr_reg; } } @@ -810,7 +814,9 @@ template iss::status riscv_hart_m_p return iss::Ok; } -template iss::status riscv_hart_m_p::write_dcsr(unsigned addr, reg_t val) { +template iss::status riscv_hart_m_p::write_dcsr_dcsr(unsigned addr, reg_t val) { + if(!debug_mode_active) + throw illegal_instruction_fault(this->fault_data); // +-------------- ebreakm // | +---------- stepi // | | +++----- cause @@ -819,6 +825,20 @@ template iss::status riscv_hart_m_p return iss::Ok; } +template iss::status riscv_hart_m_p::read_dcsr_reg(unsigned addr, reg_t &val) { + if(!debug_mode_active) + throw illegal_instruction_fault(this->fault_data); + val = csr[addr]; + return iss::Ok; +} + +template iss::status riscv_hart_m_p::write_dcsr_reg(unsigned addr, reg_t val) { + if(!debug_mode_active) + throw illegal_instruction_fault(this->fault_data); + csr[addr] = val; + return iss::Ok; +} + template iss::status riscv_hart_m_p::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) { if(mem_read_cb) return mem_read_cb(paddr, length, data); diff --git a/incl/iss/arch/riscv_hart_mu_p.h b/incl/iss/arch/riscv_hart_mu_p.h index 751f87e..6d0537c 100644 --- a/incl/iss/arch/riscv_hart_mu_p.h +++ b/incl/iss/arch/riscv_hart_mu_p.h @@ -302,7 +302,6 @@ protected: }; std::vector clic_int_reg; -private: iss::status read_csr_reg(unsigned addr, reg_t &val); iss::status write_csr_reg(unsigned addr, reg_t val); iss::status read_null(unsigned addr, reg_t &val); @@ -324,21 +323,23 @@ private: iss::status write_edeleg(unsigned addr, reg_t val); iss::status read_hartid(unsigned addr, reg_t &val); iss::status write_epc(unsigned addr, reg_t val); - iss::status write_dcsr(unsigned addr, reg_t val); iss::status write_intstatus(unsigned addr, reg_t val); iss::status write_intthresh(unsigned addr, reg_t val); + iss::status write_dcsr_dcsr(unsigned addr, reg_t val); + iss::status read_dcsr_reg(unsigned addr, reg_t &val); + iss::status write_dcsr_reg(unsigned addr, reg_t val); reg_t mhartid_reg{0x0}; std::functionmem_read_cb; std::function mem_write_cb; -protected: void check_interrupt(); bool pmp_check(const access_type type, const uint64_t addr, const unsigned len); uint64_t clic_base_addr{0}; unsigned clic_num_irq{0}; unsigned clic_num_trigger{0}; unsigned mcause_max_irq{16}; + bool debug_mode_active{false}; }; template @@ -464,14 +465,14 @@ riscv_hart_mu_p::riscv_hart_mu_p() mcause_max_irq=clic_num_irq+16; } if(FEAT & FEAT_DEBUG){ - csr_wr_cb[dscratch0] = &this_class::write_csr_reg; - csr_rd_cb[dscratch0] = &this_class::read_csr_reg; - csr_wr_cb[dscratch1] = &this_class::write_csr_reg; - csr_rd_cb[dscratch1] = &this_class::read_csr_reg; - csr_wr_cb[dpc] = &this_class::write_csr_reg; - csr_rd_cb[dpc] = &this_class::read_csr_reg; - csr_wr_cb[dcsr] = &this_class::write_dcsr; - csr_rd_cb[dcsr] = &this_class::read_csr_reg; + csr_wr_cb[dscratch0] = &this_class::write_dcsr_reg; + csr_rd_cb[dscratch0] = &this_class::read_dcsr_reg; + csr_wr_cb[dscratch1] = &this_class::write_dcsr_reg; + csr_rd_cb[dscratch1] = &this_class::read_dcsr_reg; + csr_wr_cb[dpc] = &this_class::write_dcsr_reg; + csr_rd_cb[dpc] = &this_class::read_dcsr_reg; + csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr; + csr_rd_cb[dcsr] = &this_class::read_dcsr_reg; } } @@ -977,7 +978,9 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_mu_p::write_dcsr(unsigned addr, reg_t val) { +template iss::status riscv_hart_mu_p::write_dcsr_dcsr(unsigned addr, reg_t val) { + if(!debug_mode_active) + throw illegal_instruction_fault(this->fault_data); // +-------------- ebreakm // | +---------- stepi // | | +++----- cause @@ -985,6 +988,22 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_mu_p::read_dcsr_reg(unsigned addr, reg_t &val) { + if(!debug_mode_active) + throw illegal_instruction_fault(this->fault_data); + val = csr[addr]; + return iss::Ok; +} + +template iss::status riscv_hart_mu_p::write_dcsr_reg(unsigned addr, reg_t val) { + if(!debug_mode_active) + throw illegal_instruction_fault(this->fault_data); + csr[addr] = val; + return iss::Ok; +} + + template iss::status riscv_hart_mu_p::write_intthresh(unsigned addr, reg_t val) { csr[addr]= val &0xff;