From 40f50b0ec079b912ed7ab76756772bd0527ebe05 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sat, 9 Sep 2023 18:54:18 +0200 Subject: [PATCH] changes register names to lower case in printing --- CMakeLists.txt | 4 ++- gen_input/templates/CORENAME.h.gtl | 4 +-- src/iss/arch/tgc5c.h | 4 +-- src/vm/interp/vm_tgc5c.cpp | 52 +++++++++++++++--------------- 4 files changed, 33 insertions(+), 31 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 001a346..aa62c97 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -80,7 +80,9 @@ target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core) get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES) target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL}) get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS) -target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS}) +if(NOT (DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND)) + target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS}) +endif() target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine) if(TARGET jsoncpp::jsoncpp) diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl index 96ba762..7d3a38c 100644 --- a/gen_input/templates/CORENAME.h.gtl +++ b/gen_input/templates/CORENAME.h.gtl @@ -76,10 +76,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> { constexpr static char const* const core_type = "${coreDef.name}"; static constexpr std::array reg_names{ - {"${registers.collect{it.name}.join('", "')}"}}; + {"${registers.collect{it.name.toLowerCase()}.join('", "')}"}}; static constexpr std::array reg_aliases{ - {"${registers.collect{it.alias}.join('", "')}"}}; + {"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}}; enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}}; diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index 319f31f..76e6200 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -48,10 +48,10 @@ template <> struct traits { constexpr static char const* const core_type = "TGC5C"; static constexpr std::array reg_names{ - {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}}; + {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}}; static constexpr std::array reg_aliases{ - {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}}; + {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}}; enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL}; diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index 4ba2443..639cb6d 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -719,9 +719,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - int8_t read_res = super::template read_mem(traits::MEM, load_address); + int8_t res_27 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int8_t res = (int8_t)read_res; + int8_t res = (int8_t)res_27; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -750,9 +750,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - int16_t read_res = super::template read_mem(traits::MEM, load_address); + int16_t res_28 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int16_t res = (int16_t)read_res; + int16_t res = (int16_t)res_28; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -781,9 +781,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - int32_t read_res = super::template read_mem(traits::MEM, load_address); + int32_t res_29 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int32_t res = (int32_t)read_res; + int32_t res = (int32_t)res_29; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -812,9 +812,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - uint8_t read_res = super::template read_mem(traits::MEM, load_address); + uint8_t res_30 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint8_t res = read_res; + uint8_t res = res_30; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -843,9 +843,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - uint16_t read_res = super::template read_mem(traits::MEM, load_address); + uint16_t res_31 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint16_t res = read_res; + uint16_t res = res_31; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -1543,9 +1543,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint32_t xrs1 = *(X+rs1); if(rd != 0) { - uint32_t read_res = super::template read_mem(traits::CSR, csr); + uint32_t res_32 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = read_res; + uint32_t xrd = res_32; super::template write_mem(traits::CSR, csr, xrs1); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); *(X+rd) = xrd; @@ -1578,9 +1578,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t read_res = super::template read_mem(traits::CSR, csr); + uint32_t res_33 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = read_res; + uint32_t xrd = res_33; uint32_t xrs1 = *(X+rs1); if(rs1 != 0) { super::template write_mem(traits::CSR, csr, xrd | xrs1); @@ -1613,9 +1613,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t read_res = super::template read_mem(traits::CSR, csr); + uint32_t res_34 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = read_res; + uint32_t xrd = res_34; uint32_t xrs1 = *(X+rs1); if(rs1 != 0) { super::template write_mem(traits::CSR, csr, xrd & ~ xrs1); @@ -1648,9 +1648,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t read_res = super::template read_mem(traits::CSR, csr); + uint32_t res_35 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = read_res; + uint32_t xrd = res_35; super::template write_mem(traits::CSR, csr, (uint32_t)zimm); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); if(rd != 0) { @@ -1680,9 +1680,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t read_res = super::template read_mem(traits::CSR, csr); + uint32_t res_36 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = read_res; + uint32_t xrd = res_36; if(zimm != 0) { super::template write_mem(traits::CSR, csr, xrd | (uint32_t)zimm); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); @@ -1714,9 +1714,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t read_res = super::template read_mem(traits::CSR, csr); + uint32_t res_37 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = read_res; + uint32_t xrd = res_37; if(zimm != 0) { super::template write_mem(traits::CSR, csr, xrd & ~ ((uint32_t)zimm)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); @@ -2051,9 +2051,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint32_t offs = (uint32_t)(*(X+rs1 + 8) + uimm); - int32_t read_res = super::template read_mem(traits::MEM, offs); + int32_t res_38 = super::template read_mem(traits::MEM, offs); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - *(X+rd + 8) = (uint32_t)(int32_t)read_res; + *(X+rd + 8) = (uint32_t)(int32_t)res_38; } break; }// @suppress("No break at end of case") @@ -2473,9 +2473,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t offs = (uint32_t)(*(X+2) + uimm); - int32_t read_res = super::template read_mem(traits::MEM, offs); + int32_t res_39 = super::template read_mem(traits::MEM, offs); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - *(X+rd) = (uint32_t)(int32_t)read_res; + *(X+rd) = (uint32_t)(int32_t)res_39; } } break;