From 383d762abcdde3d78b3aef949a54a7aed71d2274 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Thu, 6 Mar 2025 12:10:12 +0100 Subject: [PATCH] applies clang-format and updates SystemC HTIF implementation --- src/iss/arch/riscv_hart_common.h | 2 +- src/iss/arch/riscv_hart_m_p.h | 2 + src/iss/arch/riscv_hart_msu_vp.h | 2 + src/iss/arch/riscv_hart_mu_p.h | 2 + src/sysc/core_complex.cpp | 2 +- src/sysc/sc_core_adapter.h | 88 +++++++++++++++++++------------- src/vm/interp/vm_tgc5c.cpp | 2 +- 7 files changed, 61 insertions(+), 39 deletions(-) diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h index db5db7a..95933c1 100644 --- a/src/iss/arch/riscv_hart_common.h +++ b/src/iss/arch/riscv_hart_common.h @@ -338,7 +338,7 @@ struct riscv_hart_common { const auto fsize = pseg->get_file_size(); // 0x42c/0x0 const auto seg_data = pseg->get_data(); const auto type = pseg->get_type(); - if(type == ELFIO::PT_LOAD && fsize > 0) { + if(type == ELFIO::PT_LOAD && fsize > 0) { auto res = cb(pseg->get_physical_address(), fsize, reinterpret_cast(seg_data)); if(res != iss::Ok) CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 8d13bf5..3fe71b7 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -105,6 +105,8 @@ public: using mem_read_f = iss::status(phys_addr_t addr, unsigned, uint8_t* const); using mem_write_f = iss::status(phys_addr_t addr, unsigned, uint8_t const* const); + constexpr static unsigned MEM = traits::MEM; + // primary template template struct hart_state {}; // specialization 32bit diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index 302f8ce..ca621c2 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -103,6 +103,8 @@ public: using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t&); using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t); + constexpr static unsigned MEM = traits::MEM; + // primary template template struct hart_state {}; // specialization 32bit diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 644750d..e70e27f 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -105,6 +105,8 @@ public: using mem_read_f = iss::status(phys_addr_t addr, unsigned, uint8_t* const); using mem_write_f = iss::status(phys_addr_t addr, unsigned, uint8_t const* const); + constexpr static unsigned MEM = traits::MEM; + // primary template template struct hart_state {}; // specialization 32bit diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp index 274cd99..dfe61ef 100644 --- a/src/sysc/core_complex.cpp +++ b/src/sysc/core_complex.cpp @@ -387,7 +387,7 @@ template void core_complex::run() { quantum_keeper.reset(); cpu->set_interrupt_execution(false); cpu->start(dump_ir); - } while(cpu->get_interrupt_execution()); + } while(!cpu->get_interrupt_execution()); sc_stop(); } diff --git a/src/sysc/sc_core_adapter.h b/src/sysc/sc_core_adapter.h index 3820980..df40c5a 100644 --- a/src/sysc/sc_core_adapter.h +++ b/src/sysc/sc_core_adapter.h @@ -71,44 +71,61 @@ public: iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t* const data) override { if(addr.access && iss::access_type::DEBUG) return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err; - else { - auto tohost_upper = (sizeof(reg_t) == 4 && addr.val == (this->tohost + 4)) || (sizeof(reg_t) == 8 && addr.val == this->tohost); - auto tohost_lower = (sizeof(reg_t) == 4 && addr.val == this->tohost) || (sizeof(reg_t) == 64 && addr.val == this->tohost); - if(tohost_lower || tohost_upper) { - if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) { - switch(hostvar >> 48) { - case 0: - if(hostvar != 0x1) { - SCCINFO(owner->hier_name()) - << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; - } else { - SCCINFO(owner->hier_name()) - << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; - } - this->reg.trap_state = std::numeric_limits::max(); - this->interrupt_sim = hostvar; -#ifndef WITH_TCC - throw(iss::simulation_stopped(hostvar)); -#endif - break; - default: - break; - } - } else if(tohost_lower) - to_host_wr_cnt++; - return iss::Ok; - } else { - auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err; - // clear MTIP on mtimecmp write - if(addr.val == 0x2004000) { - reg_t val; - this->read_csr(iss::arch::mip, val); - if(val & (1ULL << 7)) - this->write_csr(iss::arch::mip, val & ~(1ULL << 7)); + if(addr.val == this->tohost) { + reg_t cur_data = *reinterpret_cast(data); + // Extract Device (bits 63:56) + uint8_t device = sizeof(reg_t) == 4 ? 0 : (cur_data >> 56) & 0xFF; + // Extract Command (bits 55:48) + uint8_t command = sizeof(reg_t) == 4 ? 0 : (cur_data >> 48) & 0xFF; + // Extract payload (bits 47:0) + uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL; // 24bits + if(payload_addr & 1) { + if(payload_addr != 0x1) { + SCCERR(owner->hier_name()) << "tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr + << "), stopping simulation"; + } else { + SCCINFO(owner->hier_name()) + << "tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr << "), stopping simulation"; } - return res; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = payload_addr; +#ifndef WITH_TCC + throw(iss::simulation_stopped(payload_addr)); +#endif + return iss::Ok; } + if(device == 0 && command == 0) { + std::array loaded_payload; + auto res = owner->read_mem(payload_addr, 8 * sizeof(uint64_t), reinterpret_cast(loaded_payload.data()), false) + ? iss::Ok + : iss::Err; + if(res == iss::Err) { + SCCERR(owner->hier_name()) << "Syscall read went wrong"; + return iss::Ok; + } + uint64_t syscall_num = loaded_payload.at(0); + if(syscall_num == 64) // SYS_WRITE + return this->execute_sys_write(this, loaded_payload, PLAT::MEM); + SCCERR(owner->hier_name()) << "tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num + << ") not implemented"; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = payload_addr; + return iss::Ok; + } + SCCERR(owner->hier_name()) << "tohost functionality not implemented for device " << device << " and command " << command; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = payload_addr; + return iss::Ok; } + auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err; + // clear MTIP on mtimecmp write + if(addr.val == 0x2004000) { + reg_t val; + this->read_csr(iss::arch::mip, val); + if(val & (1ULL << 7)) + this->write_csr(iss::arch::mip, val & ~(1ULL << 7)); + } + return res; } iss::status read_csr(unsigned addr, reg_t& val) override { @@ -165,7 +182,6 @@ public: private: sysc::tgfs::core_complex_if* const owner{nullptr}; sc_core::sc_event wfi_evt; - uint64_t hostvar{std::numeric_limits::max()}; unsigned to_host_wr_cnt = 0; bool first{true}; }; diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index 06b3869..3284e85 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -2723,4 +2723,4 @@ volatile std::array dummy = { }; } } -// clang-format on \ No newline at end of file +// clang-format on