From 1cb492b594a78173776a155096893554beba6a16 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Tue, 29 Aug 2017 16:56:11 +0200
Subject: [PATCH] Renamed hart name and core wrapper name

---
 dbt-core                                      |   2 +-
 .../{riscv_core.h => riscv_hart_msu_vp.h}     | 106 +++++++++---------
 .../incl/iss/arch/{minrv_ima.h => rv32imac.h} |  38 +++----
 riscv/src/CMakeLists.txt                      |   4 +-
 riscv/src/internal/vm_riscv.in.cpp            |   6 +-
 .../{vm_minrv_ima.cpp => vm_rv32imac.cpp}     |  22 ++--
 riscv/src/iss/{minrv_ima.cpp => rv32imac.cpp} |  19 ++--
 riscv/src/main.cpp                            |   8 +-
 riscv/src/minres_rv.core_desc                 |   2 +-
 9 files changed, 104 insertions(+), 103 deletions(-)
 rename riscv/incl/iss/arch/{riscv_core.h => riscv_hart_msu_vp.h} (92%)
 rename riscv/incl/iss/arch/{minrv_ima.h => rv32imac.h} (82%)
 rename riscv/src/internal/{vm_minrv_ima.cpp => vm_rv32imac.cpp} (99%)
 rename riscv/src/iss/{minrv_ima.cpp => rv32imac.cpp} (83%)

diff --git a/dbt-core b/dbt-core
index 8cad193..df6f6eb 160000
--- a/dbt-core
+++ b/dbt-core
@@ -1 +1 @@
-Subproject commit 8cad193b272cbaa656baf2499feb5a14e9ad0c00
+Subproject commit df6f6eb713c3c0a2dc10ba29e80d586a9f66a25f
diff --git a/riscv/incl/iss/arch/riscv_core.h b/riscv/incl/iss/arch/riscv_hart_msu_vp.h
similarity index 92%
rename from riscv/incl/iss/arch/riscv_core.h
rename to riscv/incl/iss/arch/riscv_hart_msu_vp.h
index 459a145..e4f9913 100644
--- a/riscv/incl/iss/arch/riscv_core.h
+++ b/riscv/incl/iss/arch/riscv_hart_msu_vp.h
@@ -459,9 +459,9 @@ constexpr uint64_t get_misa(uint64_t mask){
 }
 
 template<typename BASE>
-struct riscv_core: public BASE {
+struct riscv_hart_msu_vp: public BASE {
     using super = BASE;
-    using this_class = riscv_core<BASE>;
+    using this_class = riscv_hart_msu_vp<BASE>;
     using virt_addr_t= typename super::virt_addr_t;
     using phys_addr_t= typename super::phys_addr_t;
     using reg_t =  typename super::reg_t;
@@ -483,8 +483,8 @@ struct riscv_core: public BASE {
         return m[mode];
     }
 
-    riscv_core();
-    virtual ~riscv_core();
+    riscv_hart_msu_vp();
+    virtual ~riscv_hart_msu_vp();
 
     virtual void load_file(std::string name, int type=-1);
 
@@ -493,7 +493,7 @@ struct riscv_core: public BASE {
     virtual iss::status read(const iss::addr_t& addr, unsigned length, uint8_t* const data) override;
     virtual iss::status write(const iss::addr_t& addr, unsigned length, const uint8_t* const data) override;
 
-    virtual uint64_t enter_trap(uint64_t flags) override {return riscv_core::enter_trap(flags, fault_data);}
+    virtual uint64_t enter_trap(uint64_t flags) override {return riscv_hart_msu_vp::enter_trap(flags, fault_data);}
     virtual uint64_t enter_trap(uint64_t flags, uint64_t addr) override;
     virtual uint64_t leave_trap(uint64_t flags) override;
     virtual void wait_until(uint64_t flags) override;
@@ -542,7 +542,7 @@ private:
 };
 
 template<typename BASE>
-riscv_core<BASE>::riscv_core() {
+riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp() {
     csr[misa]=traits<BASE>::XLEN==32?1ULL<<(traits<BASE>::XLEN-2):2ULL<<(traits<BASE>::XLEN-2);
     uart_buf.str("");
     // read-only registers
@@ -552,38 +552,38 @@ riscv_core<BASE>::riscv_core() {
     for(unsigned addr=mcycleh; addr<=hpmcounter31h; ++addr)
         csr_wr_cb[addr]=nullptr;
     // special handling
-    csr_rd_cb[mcycle]=&riscv_core<BASE>::read_cycle;
-    csr_rd_cb[mcycleh]=&riscv_core<BASE>::read_cycle;
-    csr_rd_cb[minstret]=&riscv_core<BASE>::read_cycle;
-    csr_rd_cb[minstreth]=&riscv_core<BASE>::read_cycle;
-    csr_rd_cb[mstatus]=&riscv_core<BASE>::read_status;
-    csr_wr_cb[mstatus]=&riscv_core<BASE>::write_status;
-    csr_rd_cb[sstatus]=&riscv_core<BASE>::read_status;
-    csr_wr_cb[sstatus]=&riscv_core<BASE>::write_status;
-    csr_rd_cb[ustatus]=&riscv_core<BASE>::read_status;
-    csr_wr_cb[ustatus]=&riscv_core<BASE>::write_status;
-    csr_rd_cb[mip]=&riscv_core<BASE>::read_ip;
-    csr_wr_cb[mip]=&riscv_core<BASE>::write_ip;
-    csr_rd_cb[sip]=&riscv_core<BASE>::read_ip;
-    csr_wr_cb[sip]=&riscv_core<BASE>::write_ip;
-    csr_rd_cb[uip]=&riscv_core<BASE>::read_ip;
-    csr_wr_cb[uip]=&riscv_core<BASE>::write_ip;
-    csr_rd_cb[mie]=&riscv_core<BASE>::read_ie;
-    csr_wr_cb[mie]=&riscv_core<BASE>::write_ie;
-    csr_rd_cb[sie]=&riscv_core<BASE>::read_ie;
-    csr_wr_cb[sie]=&riscv_core<BASE>::write_ie;
-    csr_rd_cb[uie]=&riscv_core<BASE>::read_ie;
-    csr_wr_cb[uie]=&riscv_core<BASE>::write_ie;
-    csr_rd_cb[satp]=&riscv_core<BASE>::read_satp;
-    csr_wr_cb[satp]=&riscv_core<BASE>::write_satp;
+    csr_rd_cb[mcycle]=&riscv_hart_msu_vp<BASE>::read_cycle;
+    csr_rd_cb[mcycleh]=&riscv_hart_msu_vp<BASE>::read_cycle;
+    csr_rd_cb[minstret]=&riscv_hart_msu_vp<BASE>::read_cycle;
+    csr_rd_cb[minstreth]=&riscv_hart_msu_vp<BASE>::read_cycle;
+    csr_rd_cb[mstatus]=&riscv_hart_msu_vp<BASE>::read_status;
+    csr_wr_cb[mstatus]=&riscv_hart_msu_vp<BASE>::write_status;
+    csr_rd_cb[sstatus]=&riscv_hart_msu_vp<BASE>::read_status;
+    csr_wr_cb[sstatus]=&riscv_hart_msu_vp<BASE>::write_status;
+    csr_rd_cb[ustatus]=&riscv_hart_msu_vp<BASE>::read_status;
+    csr_wr_cb[ustatus]=&riscv_hart_msu_vp<BASE>::write_status;
+    csr_rd_cb[mip]=&riscv_hart_msu_vp<BASE>::read_ip;
+    csr_wr_cb[mip]=&riscv_hart_msu_vp<BASE>::write_ip;
+    csr_rd_cb[sip]=&riscv_hart_msu_vp<BASE>::read_ip;
+    csr_wr_cb[sip]=&riscv_hart_msu_vp<BASE>::write_ip;
+    csr_rd_cb[uip]=&riscv_hart_msu_vp<BASE>::read_ip;
+    csr_wr_cb[uip]=&riscv_hart_msu_vp<BASE>::write_ip;
+    csr_rd_cb[mie]=&riscv_hart_msu_vp<BASE>::read_ie;
+    csr_wr_cb[mie]=&riscv_hart_msu_vp<BASE>::write_ie;
+    csr_rd_cb[sie]=&riscv_hart_msu_vp<BASE>::read_ie;
+    csr_wr_cb[sie]=&riscv_hart_msu_vp<BASE>::write_ie;
+    csr_rd_cb[uie]=&riscv_hart_msu_vp<BASE>::read_ie;
+    csr_wr_cb[uie]=&riscv_hart_msu_vp<BASE>::write_ie;
+    csr_rd_cb[satp]=&riscv_hart_msu_vp<BASE>::read_satp;
+    csr_wr_cb[satp]=&riscv_hart_msu_vp<BASE>::write_satp;
 }
 
 template<typename BASE>
-riscv_core<BASE>::~riscv_core() {
+riscv_hart_msu_vp<BASE>::~riscv_hart_msu_vp() {
 }
 
 template<typename BASE>
-void riscv_core<BASE>::load_file(std::string name, int type) {
+void riscv_hart_msu_vp<BASE>::load_file(std::string name, int type) {
     FILE* fp = fopen(name.c_str(), "r");
     if(fp){
         char buf[5];
@@ -606,7 +606,7 @@ void riscv_core<BASE>::load_file(std::string name, int type) {
                 const auto fsize=pseg->get_file_size();         // 0x42c/0x0
                 const auto seg_data=pseg->get_data();
                 if(fsize>0){
-                    this->write(typed_addr_t<PHYSICAL>(iss::DEBUG_WRITE, traits<minrv_ima>::MEM, pseg->get_virtual_address()), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
+                    this->write(typed_addr_t<PHYSICAL>(iss::DEBUG_WRITE, traits<BASE>::MEM, pseg->get_virtual_address()), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
                 }
             }
             for (const auto sec :reader.sections ) {
@@ -621,7 +621,7 @@ void riscv_core<BASE>::load_file(std::string name, int type) {
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::read(const iss::addr_t& addr, unsigned length, uint8_t* const data){
+iss::status riscv_hart_msu_vp<BASE>::read(const iss::addr_t& addr, unsigned length, uint8_t* const data){
 #ifndef NDEBUG
     if(addr.type& iss::DEBUG){
         LOG(DEBUG)<<"debug read of "<<length<<" bytes @addr "<<addr;
@@ -717,7 +717,7 @@ iss::status riscv_core<BASE>::read(const iss::addr_t& addr, unsigned length, uin
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::write(const iss::addr_t& addr, unsigned length, const uint8_t* const data){
+iss::status riscv_hart_msu_vp<BASE>::write(const iss::addr_t& addr, unsigned length, const uint8_t* const data){
 #ifndef NDEBUG
     const char* prefix = addr.type & iss::DEBUG?"debug ":"";
     switch(length){
@@ -813,7 +813,7 @@ iss::status riscv_core<BASE>::write(const iss::addr_t& addr, unsigned length, co
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::read_csr(unsigned addr, reg_t& val){
+iss::status riscv_hart_msu_vp<BASE>::read_csr(unsigned addr, reg_t& val){
     if(addr >= csr.size()) return iss::Err;
     auto it = csr_rd_cb.find(addr);
     if(it == csr_rd_cb.end()){
@@ -827,7 +827,7 @@ iss::status riscv_core<BASE>::read_csr(unsigned addr, reg_t& val){
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::write_csr(unsigned addr, reg_t val){
+iss::status riscv_hart_msu_vp<BASE>::write_csr(unsigned addr, reg_t val){
     if(addr>=csr.size()) return iss::Err;
     auto it = csr_wr_cb.find(addr);
     if(it == csr_wr_cb.end()){
@@ -842,7 +842,7 @@ iss::status riscv_core<BASE>::write_csr(unsigned addr, reg_t val){
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::read_cycle(unsigned addr, reg_t& val) {
+iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t& val) {
     if( addr== mcycle) {
         val = static_cast<reg_t>(this->reg.icount);
     }else if(addr==mcycleh) {
@@ -853,7 +853,7 @@ iss::status riscv_core<BASE>::read_cycle(unsigned addr, reg_t& val) {
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::read_status(unsigned addr, reg_t& val) {
+iss::status riscv_hart_msu_vp<BASE>::read_status(unsigned addr, reg_t& val) {
     auto req_priv_lvl=addr>>8;
     if(this->reg.machine_state<req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
     auto mask = get_mask(req_priv_lvl, (reg_t) (std::numeric_limits<reg_t>::max()));
@@ -862,7 +862,7 @@ iss::status riscv_core<BASE>::read_status(unsigned addr, reg_t& val) {
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::write_status(unsigned addr, reg_t val) {
+iss::status riscv_hart_msu_vp<BASE>::write_status(unsigned addr, reg_t val) {
     auto req_priv_lvl=addr>>8;
     if(this->reg.machine_state<req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
     auto mask=get_mask(req_priv_lvl, (reg_t)std::numeric_limits<reg_t>::max());
@@ -874,7 +874,7 @@ iss::status riscv_core<BASE>::write_status(unsigned addr, reg_t val) {
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::read_ie(unsigned addr, reg_t& val) {
+iss::status riscv_hart_msu_vp<BASE>::read_ie(unsigned addr, reg_t& val) {
     auto req_priv_lvl=addr>>8;
     if(this->reg.machine_state<req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
     val = csr[mie];
@@ -884,7 +884,7 @@ iss::status riscv_core<BASE>::read_ie(unsigned addr, reg_t& val) {
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::write_ie(unsigned addr, reg_t val) {
+iss::status riscv_hart_msu_vp<BASE>::write_ie(unsigned addr, reg_t val) {
     auto req_priv_lvl=addr>>8;
     if(this->reg.machine_state<req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
     auto mask=get_irq_mask(req_priv_lvl);
@@ -894,7 +894,7 @@ iss::status riscv_core<BASE>::write_ie(unsigned addr, reg_t val) {
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::read_ip(unsigned addr, reg_t& val) {
+iss::status riscv_hart_msu_vp<BASE>::read_ip(unsigned addr, reg_t& val) {
     auto req_priv_lvl=addr>>8;
     if(this->reg.machine_state<req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
     val = csr[mie];
@@ -904,7 +904,7 @@ iss::status riscv_core<BASE>::read_ip(unsigned addr, reg_t& val) {
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::write_ip(unsigned addr, reg_t val) {
+iss::status riscv_hart_msu_vp<BASE>::write_ip(unsigned addr, reg_t val) {
     auto req_priv_lvl=addr>>8;
     if(this->reg.machine_state<req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
     auto mask=get_irq_mask(req_priv_lvl);
@@ -914,7 +914,7 @@ iss::status riscv_core<BASE>::write_ip(unsigned addr, reg_t val) {
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::read_satp(unsigned addr, reg_t& val){
+iss::status riscv_hart_msu_vp<BASE>::read_satp(unsigned addr, reg_t& val){
     auto status = csr[mstatus];
     auto tvm = status&(1<<20);
     if(this->reg.machine_state==PRIV_S & tvm!=0){
@@ -927,7 +927,7 @@ iss::status riscv_core<BASE>::read_satp(unsigned addr, reg_t& val){
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::write_satp(unsigned addr, reg_t val){
+iss::status riscv_hart_msu_vp<BASE>::write_satp(unsigned addr, reg_t val){
     auto status = csr[mstatus];
     auto tvm = status&(1<<20);
     if(this->reg.machine_state==PRIV_S & tvm!=0){
@@ -940,7 +940,7 @@ iss::status riscv_core<BASE>::write_satp(unsigned addr, reg_t val){
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::read_mem(phys_addr_t addr, unsigned length, uint8_t* const data) {
+iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t addr, unsigned length, uint8_t* const data) {
     const auto& p = mem(addr.val/mem.page_size);
     auto offs=addr.val&mem.page_addr_mask;
     std::copy(p.data() + offs, p.data() + offs+length, data);
@@ -948,7 +948,7 @@ iss::status riscv_core<BASE>::read_mem(phys_addr_t addr, unsigned length, uint8_
 }
 
 template<typename BASE>
-iss::status riscv_core<BASE>::write_mem(phys_addr_t addr, unsigned length, const uint8_t* const data) {
+iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t addr, unsigned length, const uint8_t* const data) {
     mem_type::page_type& p = mem(addr.val/mem.page_size);
     std::copy(data, data+length, p.data()+(addr.val&mem.page_addr_mask));
     // tohost handling in case of riscv-test
@@ -987,7 +987,7 @@ iss::status riscv_core<BASE>::write_mem(phys_addr_t addr, unsigned length, const
 }
 
 template<typename BASE>
-void riscv_core<BASE>::check_interrupt(){
+void riscv_hart_msu_vp<BASE>::check_interrupt(){
     auto status = csr[mstatus];
     auto ip = csr[mip];
     auto ie = csr[mie];
@@ -1015,7 +1015,7 @@ void riscv_core<BASE>::check_interrupt(){
 }
 
 template<typename BASE>
-typename riscv_core<BASE>::phys_addr_t riscv_core<BASE>::v2p(const iss::addr_t& addr){
+typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_hart_msu_vp<BASE>::v2p(const iss::addr_t& addr){
     const uint64_t tmp = reg_t(1) << (traits<BASE>::XLEN-1);
     const uint64_t msk = tmp | (tmp-1);
 
@@ -1123,7 +1123,7 @@ typename riscv_core<BASE>::phys_addr_t riscv_core<BASE>::v2p(const iss::addr_t&
 }
 
 template<typename BASE>
-uint64_t riscv_core<BASE>::enter_trap(uint64_t flags, uint64_t addr) {
+uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t flags, uint64_t addr) {
     auto cur_priv=this->reg.machine_state;
     // calculate and write mcause val
     auto trap_id=flags&0xffff;
@@ -1195,7 +1195,7 @@ uint64_t riscv_core<BASE>::enter_trap(uint64_t flags, uint64_t addr) {
 }
 
 template<typename BASE>
-uint64_t riscv_core<BASE>::leave_trap(uint64_t flags) {
+uint64_t riscv_hart_msu_vp<BASE>::leave_trap(uint64_t flags) {
     auto cur_priv=this->reg.machine_state;
     auto inst_priv=flags&0x3;
     auto status=csr[mstatus];
@@ -1235,7 +1235,7 @@ uint64_t riscv_core<BASE>::leave_trap(uint64_t flags) {
 }
 
 template<typename BASE>
-void riscv_core<BASE>::wait_until(uint64_t flags) {
+void riscv_hart_msu_vp<BASE>::wait_until(uint64_t flags) {
     auto status=csr[mstatus];
     auto tw = status & (1<<21);
     if(this->reg.machine_state==PRIV_S && tw!=0){
diff --git a/riscv/incl/iss/arch/minrv_ima.h b/riscv/incl/iss/arch/rv32imac.h
similarity index 82%
rename from riscv/incl/iss/arch/minrv_ima.h
rename to riscv/incl/iss/arch/rv32imac.h
index 795a26f..b2c9644 100644
--- a/riscv/incl/iss/arch/minrv_ima.h
+++ b/riscv/incl/iss/arch/rv32imac.h
@@ -28,13 +28,13 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 // 
-// Created on: Sun Aug 27 17:03:32 CEST 2017
-//             *      minrv_ima.h Author: <CoreDSL Generator>
+// Created on: Tue Aug 29 16:45:20 CEST 2017
+//             *      rv32imac.h Author: <CoreDSL Generator>
 //
 ////////////////////////////////////////////////////////////////////////////////
 
-#ifndef _MINRV_IMA_H_
-#define _MINRV_IMA_H_
+#ifndef _RV32IMAC_H_
+#define _RV32IMAC_H_
 
 #include <iss/arch_if.h>
 #include <iss/vm_if.h>
@@ -43,10 +43,10 @@
 namespace iss {
 namespace arch {
 
-struct minrv_ima;
+struct rv32imac;
 
 template<>
-struct traits<minrv_ima> {
+struct traits<rv32imac> {
 
     enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095};
 
@@ -103,13 +103,13 @@ struct traits<minrv_ima> {
     typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
 
     constexpr static unsigned reg_bit_width(unsigned r) {
-        const uint32_t MinRV_IMA_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64};
-        return MinRV_IMA_reg_size[r];
+        const uint32_t RV32IMAC_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64};
+        return RV32IMAC_reg_size[r];
     }
 
     constexpr static unsigned reg_byte_offset(unsigned r) {
-        const uint32_t MinRV_IMA_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160};
-        return MinRV_IMA_reg_byte_offset[r];
+        const uint32_t RV32IMAC_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160};
+        return RV32IMAC_reg_byte_offset[r];
     }
 
     enum sreg_flag_e {FLAGS};
@@ -118,15 +118,15 @@ struct traits<minrv_ima> {
 
 };
 
-struct minrv_ima: public arch_if {
+struct rv32imac: public arch_if {
 
-    using virt_addr_t = typename traits<minrv_ima>::virt_addr_t;
-    using phys_addr_t = typename traits<minrv_ima>::phys_addr_t;
-    using reg_t =  typename traits<minrv_ima>::reg_t;
-    using addr_t = typename traits<minrv_ima>::addr_t;
+    using virt_addr_t = typename traits<rv32imac>::virt_addr_t;
+    using phys_addr_t = typename traits<rv32imac>::phys_addr_t;
+    using reg_t =  typename traits<rv32imac>::reg_t;
+    using addr_t = typename traits<rv32imac>::addr_t;
 
-    minrv_ima();
-    ~minrv_ima();
+    rv32imac();
+    ~rv32imac();
 
     virtual void reset(uint64_t address=0) override;
 
@@ -154,7 +154,7 @@ struct minrv_ima: public arch_if {
     virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
 
 protected:
-    struct MinRV_IMA_regs {
+    struct RV32IMAC_regs {
         uint32_t X0;
         uint32_t X1;
         uint32_t X2;
@@ -196,4 +196,4 @@ protected:
 
 }
 }            
-#endif /* _MINRV_IMA_H_ */
+#endif /* _RV32IMAC_H_ */
diff --git a/riscv/src/CMakeLists.txt b/riscv/src/CMakeLists.txt
index 3e28610..a3e5dff 100644
--- a/riscv/src/CMakeLists.txt
+++ b/riscv/src/CMakeLists.txt
@@ -2,8 +2,8 @@
 FILE(GLOB RiscVHeaders *.h)
 set(LIB_HEADERS ${RiscVHeaders} )
 set(LIB_SOURCES
-    iss/minrv_ima.cpp
-    internal/vm_minrv_ima.cpp
+    iss/rv32imac.cpp
+    internal/vm_rv32imac.cpp
 )
 
 set(APP_HEADERS )
diff --git a/riscv/src/internal/vm_riscv.in.cpp b/riscv/src/internal/vm_riscv.in.cpp
index 11ec426..cdebaea 100644
--- a/riscv/src/internal/vm_riscv.in.cpp
+++ b/riscv/src/internal/vm_riscv.in.cpp
@@ -42,10 +42,10 @@
 
 #include "iss/vm_base.h"
 #include "iss/arch/CORE_DEF_NAME.h"
-#include "iss/arch/riscv_core.h"
 #include "iss/debugger/server.h"
 
 #include <boost/format.hpp>
+#include "../../incl/iss/arch/riscv_hart_msu_vp.h"
 
 namespace iss {
 namespace CORE_DEF_NAME {
@@ -452,13 +452,13 @@ template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, unsigned short port,
     return ret;\
 }\
 template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, unsigned short port, bool dump) {\
-    return create<ARCH>(new arch::riscv_core<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\
+    return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\
 }\
 template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, bool dump) {\
     return std::make_unique<CORE_DEF_NAME::vm_impl<ARCH> >(*core, dump); /* FIXME: memory leak!!!!!!! */ \
 }\
 template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, bool dump) { \
-    return create<ARCH>(new arch::riscv_core<ARCH>(), dump);\
+    return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), dump);\
 }
 
 CREATE_FUNCS(arch::CORE_DEF_NAME)
diff --git a/riscv/src/internal/vm_minrv_ima.cpp b/riscv/src/internal/vm_rv32imac.cpp
similarity index 99%
rename from riscv/src/internal/vm_minrv_ima.cpp
rename to riscv/src/internal/vm_rv32imac.cpp
index 46c97f5..35194c2 100644
--- a/riscv/src/internal/vm_minrv_ima.cpp
+++ b/riscv/src/internal/vm_rv32imac.cpp
@@ -41,14 +41,14 @@
 #include <cstring>
 
 #include "iss/vm_base.h"
-#include "iss/arch/minrv_ima.h"
-#include "iss/arch/riscv_core.h"
+#include "iss/arch/rv32imac.h"
 #include "iss/debugger/server.h"
 
 #include <boost/format.hpp>
+#include "../../incl/iss/arch/riscv_hart_msu_vp.h"
 
 namespace iss {
-namespace minrv_ima {
+namespace rv32imac {
 using namespace iss::arch;
 using namespace llvm;
 using namespace iss::debugger;
@@ -5521,27 +5521,27 @@ void vm_impl<ARCH>::gen_trap_check(llvm::BasicBlock* bb){
                     this->trap_blk, 1);
 }
 
-} // namespace minrv_ima
+} // namespace rv32imac
 
 #define CREATE_FUNCS(ARCH) \
 template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, unsigned short port, bool dump) {\
-    std::unique_ptr<minrv_ima::vm_impl<ARCH> > ret = std::make_unique<minrv_ima::vm_impl<ARCH> >(*core, dump);\
+    std::unique_ptr<rv32imac::vm_impl<ARCH> > ret = std::make_unique<rv32imac::vm_impl<ARCH> >(*core, dump);\
     debugger::server<debugger::gdb_session>::run_server(ret.get(), port);\
     return ret;\
 }\
 template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, unsigned short port, bool dump) {\
-    return create<ARCH>(new arch::riscv_core<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\
+    return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\
 }\
 template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, bool dump) {\
-    return std::make_unique<minrv_ima::vm_impl<ARCH> >(*core, dump); /* FIXME: memory leak!!!!!!! */ \
+    return std::make_unique<rv32imac::vm_impl<ARCH> >(*core, dump); /* FIXME: memory leak!!!!!!! */ \
 }\
 template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, bool dump) { \
-    return create<ARCH>(new arch::riscv_core<ARCH>(), dump);\
+    return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), dump);\
 }
 
-CREATE_FUNCS(arch::minrv_ima)
+CREATE_FUNCS(arch::rv32imac)
 
-namespace minrv_ima {
+namespace rv32imac {
 
     template<typename ARCH>
     status target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
@@ -5758,5 +5758,5 @@ namespace minrv_ima {
         vm->get_arch()->set_reg(reg_no, data);
         return resume_from_current(step, sig);
     }
-} // namespace minrv_ima
+} // namespace rv32imac
 } // namespace iss
diff --git a/riscv/src/iss/minrv_ima.cpp b/riscv/src/iss/rv32imac.cpp
similarity index 83%
rename from riscv/src/iss/minrv_ima.cpp
rename to riscv/src/iss/rv32imac.cpp
index c5917c3..57edacf 100644
--- a/riscv/src/iss/minrv_ima.cpp
+++ b/riscv/src/iss/rv32imac.cpp
@@ -28,15 +28,16 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 // 
-// Contributors:
-//       eyck@minres.com - initial API and implementation
+// Created on: Tue Aug 29 16:45:20 CEST 2017
+//             *      rv32imac.cpp Author: <CoreDSL Generator>
+//
 ////////////////////////////////////////////////////////////////////////////////
 
 #include "util/ities.h"
 #include <easylogging++.h>
 
 #include <elfio/elfio.hpp>
-#include <iss/arch/minrv_ima.h>
+#include <iss/arch/rv32imac.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -51,25 +52,25 @@ extern "C" {
 
 using namespace iss::arch;
 
-minrv_ima::minrv_ima() {
+rv32imac::rv32imac() {
     reg.icount=0;
 }
 
-minrv_ima::~minrv_ima(){
+rv32imac::~rv32imac(){
 }
 
-void minrv_ima::reset(uint64_t address) {
-    for(size_t i=0; i<traits<minrv_ima>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<minrv_ima>::reg_t),0));
+void rv32imac::reset(uint64_t address) {
+    for(size_t i=0; i<traits<rv32imac>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t),0));
     reg.PC=address;
     reg.NEXT_PC=reg.PC;
     reg.trap_state=0;
     reg.machine_state=0x3;
 }
 
-uint8_t* minrv_ima::get_regs_base_ptr(){
+uint8_t* rv32imac::get_regs_base_ptr(){
     return reinterpret_cast<uint8_t*>(&reg);
 }
 
-minrv_ima::phys_addr_t minrv_ima::v2p(const iss::addr_t& pc) {
+rv32imac::phys_addr_t rv32imac::v2p(const iss::addr_t& pc) {
     return phys_addr_t(pc); //change logical address to physical address
 }
diff --git a/riscv/src/main.cpp b/riscv/src/main.cpp
index e8147ff..75a5910 100644
--- a/riscv/src/main.cpp
+++ b/riscv/src/main.cpp
@@ -37,7 +37,7 @@
 #include <iss/iss.h>
 #include <iostream>
 
-#include <iss/arch/minrv_ima.h>
+#include <iss/arch/rv32imac.h>
 #ifndef WITHOUT_LLVM
 #include <iss/jit/MCJIThelper.h>
 #endif
@@ -72,13 +72,13 @@ int main(int argc, char *argv[]) {
             bool  dump=vm.count("dump-ir");
             // instantiate the simulator
             std::unique_ptr<iss::vm_if> cpu = vm.count("gdb-port")?
-                    iss::create<iss::arch::minrv_ima>("rv32ima", vm["gdb-port"].as<unsigned>(), dump):
-                    iss::create<iss::arch::minrv_ima>("rv32ima", dump);
+                    iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump):
+                    iss::create<iss::arch::rv32imac>("rv32ima", dump);
             if(vm.count("elf")){
                 for(std::string input: vm["elf"].as<std::vector<std::string> >())
                     cpu->get_arch()->load_file(input);
             } else if(vm.count("mem")){
-                cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::minrv_ima>::MEM);
+                cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::rv32imac>::MEM);
             } //else
               //  LOG(FATAL)<<"At least one (flash-)input file (ELF or IHEX) needs to be specified";
 
diff --git a/riscv/src/minres_rv.core_desc b/riscv/src/minres_rv.core_desc
index b2af3aa..126bddf 100644
--- a/riscv/src/minres_rv.core_desc
+++ b/riscv/src/minres_rv.core_desc
@@ -6,7 +6,7 @@ import "RV32C.core_desc"
 //import "RV64M.core_desc"
 //import "RV64A.core_desc"
 
-Core MinRV_IMA provides RV32IBase,RV32M,RV32A, RV32CI  {
+Core RV32IMAC provides RV32IBase,RV32M,RV32A, RV32CI  {
     template:"vm_riscv.in.cpp";
     constants {
         XLEN:=32;