diff --git a/gen_input/templates/tcc/CORENAME.cpp.gtl b/gen_input/templates/tcc/CORENAME.cpp.gtl
index c215a03..ec327a1 100644
--- a/gen_input/templates/tcc/CORENAME.cpp.gtl
+++ b/gen_input/templates/tcc/CORENAME.cpp.gtl
@@ -38,7 +38,9 @@
 #include <util/logging.h>
 #include <sstream>
 #include <iss/instruction_decoder.h>
-
+<%def fcsr = registers.find {it.name=='FCSR'}
+if(fcsr != null) {%>
+#include <vm/fp_functions.h><%}%>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif
@@ -86,7 +88,6 @@ protected:
 
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 <%
-def fcsr = registers.find {it.name=='FCSR'}
 if(fcsr != null) {%>
     inline const char *fname(size_t index){return index < 32?name(index+traits::F0):"illegal";}   
 
@@ -284,6 +285,7 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
 if(fcsr != null) {%>
 template <typename ARCH> void vm_impl<ARCH>::add_prologue(tu_builder& tu){
     std::ostringstream os;
+    os << "uint32_t (*fget_flags)()=" << (uintptr_t)&fget_flags << ";\\n";
     os << "uint32_t (*fadd_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fadd_s << ";\\n";
     os << "uint32_t (*fsub_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fsub_s << ";\\n";
     os << "uint32_t (*fmul_s)(uint32_t v1, uint32_t v2, uint8_t mode)=" << (uintptr_t)&fmul_s << ";\\n";