DBT-RISE-TGC/riscv.sc/incl/sysc/SiFive/platform.h

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/*******************************************************************************
* Copyright 2017 eyck@minres.com
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*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
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*
* http://www.apache.org/licenses/LICENSE-2.0
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*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
/*
* simplesystem.h
*
* Created on: 17.09.2017
* Author: eyck@minres.com
*/
#ifndef SIMPLESYSTEM_H_
#define SIMPLESYSTEM_H_
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#include "aon.h"
#include "clint.h"
#include "gpio.h"
#include "plic.h"
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#include "prci.h"
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#include "spi.h"
#include "uart.h"
#include <array>
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#include <sysc/kernel/sc_module.h>
#include "scc/memory.h"
#include "scc/router.h"
#include "scc/utilities.h"
#include "core_complex.h"
namespace sysc {
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class platform : public sc_core::sc_module {
public:
SC_HAS_PROCESS(platform);
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SiFive::core_complex i_core_complex;
scc::router<> i_router;
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uart i_uart0, i_uart1;
spi i_spi;
gpio i_gpio;
plic i_plic;
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aon i_aon;
prci i_prci;
clint i_clint;
scc::memory<512_MB, 32> i_mem_qspi;
scc::memory<128_kB, 32> i_mem_ram;
sc_core::sc_signal<sc_core::sc_time> s_clk;
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sc_core::sc_signal<bool> s_rst, s_mtime_int, s_msie_int;
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sc_core::sc_vector<sc_core::sc_signal<bool>> s_global_int;
sc_core::sc_signal<bool> s_core_int;
platform(sc_core::sc_module_name nm);
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protected:
void gen_reset();
#include "gen/e300_plat_t.h"
};
} /* namespace sysc */
#endif /* SIMPLESYSTEM_H_ */