riscv_target_adapter.h 20KB

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  1. /*******************************************************************************
  2. * Copyright (C) 2017, 2018 MINRES Technologies GmbH
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright notice,
  9. * this list of conditions and the following disclaimer.
  10. *
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * 3. Neither the name of the copyright holder nor the names of its contributors
  16. * may be used to endorse or promote products derived from this software
  17. * without specific prior written permission.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29. * POSSIBILITY OF SUCH DAMAGE.
  30. *
  31. *******************************************************************************/
  32. #ifndef _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
  33. #define _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_
  34. #include "iss/arch_if.h"
  35. #include <iss/arch/traits.h>
  36. #include <iss/debugger/target_adapter_base.h>
  37. #include <iss/iss.h>
  38. #include <array>
  39. #include <memory>
  40. #define FMT_HEADER_ONLY
  41. #include <fmt/format.h>
  42. #include <util/logging.h>
  43. namespace iss {
  44. namespace debugger {
  45. using namespace iss::arch;
  46. using namespace iss::debugger;
  47. template <typename ARCH> class riscv_target_adapter : public target_adapter_base {
  48. public:
  49. riscv_target_adapter(server_if *srv, iss::arch_if *core)
  50. : target_adapter_base(srv)
  51. , core(core) {}
  52. /*============== Thread Control ===============================*/
  53. /* Set generic thread */
  54. status set_gen_thread(rp_thread_ref &thread) override;
  55. /* Set control thread */
  56. status set_ctrl_thread(rp_thread_ref &thread) override;
  57. /* Get thread status */
  58. status is_thread_alive(rp_thread_ref &thread, bool &alive) override;
  59. /*============= Register Access ================================*/
  60. /* Read all registers. buf is 4-byte aligned and it is in
  61. target byte order. If register is not available
  62. corresponding bytes in avail_buf are 0, otherwise
  63. avail buf is 1 */
  64. status read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) override;
  65. /* Write all registers. buf is 4-byte aligned and it is in target
  66. byte order */
  67. status write_registers(const std::vector<uint8_t> &data) override;
  68. /* Read one register. buf is 4-byte aligned and it is in
  69. target byte order. If register is not available
  70. corresponding bytes in avail_buf are 0, otherwise
  71. avail buf is 1 */
  72. status read_single_register(unsigned int reg_no, std::vector<uint8_t> &buf,
  73. std::vector<uint8_t> &avail_buf) override;
  74. /* Write one register. buf is 4-byte aligned and it is in target byte
  75. order */
  76. status write_single_register(unsigned int reg_no, const std::vector<uint8_t> &buf) override;
  77. /*=================== Memory Access =====================*/
  78. /* Read memory, buf is 4-bytes aligned and it is in target
  79. byte order */
  80. status read_mem(uint64_t addr, std::vector<uint8_t> &buf) override;
  81. /* Write memory, buf is 4-bytes aligned and it is in target
  82. byte order */
  83. status write_mem(uint64_t addr, const std::vector<uint8_t> &buf) override;
  84. status process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) override;
  85. status thread_list_query(int first, const rp_thread_ref &arg, std::vector<rp_thread_ref> &result, size_t max_num,
  86. size_t &num, bool &done) override;
  87. status current_thread_query(rp_thread_ref &thread) override;
  88. status offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) override;
  89. status crc_query(uint64_t addr, size_t len, uint32_t &val) override;
  90. status raw_query(std::string in_buf, std::string &out_buf) override;
  91. status threadinfo_query(int first, std::string &out_buf) override;
  92. status threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) override;
  93. status packetsize_query(std::string &out_buf) override;
  94. status add_break(int type, uint64_t addr, unsigned int length) override;
  95. status remove_break(int type, uint64_t addr, unsigned int length) override;
  96. status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
  97. std::function<void(unsigned)> stop_callback) override;
  98. status target_xml_query(std::string &out_buf) override;
  99. protected:
  100. static inline constexpr addr_t map_addr(const addr_t &i) { return i; }
  101. iss::arch_if *core;
  102. rp_thread_ref thread_idx;
  103. };
  104. template <typename ARCH> status riscv_target_adapter<ARCH>::set_gen_thread(rp_thread_ref &thread) {
  105. thread_idx = thread;
  106. return Ok;
  107. }
  108. template <typename ARCH> status riscv_target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref &thread) {
  109. thread_idx = thread;
  110. return Ok;
  111. }
  112. template <typename ARCH> status riscv_target_adapter<ARCH>::is_thread_alive(rp_thread_ref &thread, bool &alive) {
  113. alive = 1;
  114. return Ok;
  115. }
  116. /* List threads. If first is non-zero then start from the first thread,
  117. * otherwise start from arg, result points to array of threads to be
  118. * filled out, result size is number of elements in the result,
  119. * num points to the actual number of threads found, done is
  120. * set if all threads are processed.
  121. */
  122. template <typename ARCH>
  123. status riscv_target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref &arg,
  124. std::vector<rp_thread_ref> &result, size_t max_num, size_t &num,
  125. bool &done) {
  126. if (first == 0) {
  127. result.clear();
  128. result.push_back(thread_idx);
  129. num = 1;
  130. done = true;
  131. return Ok;
  132. } else
  133. return NotSupported;
  134. }
  135. template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query(rp_thread_ref &thread) {
  136. thread = thread_idx;
  137. return Ok;
  138. }
  139. template <typename ARCH>
  140. status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t> &data, std::vector<uint8_t> &avail) {
  141. LOG(TRACE) << "reading target registers";
  142. // return idx<0?:;
  143. data.clear();
  144. avail.clear();
  145. const uint8_t *reg_base = core->get_regs_base_ptr();
  146. for (size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no) {
  147. auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
  148. unsigned offset = traits<ARCH>::reg_byte_offsets[reg_no];
  149. for (size_t j = 0; j < reg_width; ++j) {
  150. data.push_back(*(reg_base + offset + j));
  151. avail.push_back(0xff);
  152. }
  153. // if(arch::traits<ARCH>::XLEN < 64)
  154. // for(unsigned j=0; j<4; ++j){
  155. // data.push_back(0);
  156. // avail.push_back(0xff);
  157. // }
  158. }
  159. // work around fill with F type registers
  160. if (arch::traits<ARCH>::NUM_REGS < 65) {
  161. auto reg_width = sizeof(typename arch::traits<ARCH>::reg_t);
  162. for (size_t reg_no = 0; reg_no < 33; ++reg_no) {
  163. for (size_t j = 0; j < reg_width; ++j) {
  164. data.push_back(0x0);
  165. avail.push_back(0x00);
  166. }
  167. // if(arch::traits<ARCH>::XLEN < 64)
  168. // for(unsigned j=0; j<4; ++j){
  169. // data.push_back(0x0);
  170. // avail.push_back(0x00);
  171. // }
  172. }
  173. }
  174. return Ok;
  175. }
  176. template <typename ARCH> status riscv_target_adapter<ARCH>::write_registers(const std::vector<uint8_t> &data) {
  177. auto reg_count = arch::traits<ARCH>::NUM_REGS;
  178. auto *reg_base = core->get_regs_base_ptr();
  179. auto iter = data.data();
  180. for (size_t reg_no = 0; reg_no < reg_count; ++reg_no) {
  181. auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
  182. auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
  183. std::copy(iter, iter + reg_width, reg_base);
  184. iter += 4;
  185. reg_base += offset;
  186. }
  187. return Ok;
  188. }
  189. template <typename ARCH>
  190. status riscv_target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t> &data,
  191. std::vector<uint8_t> &avail) {
  192. if (reg_no < 65) {
  193. // auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename
  194. // arch::traits<ARCH>::reg_e>(reg_no))/8;
  195. auto *reg_base = core->get_regs_base_ptr();
  196. auto reg_width = arch::traits<ARCH>::reg_bit_widths[reg_no] / 8;
  197. data.resize(reg_width);
  198. avail.resize(reg_width);
  199. auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
  200. std::copy(reg_base + offset, reg_base + offset + reg_width, data.begin());
  201. std::fill(avail.begin(), avail.end(), 0xff);
  202. } else {
  203. typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_READ, traits<ARCH>::CSR, reg_no - 65);
  204. data.resize(sizeof(typename traits<ARCH>::reg_t));
  205. avail.resize(sizeof(typename traits<ARCH>::reg_t));
  206. std::fill(avail.begin(), avail.end(), 0xff);
  207. core->read(a, data.size(), data.data());
  208. }
  209. return data.size() > 0 ? Ok : Err;
  210. }
  211. template <typename ARCH>
  212. status riscv_target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t> &data) {
  213. if (reg_no < 65) {
  214. auto *reg_base = core->get_regs_base_ptr();
  215. auto reg_width = arch::traits<ARCH>::reg_bit_widths[static_cast<typename arch::traits<ARCH>::reg_e>(reg_no)] / 8;
  216. auto offset = traits<ARCH>::reg_byte_offsets[reg_no];
  217. std::copy(data.begin(), data.begin() + reg_width, reg_base + offset);
  218. } else {
  219. typed_addr_t<iss::address_type::PHYSICAL> a(iss::access_type::DEBUG_WRITE, traits<ARCH>::CSR, reg_no - 65);
  220. core->write(a, data.size(), data.data());
  221. }
  222. return Ok;
  223. }
  224. template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t> &data) {
  225. auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
  226. auto f = [&]() -> status { return core->read(a, data.size(), data.data()); };
  227. return srv->execute_syncronized(f);
  228. }
  229. template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t> &data) {
  230. auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
  231. auto f = [&]() -> status { return core->write(a, data.size(), data.data()); };
  232. return srv->execute_syncronized(f);
  233. }
  234. template <typename ARCH>
  235. status riscv_target_adapter<ARCH>::process_query(unsigned int &mask, const rp_thread_ref &arg, rp_thread_info &info) {
  236. return NotSupported;
  237. }
  238. template <typename ARCH>
  239. status riscv_target_adapter<ARCH>::offsets_query(uint64_t &text, uint64_t &data, uint64_t &bss) {
  240. text = 0;
  241. data = 0;
  242. bss = 0;
  243. return Ok;
  244. }
  245. template <typename ARCH> status riscv_target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t &val) {
  246. return NotSupported;
  247. }
  248. template <typename ARCH> status riscv_target_adapter<ARCH>::raw_query(std::string in_buf, std::string &out_buf) {
  249. return NotSupported;
  250. }
  251. template <typename ARCH> status riscv_target_adapter<ARCH>::threadinfo_query(int first, std::string &out_buf) {
  252. if (first) {
  253. out_buf = fmt::format("m{:x}", thread_idx.val);
  254. } else {
  255. out_buf = "l";
  256. }
  257. return Ok;
  258. }
  259. template <typename ARCH>
  260. status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) {
  261. std::array<char, 20> buf;
  262. memset(buf.data(), 0, 20);
  263. sprintf(buf.data(), "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
  264. out_buf = buf.data();
  265. return Ok;
  266. }
  267. template <typename ARCH> status riscv_target_adapter<ARCH>::packetsize_query(std::string &out_buf) {
  268. out_buf = "PacketSize=1000";
  269. return Ok;
  270. }
  271. template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
  272. auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
  273. auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
  274. target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
  275. LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex
  276. << saddr.val << std::dec;
  277. LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
  278. return Ok;
  279. }
  280. template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
  281. auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
  282. unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
  283. if (handle) {
  284. LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
  285. << std::dec;
  286. // TODO: check length of addr range
  287. target_adapter_base::bp_lut.removeEntry(handle);
  288. LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
  289. return Ok;
  290. }
  291. LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
  292. return Err;
  293. }
  294. template <typename ARCH>
  295. status riscv_target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
  296. std::function<void(unsigned)> stop_callback) {
  297. auto *reg_base = core->get_regs_base_ptr();
  298. auto reg_width = arch::traits<ARCH>::reg_bit_widths[arch::traits<ARCH>::PC] / 8;
  299. auto offset = traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC];
  300. const uint8_t *iter = reinterpret_cast<const uint8_t *>(&addr);
  301. std::copy(iter, iter + reg_width, reg_base);
  302. return resume_from_current(step, sig, thread, stop_callback);
  303. }
  304. template <typename ARCH> status riscv_target_adapter<ARCH>::target_xml_query(std::string &out_buf) {
  305. const std::string res{"<?xml version=\"1.0\"?><!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
  306. "<target><architecture>riscv:rv32</architecture>"
  307. //" <feature name=\"org.gnu.gdb.riscv.rv32i\">\n"
  308. //" <reg name=\"x0\" bitsize=\"32\" group=\"general\"/>\n"
  309. //" <reg name=\"x1\" bitsize=\"32\" group=\"general\"/>\n"
  310. //" <reg name=\"x2\" bitsize=\"32\" group=\"general\"/>\n"
  311. //" <reg name=\"x3\" bitsize=\"32\" group=\"general\"/>\n"
  312. //" <reg name=\"x4\" bitsize=\"32\" group=\"general\"/>\n"
  313. //" <reg name=\"x5\" bitsize=\"32\" group=\"general\"/>\n"
  314. //" <reg name=\"x6\" bitsize=\"32\" group=\"general\"/>\n"
  315. //" <reg name=\"x7\" bitsize=\"32\" group=\"general\"/>\n"
  316. //" <reg name=\"x8\" bitsize=\"32\" group=\"general\"/>\n"
  317. //" <reg name=\"x9\" bitsize=\"32\" group=\"general\"/>\n"
  318. //" <reg name=\"x10\" bitsize=\"32\" group=\"general\"/>\n"
  319. //" <reg name=\"x11\" bitsize=\"32\" group=\"general\"/>\n"
  320. //" <reg name=\"x12\" bitsize=\"32\" group=\"general\"/>\n"
  321. //" <reg name=\"x13\" bitsize=\"32\" group=\"general\"/>\n"
  322. //" <reg name=\"x14\" bitsize=\"32\" group=\"general\"/>\n"
  323. //" <reg name=\"x15\" bitsize=\"32\" group=\"general\"/>\n"
  324. //" <reg name=\"x16\" bitsize=\"32\" group=\"general\"/>\n"
  325. //" <reg name=\"x17\" bitsize=\"32\" group=\"general\"/>\n"
  326. //" <reg name=\"x18\" bitsize=\"32\" group=\"general\"/>\n"
  327. //" <reg name=\"x19\" bitsize=\"32\" group=\"general\"/>\n"
  328. //" <reg name=\"x20\" bitsize=\"32\" group=\"general\"/>\n"
  329. //" <reg name=\"x21\" bitsize=\"32\" group=\"general\"/>\n"
  330. //" <reg name=\"x22\" bitsize=\"32\" group=\"general\"/>\n"
  331. //" <reg name=\"x23\" bitsize=\"32\" group=\"general\"/>\n"
  332. //" <reg name=\"x24\" bitsize=\"32\" group=\"general\"/>\n"
  333. //" <reg name=\"x25\" bitsize=\"32\" group=\"general\"/>\n"
  334. //" <reg name=\"x26\" bitsize=\"32\" group=\"general\"/>\n"
  335. //" <reg name=\"x27\" bitsize=\"32\" group=\"general\"/>\n"
  336. //" <reg name=\"x28\" bitsize=\"32\" group=\"general\"/>\n"
  337. //" <reg name=\"x29\" bitsize=\"32\" group=\"general\"/>\n"
  338. //" <reg name=\"x30\" bitsize=\"32\" group=\"general\"/>\n"
  339. //" <reg name=\"x31\" bitsize=\"32\" group=\"general\"/>\n"
  340. //" </feature>\n"
  341. "</target>"};
  342. out_buf = res;
  343. return Ok;
  344. }
  345. /*
  346. *
  347. <?xml version="1.0"?>
  348. <!DOCTYPE target SYSTEM "gdb-target.dtd">
  349. <target>
  350. <architecture>riscv:rv32</architecture>
  351. <feature name="org.gnu.gdb.riscv.rv32i">
  352. <reg name="x0" bitsize="32" group="general"/>
  353. <reg name="x1" bitsize="32" group="general"/>
  354. <reg name="x2" bitsize="32" group="general"/>
  355. <reg name="x3" bitsize="32" group="general"/>
  356. <reg name="x4" bitsize="32" group="general"/>
  357. <reg name="x5" bitsize="32" group="general"/>
  358. <reg name="x6" bitsize="32" group="general"/>
  359. <reg name="x7" bitsize="32" group="general"/>
  360. <reg name="x8" bitsize="32" group="general"/>
  361. <reg name="x9" bitsize="32" group="general"/>
  362. <reg name="x10" bitsize="32" group="general"/>
  363. <reg name="x11" bitsize="32" group="general"/>
  364. <reg name="x12" bitsize="32" group="general"/>
  365. <reg name="x13" bitsize="32" group="general"/>
  366. <reg name="x14" bitsize="32" group="general"/>
  367. <reg name="x15" bitsize="32" group="general"/>
  368. <reg name="x16" bitsize="32" group="general"/>
  369. <reg name="x17" bitsize="32" group="general"/>
  370. <reg name="x18" bitsize="32" group="general"/>
  371. <reg name="x19" bitsize="32" group="general"/>
  372. <reg name="x20" bitsize="32" group="general"/>
  373. <reg name="x21" bitsize="32" group="general"/>
  374. <reg name="x22" bitsize="32" group="general"/>
  375. <reg name="x23" bitsize="32" group="general"/>
  376. <reg name="x24" bitsize="32" group="general"/>
  377. <reg name="x25" bitsize="32" group="general"/>
  378. <reg name="x26" bitsize="32" group="general"/>
  379. <reg name="x27" bitsize="32" group="general"/>
  380. <reg name="x28" bitsize="32" group="general"/>
  381. <reg name="x29" bitsize="32" group="general"/>
  382. <reg name="x30" bitsize="32" group="general"/>
  383. <reg name="x31" bitsize="32" group="general"/>
  384. </feature>
  385. </target>
  386. */
  387. }
  388. }
  389. #endif /* _ISS_DEBUGGER_RISCV_TARGET_ADAPTER_H_ */