vm-vm_CORENAME.cpp.gtl 14KB

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  1. /*******************************************************************************
  2. * Copyright (C) 2017, 2018 MINRES Technologies GmbH
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright notice,
  9. * this list of conditions and the following disclaimer.
  10. *
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * 3. Neither the name of the copyright holder nor the names of its contributors
  16. * may be used to endorse or promote products derived from this software
  17. * without specific prior written permission.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29. * POSSIBILITY OF SUCH DAMAGE.
  30. *
  31. *******************************************************************************/
  32. #include <iss/arch/${coreDef.name.toLowerCase()}.h>
  33. #include <iss/arch/riscv_hart_msu_vp.h>
  34. #include <iss/debugger/gdb_session.h>
  35. #include <iss/debugger/server.h>
  36. #include <iss/iss.h>
  37. #include <iss/llvm/vm_base.h>
  38. #include <util/logging.h>
  39. #define FMT_HEADER_ONLY
  40. #include <fmt/format.h>
  41. #include <array>
  42. #include <iss/debugger/riscv_target_adapter.h>
  43. namespace iss {
  44. namespace vm {
  45. namespace fp_impl {
  46. void add_fp_functions_2_module(llvm::Module *, unsigned, unsigned);
  47. }
  48. }
  49. namespace ${coreDef.name.toLowerCase()} {
  50. using namespace iss::arch;
  51. using namespace llvm;
  52. using namespace iss::debugger;
  53. using namespace iss::vm::llvm;
  54. template <typename ARCH> class vm_impl : public vm_base<ARCH> {
  55. public:
  56. using super = typename iss::vm::llvm::vm_base<ARCH>;
  57. using virt_addr_t = typename super::virt_addr_t;
  58. using phys_addr_t = typename super::phys_addr_t;
  59. using code_word_t = typename super::code_word_t;
  60. using addr_t = typename super::addr_t;
  61. vm_impl();
  62. vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
  63. void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
  64. target_adapter_if *accquire_target_adapter(server_if *srv) override {
  65. debugger_if::dbg_enabled = true;
  66. if (vm_base<ARCH>::tgt_adapter == nullptr)
  67. vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
  68. return vm_base<ARCH>::tgt_adapter;
  69. }
  70. protected:
  71. using vm_base<ARCH>::get_reg_ptr;
  72. inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
  73. template <typename T> inline ConstantInt *size(T type) {
  74. return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
  75. }
  76. void setup_module(Module* m) override {
  77. super::setup_module(m);
  78. iss::vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
  79. }
  80. inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
  81. return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
  82. }
  83. std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
  84. void gen_leave_behavior(BasicBlock *leave_blk) override;
  85. void gen_raise_trap(uint16_t trap_id, uint16_t cause);
  86. void gen_leave_trap(unsigned lvl);
  87. void gen_wait(unsigned type);
  88. void gen_trap_behavior(BasicBlock *) override;
  89. void gen_trap_check(BasicBlock *bb);
  90. inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
  91. return this->builder.CreateLoad(get_reg_ptr(i), false);
  92. }
  93. inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
  94. Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
  95. this->get_type(traits<ARCH>::XLEN));
  96. this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
  97. }
  98. // some compile time constants
  99. // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
  100. enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
  101. enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
  102. enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
  103. using this_class = vm_impl<ARCH>;
  104. using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
  105. code_word_t instr,
  106. BasicBlock *bb);
  107. std::array<compile_func, LUT_SIZE> lut;
  108. std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
  109. std::array<compile_func, LUT_SIZE> lut_11;
  110. std::array<compile_func *, 4> qlut;
  111. std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
  112. void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
  113. compile_func f) {
  114. if (pos < 0) {
  115. lut[idx] = f;
  116. } else {
  117. auto bitmask = 1UL << pos;
  118. if ((mask & bitmask) == 0) {
  119. expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
  120. } else {
  121. if ((valid & bitmask) == 0) {
  122. expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
  123. expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
  124. } else {
  125. auto new_val = idx << 1;
  126. if ((value & bitmask) != 0) new_val++;
  127. expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
  128. }
  129. }
  130. }
  131. }
  132. inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
  133. uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
  134. if (pos >= 0) {
  135. auto bitmask = 1UL << pos;
  136. if ((mask & bitmask) == 0) {
  137. lut_val = extract_fields(pos - 1, val, mask, lut_val);
  138. } else {
  139. auto new_val = lut_val << 1;
  140. if ((val & bitmask) != 0) new_val++;
  141. lut_val = extract_fields(pos - 1, val, mask, new_val);
  142. }
  143. }
  144. return lut_val;
  145. }
  146. private:
  147. /****************************************************************************
  148. * start opcode definitions
  149. ****************************************************************************/
  150. struct InstructionDesriptor {
  151. size_t length;
  152. uint32_t value;
  153. uint32_t mask;
  154. compile_func op;
  155. };
  156. const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
  157. /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
  158. /* instruction ${instr.instruction.name} */
  159. {${instr.length}, ${instr.value}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
  160. }};
  161. /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
  162. /* instruction ${idx}: ${instr.name} */
  163. std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){<%instr.code.eachLine{%>
  164. ${it}<%}%>
  165. }
  166. <%}%>
  167. /****************************************************************************
  168. * end opcode definitions
  169. ****************************************************************************/
  170. std::tuple<continuation_e, BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
  171. this->gen_sync(iss::PRE_SYNC, instr_descr.size());
  172. this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
  173. get_reg_ptr(traits<ARCH>::PC), true);
  174. this->builder.CreateStore(
  175. this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
  176. this->gen_const(64U, 1)),
  177. get_reg_ptr(traits<ARCH>::ICOUNT), true);
  178. pc = pc + ((instr & 3) == 3 ? 4 : 2);
  179. this->gen_raise_trap(0, 2); // illegal instruction trap
  180. this->gen_sync(iss::POST_SYNC, instr_descr.size());
  181. this->gen_trap_check(this->leave_blk);
  182. return std::make_tuple(BRANCH, nullptr);
  183. }
  184. };
  185. template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
  186. volatile CODE_WORD x = insn;
  187. insn = 2 * x;
  188. }
  189. template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
  190. template <typename ARCH>
  191. vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
  192. : vm_base<ARCH>(core, core_id, cluster_id) {
  193. qlut[0] = lut_00.data();
  194. qlut[1] = lut_01.data();
  195. qlut[2] = lut_10.data();
  196. qlut[3] = lut_11.data();
  197. for (auto instr : instr_descr) {
  198. auto quantrant = instr.value & 0x3;
  199. expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
  200. }
  201. }
  202. template <typename ARCH>
  203. std::tuple<continuation_e, BasicBlock *>
  204. vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
  205. // we fetch at max 4 byte, alignment is 2
  206. enum {TRAP_ID=1<<16};
  207. code_word_t insn = 0;
  208. const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
  209. phys_addr_t paddr(pc);
  210. auto *const data = (uint8_t *)&insn;
  211. paddr = this->core.v2p(pc);
  212. if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
  213. auto res = this->core.read(paddr, 2, data);
  214. if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
  215. if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
  216. res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
  217. }
  218. } else {
  219. auto res = this->core.read(paddr, 4, data);
  220. if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
  221. }
  222. if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
  223. // curr pc on stack
  224. ++inst_cnt;
  225. auto lut_val = extract_fields(insn);
  226. auto f = qlut[insn & 0x3][lut_val];
  227. if (f == nullptr) {
  228. f = &this_class::illegal_intruction;
  229. }
  230. return (this->*f)(pc, insn, this_block);
  231. }
  232. template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
  233. this->builder.SetInsertPoint(leave_blk);
  234. this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
  235. }
  236. template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
  237. auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
  238. this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
  239. this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
  240. }
  241. template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
  242. std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
  243. this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
  244. auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
  245. this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
  246. this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
  247. }
  248. template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
  249. std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
  250. this->builder.CreateCall(this->mod->getFunction("wait"), args);
  251. }
  252. template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
  253. this->builder.SetInsertPoint(trap_blk);
  254. auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
  255. this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
  256. get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
  257. std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
  258. this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
  259. this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
  260. auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
  261. this->builder.CreateRet(trap_addr_val);
  262. }
  263. template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
  264. auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
  265. this->gen_cond_branch(this->builder.CreateICmp(
  266. ICmpInst::ICMP_EQ, v,
  267. ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
  268. bb, this->trap_blk, 1);
  269. }
  270. } // namespace ${coreDef.name.toLowerCase()}
  271. template <>
  272. std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
  273. auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
  274. if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
  275. return std::unique_ptr<vm_if>(ret);
  276. }
  277. } // namespace iss