spi.cpp 10KB

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  1. /*******************************************************************************
  2. * Copyright (C) 2017, 2018 MINRES Technologies GmbH
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright notice,
  9. * this list of conditions and the following disclaimer.
  10. *
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * 3. Neither the name of the copyright holder nor the names of its contributors
  16. * may be used to endorse or promote products derived from this software
  17. * without specific prior written permission.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29. * POSSIBILITY OF SUCH DAMAGE.
  30. *
  31. *******************************************************************************/
  32. #include "sysc/SiFive/spi.h"
  33. #include "cci_configuration"
  34. #include "scc/signal_initiator_mixin.h"
  35. #include "scc/signal_target_mixin.h"
  36. #include "scc/tlm_target.h"
  37. #include "scc/utilities.h"
  38. #include "sysc/SiFive/gen/spi_regs.h"
  39. #include "sysc/tlm_extensions.h"
  40. #include <util/ities.h>
  41. namespace sysc {
  42. namespace spi_impl {
  43. using namespace sc_core;
  44. class beh : public sysc::spi, public scc::tlm_target<> {
  45. public:
  46. SC_HAS_PROCESS(beh); // NOLINT
  47. cci::cci_param<bool> bit_true_transfer;
  48. beh(sc_core::sc_module_name nm);
  49. ~beh() override;
  50. protected:
  51. scc::tlm_signal_bool_opt_out _sck_o;
  52. scc::tlm_signal_bool_opt_out _mosi_o;
  53. scc::tlm_signal_bool_opt_in _miso_i;
  54. sc_core::sc_vector<scc::tlm_signal_bool_opt_out> _scs_o;
  55. void clock_cb();
  56. void reset_cb();
  57. void transmit_data();
  58. void receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay);
  59. void update_irq();
  60. sc_core::sc_event update_irq_evt;
  61. sc_core::sc_time clk;
  62. std::unique_ptr<spi_regs> regs;
  63. sc_core::sc_fifo<uint8_t> rx_fifo, tx_fifo;
  64. };
  65. beh::beh(sc_core::sc_module_name nm)
  66. : sysc::spi(nm)
  67. , tlm_target<>(clk)
  68. , NAMED(_sck_o)
  69. , NAMED(_mosi_o)
  70. , NAMED(_miso_i)
  71. , NAMED(_scs_o, 4)
  72. , NAMED(bit_true_transfer, false)
  73. , NAMEDD(regs, spi_regs)
  74. , rx_fifo(8)
  75. , tx_fifo(8) {
  76. spi::socket(scc::tlm_target<>::socket);
  77. _sck_o(sck_o);
  78. _mosi_o(mosi_o);
  79. miso_i(_miso_i);
  80. _scs_o(scs_o);
  81. regs->registerResources(*this);
  82. SC_METHOD(clock_cb);
  83. sensitive << clk_i;
  84. SC_METHOD(reset_cb);
  85. sensitive << rst_i;
  86. dont_initialize();
  87. SC_THREAD(transmit_data);
  88. _miso_i.register_nb_transport(
  89. [this](tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
  90. this->receive_data(gp, delay);
  91. return tlm::TLM_COMPLETED;
  92. });
  93. regs->txdata.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
  94. if (!this->regs->in_reset()) {
  95. reg.put(data);
  96. tx_fifo.nb_write(static_cast<uint8_t>(regs->r_txdata.data));
  97. }
  98. return true;
  99. });
  100. regs->rxdata.set_read_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
  101. if (!this->regs->in_reset()) {
  102. uint8_t val;
  103. if (rx_fifo.nb_read(val)) {
  104. regs->r_rxdata.empty = 0;
  105. regs->r_rxdata.data = val;
  106. if (regs->r_rxmark.rxmark <= rx_fifo.num_available()) {
  107. regs->r_ip.rxwm = 1;
  108. update_irq();
  109. }
  110. } else
  111. regs->r_rxdata.empty = 1;
  112. data = reg.get() & reg.rdmask;
  113. }
  114. return true;
  115. });
  116. regs->csmode.set_write_cb(
  117. [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
  118. if (regs->r_csmode.mode == 2 && regs->r_csmode.mode != bit_sub<0, 2>(data) && regs->r_csid < 4) {
  119. tlm::tlm_phase phase(tlm::BEGIN_REQ);
  120. sc_core::sc_time delay(SC_ZERO_TIME);
  121. tlm::tlm_signal_gp<> gp;
  122. gp.set_command(tlm::TLM_WRITE_COMMAND);
  123. gp.set_value(true);
  124. _scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
  125. }
  126. reg.put(data);
  127. return true;
  128. });
  129. regs->csid.set_write_cb([this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
  130. if (regs->r_csmode.mode == 2 && regs->csid != data && regs->r_csid < 4) {
  131. tlm::tlm_phase phase(tlm::BEGIN_REQ);
  132. sc_core::sc_time delay(SC_ZERO_TIME);
  133. tlm::tlm_signal_gp<> gp;
  134. gp.set_command(tlm::TLM_WRITE_COMMAND);
  135. gp.set_value(true);
  136. _scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
  137. }
  138. reg.put(data);
  139. return true;
  140. });
  141. regs->csdef.set_write_cb([this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
  142. auto diff = regs->csdef ^ data;
  143. if (regs->r_csmode.mode == 2 && diff != 0 && (regs->r_csid < 4) && (diff & (1 << regs->r_csid)) != 0) {
  144. tlm::tlm_phase phase(tlm::BEGIN_REQ);
  145. sc_core::sc_time delay(SC_ZERO_TIME);
  146. tlm::tlm_signal_gp<> gp;
  147. gp.set_command(tlm::TLM_WRITE_COMMAND);
  148. gp.set_value(true);
  149. _scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
  150. }
  151. reg.put(data);
  152. return true;
  153. });
  154. regs->ie.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
  155. reg.put(data);
  156. update_irq_evt.notify();
  157. return true;
  158. });
  159. regs->ip.set_write_cb([this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
  160. reg.put(data);
  161. update_irq_evt.notify();
  162. return true;
  163. });
  164. SC_METHOD(update_irq);
  165. sensitive << update_irq_evt << rx_fifo.data_written_event() << rx_fifo.data_read_event()
  166. << tx_fifo.data_written_event() << tx_fifo.data_read_event();
  167. }
  168. beh::~beh() = default;
  169. void beh::clock_cb() { this->clk = clk_i.read(); }
  170. void beh::reset_cb() {
  171. if (rst_i.read())
  172. regs->reset_start();
  173. else
  174. regs->reset_stop();
  175. }
  176. void beh::transmit_data() {
  177. uint8_t txdata;
  178. tlm::tlm_phase phase(tlm::BEGIN_REQ);
  179. sc_core::sc_time delay(SC_ZERO_TIME);
  180. sc_core::sc_time bit_duration(SC_ZERO_TIME);
  181. sc_core::sc_time start_time;
  182. auto set_bit = [&](bool val, scc::tlm_signal_bool_opt_out &socket,
  183. bool data_valid = false) -> std::pair<bool, uint32_t> {
  184. if (socket.get_interface() == nullptr) return std::pair<bool, uint32_t>{false, 0};
  185. auto *gp = tlm::tlm_signal_gp<>::create();
  186. auto *ext = new sysc::tlm_signal_spi_extension();
  187. ext->tx.data_bits = 8;
  188. ext->start_time = start_time;
  189. ext->tx.m2s_data = txdata;
  190. ext->tx.m2s_data_valid = data_valid;
  191. ext->tx.s2m_data_valid = false;
  192. gp->set_extension(ext);
  193. gp->set_command(tlm::TLM_WRITE_COMMAND);
  194. gp->set_value(val);
  195. tlm::tlm_phase phase(tlm::BEGIN_REQ);
  196. gp->acquire();
  197. phase = tlm::BEGIN_REQ;
  198. delay = SC_ZERO_TIME;
  199. socket->nb_transport_fw(*gp, phase, delay);
  200. std::pair<bool, uint32_t> ret{ext->tx.s2m_data_valid != 0, ext->tx.s2m_data};
  201. gp->release();
  202. return ret;
  203. };
  204. wait(delay); // intentionally 0ns;
  205. while (true) {
  206. wait(tx_fifo.data_written_event());
  207. if (regs->r_csmode.mode != 3 && regs->r_csid < 4) // not in OFF mode
  208. set_bit(false, _scs_o[regs->r_csid]);
  209. set_bit(regs->r_sckmode.pol, _sck_o);
  210. while (tx_fifo.nb_read(txdata)) {
  211. regs->r_txdata.full = tx_fifo.num_free() == 0;
  212. regs->r_ip.txwm = regs->r_txmark.txmark <= (7 - tx_fifo.num_free()) ? 1 : 0;
  213. update_irq_evt.notify();
  214. bit_duration = 2 * (regs->r_sckdiv.div + 1) * clk;
  215. start_time = sc_core::sc_time_stamp();
  216. set_bit(txdata & 0x80, _mosi_o); // 8 data bits, MSB first
  217. auto s2m = set_bit(1 - regs->r_sckmode.pol, _sck_o, true);
  218. wait(bit_duration / 2);
  219. set_bit(regs->r_sckmode.pol, _sck_o, true);
  220. wait(bit_duration / 2);
  221. if (bit_true_transfer.get_value()) {
  222. for (size_t i = 0, mask = 0x40; i < 7; ++i, mask >= 1) {
  223. set_bit(txdata & mask, _mosi_o); // 8 data bits, MSB first
  224. set_bit(1 - regs->r_sckmode.pol, _sck_o);
  225. wait(bit_duration / 2);
  226. set_bit(regs->r_sckmode.pol, _sck_o);
  227. wait(bit_duration / 2);
  228. }
  229. } else
  230. wait(7 * bit_duration);
  231. if (s2m.first) rx_fifo.nb_write(s2m.second & 0xff);
  232. update_irq_evt.notify();
  233. }
  234. if (regs->r_csmode.mode == 0 && regs->r_csid < 4) // in AUTO mode
  235. set_bit(false, _scs_o[regs->r_csid]);
  236. }
  237. }
  238. void beh::receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {}
  239. void beh::update_irq() {
  240. regs->r_ip.rxwm = regs->r_rxmark.rxmark < rx_fifo.num_available();
  241. regs->r_ip.txwm = regs->r_txmark.txmark <= tx_fifo.num_available();
  242. regs->r_txdata.full = tx_fifo.num_free() == 0;
  243. irq_o.write((regs->r_ie.rxwm > 0 && regs->r_ip.rxwm > 0) || (regs->r_ie.txwm > 0 && regs->r_ip.txwm > 0));
  244. }
  245. } /* namespace spi:impl */
  246. template <> std::unique_ptr<spi> spi::create<sysc::spi_impl::beh>(sc_core::sc_module_name nm) {
  247. auto *res = new sysc::spi_impl::beh(nm);
  248. return std::unique_ptr<spi>(res);
  249. }
  250. } /* namespace sysc */