Generic RISC-V ISS
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////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial API and implementation
//
//
////////////////////////////////////////////////////////////////////////////////
#include <iss/arch/rv32imac.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
#include <iss/vm_base.h>
#include <util/logging.h>
#include <boost/format.hpp>
#include <iss/debugger/riscv_target_adapter.h>
#include <array>
namespace iss {
namespace vm {
namespace fp_impl{
void add_fp_functions_2_module(llvm::Module *, unsigned);
}
}
namespace rv32imac {
using namespace iss::arch;
using namespace llvm;
using namespace iss::debugger;
template <typename ARCH> class vm_impl : public vm::vm_base<ARCH> {
public:
using super = typename vm::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
using addr_t = typename super::addr_t;
vm_impl();
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
target_adapter_if *accquire_target_adapter(server_if *srv) {
debugger_if::dbg_enabled = true;
if (vm::vm_base<ARCH>::tgt_adapter == nullptr)
vm::vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return vm::vm_base<ARCH>::tgt_adapter;
}
protected:
using vm::vm_base<ARCH>::get_reg_ptr;
template <typename T> inline llvm::ConstantInt *size(T type) {
return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
}
void setup_module(llvm::Module* m) override {
super::setup_module(m);
vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE);
}
inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal, unsigned size) {
return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
}
std::tuple<vm::continuation_e, llvm::BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &,
llvm::BasicBlock *) override;
void gen_leave_behavior(llvm::BasicBlock *leave_blk) override;
void gen_raise_trap(uint16_t trap_id, uint16_t cause);
void gen_leave_trap(unsigned lvl);
void gen_wait(unsigned type);
void gen_trap_behavior(llvm::BasicBlock *) override;
void gen_trap_check(llvm::BasicBlock *bb);
inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) {
return this->builder.CreateLoad(get_reg_ptr(i), false);
}
inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
this->get_type(traits<ARCH>::XLEN));
this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
}
// some compile time constants
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
using this_class = vm_impl<ARCH>;
using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock *> (this_class::*)(virt_addr_t &pc,
code_word_t instr,
llvm::BasicBlock *bb);
std::array<compile_func, LUT_SIZE> lut;
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
std::array<compile_func, LUT_SIZE> lut_11;
std::array<compile_func*, 4> qlut;
std::array<const uint32_t, 4> lutmasks = { { EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32 } };
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
compile_func f) {
if (pos < 0) {
lut[idx] = f;
} else {
auto bitmask = 1UL << pos;
if ((mask & bitmask) == 0) {
expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
} else {
if ((valid & bitmask) == 0) {
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
} else {
auto new_val = idx << 1;
if ((value & bitmask) != 0) new_val++;
expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
}
}
}
}
inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
if (pos >= 0) {
auto bitmask = 1UL << pos;
if ((mask & bitmask) == 0) {
lut_val = extract_fields(pos - 1, val, mask, lut_val);
} else {
auto new_val = lut_val << 1;
if ((val & bitmask) != 0) new_val++;
lut_val = extract_fields(pos - 1, val, mask, new_val);
}
}
return lut_val;
}
private:
/****************************************************************************
* start opcode definitions
****************************************************************************/
struct InstructionDesriptor {
size_t length;
uint32_t value;
uint32_t mask;
compile_func op;
};
const std::array<InstructionDesriptor, 99> instr_descr = {{
/* entries are: size, valid value, valid mask, function ptr */
/* instruction LUI */
{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
/* instruction AUIPC */
{32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc},
/* instruction JAL */
{32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal},
/* instruction JALR */
{32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr},
/* instruction BEQ */
{32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq},
/* instruction BNE */
{32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne},
/* instruction BLT */
{32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt},
/* instruction BGE */
{32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge},
/* instruction BLTU */
{32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu},
/* instruction BGEU */
{32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu},
/* instruction LB */
{32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb},
/* instruction LH */
{32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh},
/* instruction LW */
{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw},
/* instruction LBU */
{32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu},
/* instruction LHU */
{32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu},
/* instruction SB */
{32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb},
/* instruction SH */
{32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh},
/* instruction SW */
{32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw},
/* instruction ADDI */
{32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi},
/* instruction SLTI */
{32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti},
/* instruction SLTIU */
{32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu},
/* instruction XORI */
{32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori},
/* instruction ORI */
{32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori},
/* instruction ANDI */
{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi},
/* instruction SLLI */
{32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli},
/* instruction SRLI */
{32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli},
/* instruction SRAI */
{32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai},
/* instruction ADD */
{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add},
/* instruction SUB */
{32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub},
/* instruction SLL */
{32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll},
/* instruction SLT */
{32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt},
/* instruction SLTU */
{32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu},
/* instruction XOR */
{32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor},
/* instruction SRL */
{32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl},
/* instruction SRA */
{32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra},
/* instruction OR */
{32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or},
/* instruction AND */
{32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and},
/* instruction FENCE */
{32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence},
/* instruction FENCE_I */
{32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i},
/* instruction ECALL */
{32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall},
/* instruction EBREAK */
{32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak},
/* instruction URET */
{32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret},
/* instruction SRET */
{32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret},
/* instruction MRET */
{32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret},
/* instruction WFI */
{32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi},
/* instruction SFENCE.VMA */
{32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma},
/* instruction CSRRW */
{32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw},
/* instruction CSRRS */
{32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs},
/* instruction CSRRC */
{32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc},
/* instruction CSRRWI */
{32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi},
/* instruction CSRRSI */
{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
/* instruction CSRRCI */
{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
/* instruction MUL */
{32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul},
/* instruction MULH */
{32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh},
/* instruction MULHSU */
{32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu},
/* instruction MULHU */
{32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu},
/* instruction DIV */
{32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div},
/* instruction DIVU */
{32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu},
/* instruction REM */
{32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem},
/* instruction REMU */
{32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu},
/* instruction LR.W */
{32, 0b00010000000000000010000000101111, 0b11111001111100000111000001111111, &this_class::__lr_w},
/* instruction SC.W */
{32, 0b00011000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__sc_w},
/* instruction AMOSWAP.W */
{32, 0b00001000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoswap_w},
/* instruction AMOADD.W */
{32, 0b00000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoadd_w},
/* instruction AMOXOR.W */
{32, 0b00100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoxor_w},
/* instruction AMOAND.W */
{32, 0b01100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoand_w},
/* instruction AMOOR.W */
{32, 0b01000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoor_w},
/* instruction AMOMIN.W */
{32, 0b10000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomin_w},
/* instruction AMOMAX.W */
{32, 0b10100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomax_w},
/* instruction AMOMINU.W */
{32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominu_w},
/* instruction AMOMAXU.W */
{32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_w},
/* instruction C.ADDI4SPN */
{16, 0b0000000000000000, 0b1110000000000011, &this_class::__c_addi4spn},
/* instruction C.LW */
{16, 0b0100000000000000, 0b1110000000000011, &this_class::__c_lw},
/* instruction C.SW */
{16, 0b1100000000000000, 0b1110000000000011, &this_class::__c_sw},
/* instruction C.ADDI */
{16, 0b0000000000000001, 0b1110000000000011, &this_class::__c_addi},
/* instruction C.NOP */
{16, 0b0000000000000001, 0b1111111111111111, &this_class::__c_nop},
/* instruction C.JAL */
{16, 0b0010000000000001, 0b1110000000000011, &this_class::__c_jal},
/* instruction C.LI */
{16, 0b0100000000000001, 0b1110000000000011, &this_class::__c_li},
/* instruction C.LUI */
{16, 0b0110000000000001, 0b1110000000000011, &this_class::__c_lui},
/* instruction C.ADDI16SP */
{16, 0b0110000100000001, 0b1110111110000011, &this_class::__c_addi16sp},
/* instruction C.SRLI */
{16, 0b1000000000000001, 0b1111110000000011, &this_class::__c_srli},
/* instruction C.SRAI */
{16, 0b1000010000000001, 0b1111110000000011, &this_class::__c_srai},
/* instruction C.ANDI */
{16, 0b1000100000000001, 0b1110110000000011, &this_class::__c_andi},
/* instruction C.SUB */
{16, 0b1000110000000001, 0b1111110001100011, &this_class::__c_sub},
/* instruction C.XOR */
{16, 0b1000110000100001, 0b1111110001100011, &this_class::__c_xor},
/* instruction C.OR */
{16, 0b1000110001000001, 0b1111110001100011, &this_class::__c_or},
/* instruction C.AND */
{16, 0b1000110001100001, 0b1111110001100011, &this_class::__c_and},
/* instruction C.J */
{16, 0b1010000000000001, 0b1110000000000011, &this_class::__c_j},
/* instruction C.BEQZ */
{16, 0b1100000000000001, 0b1110000000000011, &this_class::__c_beqz},
/* instruction C.BNEZ */
{16, 0b1110000000000001, 0b1110000000000011, &this_class::__c_bnez},
/* instruction C.SLLI */
{16, 0b0000000000000010, 0b1111000000000011, &this_class::__c_slli},
/* instruction C.LWSP */
{16, 0b0100000000000010, 0b1110000000000011, &this_class::__c_lwsp},
/* instruction C.MV */
{16, 0b1000000000000010, 0b1111000000000011, &this_class::__c_mv},
/* instruction C.JR */
{16, 0b1000000000000010, 0b1111000001111111, &this_class::__c_jr},
/* instruction C.ADD */
{16, 0b1001000000000010, 0b1111000000000011, &this_class::__c_add},
/* instruction C.JALR */
{16, 0b1001000000000010, 0b1111000001111111, &this_class::__c_jalr},
/* instruction C.EBREAK */
{16, 0b1001000000000010, 0b1111111111111111, &this_class::__c_ebreak},
/* instruction C.SWSP */
{16, 0b1100000000000010, 0b1110000000000011, &this_class::__c_swsp},
/* instruction DII */
{16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii},
}};
/* instruction definitions */
/* instruction 0: LUI */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lui(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("LUI");
this->gen_sync(iss::PRE_SYNC, 0);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
int32_t fld_imm_val = 0 | (signed_bit_sub<12,20>(instr) << 12);
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("LUI x%1$d, 0x%2$05x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_const(32U, fld_imm_val);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 0);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 1: AUIPC */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __auipc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("AUIPC");
this->gen_sync(iss::PRE_SYNC, 1);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
int32_t fld_imm_val = 0 | (signed_bit_sub<12,20>(instr) << 12);
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("AUIPC x%1%, 0x%2$08x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAdd(
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 1);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 2: JAL */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __jal(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("JAL");
this->gen_sync(iss::PRE_SYNC, 2);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
int32_t fld_imm_val = 0 | (bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (signed_bit_sub<31,1>(instr) << 20);
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("JAL x%1$d, 0x%2$x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAdd(
cur_pc_val,
this->gen_const(32U, 4));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
Value* PC_val = this->builder.CreateAdd(
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v");
this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
this->gen_sync(iss::POST_SYNC, 2);
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
}
/* instruction 3: JALR */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __jalr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("JALR");
this->gen_sync(iss::PRE_SYNC, 3);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("JALR x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* new_pc_val = this->builder.CreateAdd(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
Value* align_val = this->builder.CreateAnd(
new_pc_val,
this->gen_const(32U, 0x1));
{
llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk);
llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext);
llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext);
// this->builder.SetInsertPoint(bb);
this->gen_cond_branch(this->builder.CreateICmp(
ICmpInst::ICMP_NE,
align_val,
this->gen_const(32U, 0)),
bb_then,
bb_else);
this->builder.SetInsertPoint(bb_then);
{
this->gen_raise_trap(0, 0);
}
this->builder.CreateBr(bbnext);
this->builder.SetInsertPoint(bb_else);
{
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAdd(
cur_pc_val,
this->gen_const(32U, 4));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
Value* PC_val = this->builder.CreateAnd(
new_pc_val,
this->builder.CreateNot(this->gen_const(32U, 0x1)));
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
}
this->builder.CreateBr(bbnext);
bb=bbnext;
}
this->builder.SetInsertPoint(bb);
this->gen_sync(iss::POST_SYNC, 3);
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
}
/* instruction 4: BEQ */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __beq(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("BEQ");
this->gen_sync(iss::PRE_SYNC, 4);
int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("BEQ x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* PC_val = this->gen_choose(
this->builder.CreateICmp(
ICmpInst::ICMP_EQ,
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
this->builder.CreateAdd(
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_const(32U, 4)),
32);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v");
this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
this->gen_sync(iss::POST_SYNC, 4);
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
}
/* instruction 5: BNE */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __bne(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("BNE");
this->gen_sync(iss::PRE_SYNC, 5);
int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("BNE x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* PC_val = this->gen_choose(
this->builder.CreateICmp(
ICmpInst::ICMP_NE,
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
this->builder.CreateAdd(
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_const(32U, 4)),
32);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v");
this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
this->gen_sync(iss::POST_SYNC, 5);
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
}
/* instruction 6: BLT */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __blt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("BLT");
this->gen_sync(iss::PRE_SYNC, 6);
int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("BLT x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* PC_val = this->gen_choose(
this->builder.CreateICmp(
ICmpInst::ICMP_SLT,
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_ext(
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
32, true)),
this->builder.CreateAdd(
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_const(32U, 4)),
32);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v");
this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
this->gen_sync(iss::POST_SYNC, 6);
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
}
/* instruction 7: BGE */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __bge(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("BGE");
this->gen_sync(iss::PRE_SYNC, 7);
int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("BGE x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* PC_val = this->gen_choose(
this->builder.CreateICmp(
ICmpInst::ICMP_SGE,
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_ext(
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
32, true)),
this->builder.CreateAdd(
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_const(32U, 4)),
32);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v");
this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
this->gen_sync(iss::POST_SYNC, 7);
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
}
/* instruction 8: BLTU */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __bltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("BLTU");
this->gen_sync(iss::PRE_SYNC, 8);
int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("BLTU x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* PC_val = this->gen_choose(
this->builder.CreateICmp(
ICmpInst::ICMP_ULT,
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
this->builder.CreateAdd(
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_const(32U, 4)),
32);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v");
this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
this->gen_sync(iss::POST_SYNC, 8);
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
}
/* instruction 9: BGEU */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __bgeu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("BGEU");
this->gen_sync(iss::PRE_SYNC, 9);
int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("BGEU x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* PC_val = this->gen_choose(
this->builder.CreateICmp(
ICmpInst::ICMP_UGE,
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
this->builder.CreateAdd(
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_const(32U, 4)),
32);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
Value* is_cont_v = this->builder.CreateICmp(ICmpInst::ICMP_NE, PC_val, this->gen_const(32U, pc.val), "is_cont_v");
this->builder.CreateStore(this->gen_ext(is_cont_v, 32U, false), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
this->gen_sync(iss::POST_SYNC, 9);
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
}
/* instruction 10: LB */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("LB");
this->gen_sync(iss::PRE_SYNC, 10);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("LB x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 8/8),
32,
true);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 10);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 11: LH */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("LH");
this->gen_sync(iss::PRE_SYNC, 11);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("LH x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 16/8),
32,
true);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 11);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 12: LW */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("LW");
this->gen_sync(iss::PRE_SYNC, 12);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("LW x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 32/8),
32,
true);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 12);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 13: LBU */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lbu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("LBU");
this->gen_sync(iss::PRE_SYNC, 13);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("LBU x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 8/8),
32,
false);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 13);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 14: LHU */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lhu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("LHU");
this->gen_sync(iss::PRE_SYNC, 14);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("LHU x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
this->gen_read_mem(traits<ARCH>::MEM, offs_val, 16/8),
32,
false);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 14);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 15: SB */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SB");
this->gen_sync(iss::PRE_SYNC, 15);
int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SB x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
this->gen_write_mem(
traits<ARCH>::MEM,
offs_val,
this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(8)));
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 15);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 16: SH */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SH");
this->gen_sync(iss::PRE_SYNC, 16);
int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SH x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
this->gen_write_mem(
traits<ARCH>::MEM,
offs_val,
this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(16)));
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 16);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 17: SW */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SW");
this->gen_sync(iss::PRE_SYNC, 17);
int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SW x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
this->gen_write_mem(
traits<ARCH>::MEM,
offs_val,
this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32)));
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 17);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 18: ADDI */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __addi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("ADDI");
this->gen_sync(iss::PRE_SYNC, 18);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("ADDI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAdd(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 18);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 19: SLTI */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __slti(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SLTI");
this->gen_sync(iss::PRE_SYNC, 19);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SLTI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_choose(
this->builder.CreateICmp(
ICmpInst::ICMP_SLT,
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val)),
this->gen_const(32U, 1),
this->gen_const(32U, 0),
32);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 19);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 20: SLTIU */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sltiu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SLTIU");
this->gen_sync(iss::PRE_SYNC, 20);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SLTIU x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
int32_t full_imm_val = fld_imm_val;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_choose(
this->builder.CreateICmp(
ICmpInst::ICMP_ULT,
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_const(32U, full_imm_val)),
this->gen_const(32U, 1),
this->gen_const(32U, 0),
32);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 20);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 21: XORI */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __xori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("XORI");
this->gen_sync(iss::PRE_SYNC, 21);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("XORI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateXor(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 21);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 22: ORI */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __ori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("ORI");
this->gen_sync(iss::PRE_SYNC, 22);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("ORI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateOr(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 22);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 23: ANDI */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __andi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("ANDI");
this->gen_sync(iss::PRE_SYNC, 23);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAnd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 23);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 24: SLLI */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __slli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SLLI");
this->gen_sync(iss::PRE_SYNC, 24);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_shamt_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SLLI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_shamt_val > 31){
this->gen_raise_trap(0, 0);
} else {
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateShl(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_const(32U, fld_shamt_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 24);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 25: SRLI */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __srli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SRLI");
this->gen_sync(iss::PRE_SYNC, 25);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_shamt_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SRLI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_shamt_val > 31){
this->gen_raise_trap(0, 0);
} else {
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateLShr(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_const(32U, fld_shamt_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 25);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 26: SRAI */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __srai(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SRAI");
this->gen_sync(iss::PRE_SYNC, 26);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_shamt_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SRAI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_shamt_val > 31){
this->gen_raise_trap(0, 0);
} else {
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAShr(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_const(32U, fld_shamt_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 26);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 27: ADD */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __add(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("ADD");
this->gen_sync(iss::PRE_SYNC, 27);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("ADD x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 27);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 28: SUB */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sub(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SUB");
this->gen_sync(iss::PRE_SYNC, 28);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SUB x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateSub(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 28);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 29: SLL */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sll(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SLL");
this->gen_sync(iss::PRE_SYNC, 29);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SLL x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateShl(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->builder.CreateAnd(
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
this->gen_const(32U, 0x1f)));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 29);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 30: SLT */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __slt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SLT");
this->gen_sync(iss::PRE_SYNC, 30);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SLT x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_choose(
this->builder.CreateICmp(
ICmpInst::ICMP_SLT,
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_ext(
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
32, true)),
this->gen_const(32U, 1),
this->gen_const(32U, 0),
32);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 30);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 31: SLTU */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SLTU");
this->gen_sync(iss::PRE_SYNC, 31);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SLTU x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_choose(
this->builder.CreateICmp(
ICmpInst::ICMP_ULT,
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32,
false),
this->gen_ext(
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
32,
false)),
this->gen_const(32U, 1),
this->gen_const(32U, 0),
32);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 31);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 32: XOR */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __xor(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("XOR");
this->gen_sync(iss::PRE_SYNC, 32);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("XOR x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateXor(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 32);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 33: SRL */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __srl(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SRL");
this->gen_sync(iss::PRE_SYNC, 33);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SRL x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateLShr(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->builder.CreateAnd(
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
this->gen_const(32U, 0x1f)));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 33);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 34: SRA */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __sra(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("SRA");
this->gen_sync(iss::PRE_SYNC, 34);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("SRA x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAShr(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->builder.CreateAnd(
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
this->gen_const(32U, 0x1f)));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 34);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 35: OR */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __or(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("OR");
this->gen_sync(iss::PRE_SYNC, 35);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("OR x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateOr(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 35);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 36: AND */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __and(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("AND");
this->gen_sync(iss::PRE_SYNC, 36);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("AND x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr(ins_fmter.str()),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAnd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 36);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 37: FENCE */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __fence(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("FENCE");
this->gen_sync(iss::PRE_SYNC, 37);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint8_t fld_succ_val = 0 | (bit_sub<20,4>(instr));
uint8_t fld_pred_val = 0 | (bit_sub<24,4>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr("FENCE"),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* FENCEtmp0_val = this->builder.CreateOr(
this->builder.CreateShl(
this->gen_const(32U, fld_pred_val),
this->gen_const(32U, 4)),
this->gen_const(32U, fld_succ_val));
this->gen_write_mem(
traits<ARCH>::FENCE,
this->gen_const(64U, 0),
this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32)));
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 37);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
this->gen_trap_check(bb);
return std::make_tuple(vm::CONT, bb);
}
/* instruction 38: FENCE_I */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __fence_i(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("FENCE_I");
this->gen_sync(iss::PRE_SYNC, 38);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
this->builder.CreateGlobalStringPtr("FENCE_I"),
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
Value* FENCEtmp0_val = this->gen_const(32U, fld_imm_val);
this->gen_write_mem(
traits<ARCH>::FENCE,
this->gen_const(64U, 1),
this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32)));
this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 38);
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::FLUSH, nullptr);
}
/* instruction 39: ECALL */
std::tuple<vm::continuation_e, llvm::BasicBlock*> __ecall(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("ECALL");