Am instruction set simulator based on DBT-RISE implementing the RISC-V ISA
This is work in progress, so use at your own risk. Goal is to implement an open-source ISS which can easily embedded e.g. into SystemC Virtual Prototypes. It used code generation to allow easy extension and adaptation of the used instruction. The RISC-V ISS reaches about 30MIPS running on Intel Core i7-2600K.
The implementation is based on LLVM 4.0. Eclipse CDT 4.7 (Oxygen) is recommended as IDE.
pip install conan
conan remote add minres https://api.bintray.com/conan/minres/conan-repo conan remote add bincrafters https://api.bintray.com/conan/bincrafters/public-conan
cd DBT-RISE-RiscV mkdir build cd build cmake .. cmake --build .