Generic RISC-V ISS
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 
 
Eyck Jentzsch dfcc3ace66 Adapted generated code to support translation block linking 2 years ago
.settings Adapted generated code to support translation block linking 2 years ago
cmake Adapted plugin behavior obeying availabiltiy of instrumentation 2 years ago
dbt-core@b7e5fd5113 Adapted generated code to support translation block linking 2 years ago
etc Adapted generated code to support translation block linking 2 years ago
external Updated CMake settings 2 years ago
html Fixed transaction linking and gpio visualization 3 years ago
riscv Adapted generated code to support translation block linking 2 years ago
riscv.sc Adapted generated code to support translation block linking 2 years ago
sc-components@bab66d1744 Updated sc-components 2 years ago
softfloat Added RV32D extension 2 years ago
.clang-format Added clang-format formatting 3 years ago
.cproject Adapted generated code to support translation block linking 2 years ago
.gitignore Moved to cmake4eclipse builder 2 years ago
.gitmodules Fixed submodules spec 3 years ago
.project Updated Eclipse project name 2 years ago
CMakeLists.txt Adapted generated code to support translation block linking 2 years ago
LICENSE Initial commit 3 years ago
README.md Added use of CCI and support of LLVM 5.0 2 years ago
build.sh Moved to cmake4eclipse builder 2 years ago
conanfile.txt Adapted plugin behavior obeying availabiltiy of instrumentation 2 years ago
cycles.txt Made plugin call configurable 2 years ago
simple-system.json Updated CMake settings 2 years ago

README.md

DBT-RISE-RISCV

Am instruction set simulator based on DBT-RISE implementing the RISC-V ISA

DBT-RISE-RISCV README

This is work in progress, so use at your own risk. Goal is to implement an open-source ISS which can easily embedded e.g. into SystemC Virtual Prototypes. It used code generation to allow easy extension and adaptation of the used instruction. The RISC-V ISS reaches about 30MIPS running on Intel Core i7-2600K.

The implementation is based on LLVM 4.0. Eclipse CDT 4.7 (Oxygen) is recommended as IDE.

DBT-RISE-RISCV uses libGIS (https://github.com/vsergeev/libGIS) as well as ELFIO (http://elfio.sourceforge.net/), both under MIT license

What's missing

  • F & D standard extensions for 32bit to be implemented
  • MACF &D standard extensions for 64bit to be implemented and verified

Planned features

  • add platform peripherals beyond programmers view to resemble E300 platform
    • QSPI
    • PWM
    • ...
  • and more

Quick start

    pip install conan
  • setup conan to use the minres repo:
    conan remote add minres https://api.bintray.com/conan/minres/conan-repo
    conan remote add bincrafters https://api.bintray.com/conan/bincrafters/public-conan
  • checkout source from git
  • start an out-of-source build:
    cd DBT-RISE-RiscV
    mkdir build
    cd build
    cmake ..
    cmake --build .
  • if you encounter issues when linking wrt. c++11 symbols you might have run into GCC ABI incompatibility introduced from GCC 5.0 onwards. You can fix this by adding '-s compiler.libcxx=libstdc++11' to the conan call or changing compiler.libcxx to
compiler.libcxx=libstdc++11

in $HOME/.conan/profiles/default