RISCVBase.core_desc 1.6KB

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  1. InsructionSet RISCVBase {
  2. constants {
  3. XLEN,
  4. fence:=0,
  5. fencei:=1,
  6. fencevmal:=2,
  7. fencevmau:=3
  8. }
  9. address_spaces {
  10. MEM[8], CSR[XLEN], FENCE[XLEN], RES[8]
  11. }
  12. registers {
  13. [31:0] X[XLEN],
  14. PC[XLEN](is_pc),
  15. alias ZERO[XLEN] is X[0],
  16. alias RA[XLEN] is X[1],
  17. alias SP[XLEN] is X[2],
  18. alias GP[XLEN] is X[3],
  19. alias TP[XLEN] is X[4],
  20. alias T0[XLEN] is X[5],
  21. alias T1[XLEN] is X[6],
  22. alias T2[XLEN] is X[7],
  23. alias S0[XLEN] is X[8],
  24. alias S1[XLEN] is X[9],
  25. alias A0[XLEN] is X[10],
  26. alias A1[XLEN] is X[11],
  27. alias A2[XLEN] is X[12],
  28. alias A3[XLEN] is X[13],
  29. alias A4[XLEN] is X[14],
  30. alias A5[XLEN] is X[15],
  31. alias A6[XLEN] is X[16],
  32. alias A7[XLEN] is X[17],
  33. alias S2[XLEN] is X[18],
  34. alias S3[XLEN] is X[19],
  35. alias S4[XLEN] is X[20],
  36. alias S5[XLEN] is X[21],
  37. alias S6[XLEN] is X[22],
  38. alias S7[XLEN] is X[23],
  39. alias S8[XLEN] is X[24],
  40. alias S9[XLEN] is X[25],
  41. alias S10[XLEN] is X[26],
  42. alias S11[XLEN] is X[27],
  43. alias T3[XLEN] is X[28],
  44. alias T4[XLEN] is X[29],
  45. alias T5[XLEN] is X[30],
  46. alias T6[XLEN] is X[31]
  47. }
  48. }