|Eyck Jentzsch d037141d98 Fixed C++11 compatibility||4 months ago|
|.settings||1 year ago|
|gen_input||4 months ago|
|incl||4 months ago|
|softfloat||5 months ago|
|src||4 months ago|
|.clang-format||2 years ago|
|.cproject||5 months ago|
|.gitignore||5 months ago|
|.project||1 year ago|
|CMakeLists.txt||4 months ago|
|CMakeLists.txt.orig||5 months ago|
|LICENSE||2 years ago|
|README.md||4 months ago|
Core of an instruction set simulator based on DBT-RISE implementing the RISC-V ISA. The project is hosted at https://git.minres.com/DBT-RISE/DBT-RISE-RISCV .
This library provide the infrastructure to build RISC-V ISS. Currently part of the library are the following implementations adhering to version 2.2 of the 'The RISC-V Instruction Set Manual Volume I: User-Level ISA':
All pass the respective compliance tests. Along with those ISA implementations there is a wrapper implementing the M/S/U modes inlcuding virtual memory management and CSRs as of privileged spec 1.10. The main.cpp in src allows to build a standalone ISS when integrated into a top-level project. For further information please have a look at https://git.minres.com/VP/RISCV-VP.
Last but not least an SystemC wrapper is provided which allows easy integration into SystemC based virtual platforms.
Since DBT-RISE uses a generative approch other needed combinations or custom extension can be generated. For further information please contact email@example.com.