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Fixed implementation of RV64 so that remaining riscv-test pass

eyck 4 months ago
parent
commit
f69b529cab

+ 3
- 1
CMakeLists.txt View File

@@ -2,6 +2,7 @@ cmake_minimum_required(VERSION 3.3)
2 2
 set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake ${CMAKE_CURRENT_SOURCE_DIR}/sc-components/cmake)
3 3
 
4 4
 set(ENABLE_SCV TRUE CACHE BOOL "Enable use of SCV")
5
+set(ENABLE_SHARED TRUE CACHE BOOL "Build shared libraries")
5 6
 
6 7
 include(GitFunctions)
7 8
 get_branch_from_git()
@@ -32,7 +33,8 @@ include(Conan)
32 33
 set(CMAKE_CXX_STANDARD 14)
33 34
 set(CMAKE_CXX_STANDARD_REQUIRED ON)
34 35
 set(CMAKE_CXX_EXTENSIONS OFF)
35
-	
36
+set(CMAKE_POSITION_INDEPENDENT_CODE ON)
37
+
36 38
 include(CheckCXXCompilerFlag)
37 39
 CHECK_CXX_COMPILER_FLAG("-march=native" COMPILER_SUPPORTS_MARCH_NATIVE)
38 40
 if(COMPILER_SUPPORTS_MARCH_NATIVE)

+ 12
- 2
platform/src/CMakeLists.txt View File

@@ -30,7 +30,17 @@ set(LIBRARY_NAME platform)
30 30
 #add_definitions(-DSC_DEFAULT_WRITER_POLICY=SC_MANY_WRITERS)
31 31
 
32 32
 # Define the library
33
-add_library(${LIBRARY_NAME} ${LIB_SOURCES})
33
+add_library(${LIBRARY_NAME} SHARED ${LIB_SOURCES})
34
+
35
+# Links the target exe against the libraries
36
+target_link_libraries(${LIBRARY_NAME} riscv_sc)
37
+target_link_libraries(${LIBRARY_NAME} dbt-core)
38
+target_link_libraries(${LIBRARY_NAME} softfloat)
39
+target_link_libraries(${LIBRARY_NAME} sc-components)
40
+target_link_libraries(${LIBRARY_NAME} ${CONAN_LIBS_SEASOCKS})
41
+target_link_libraries(${LIBRARY_NAME} external)
42
+target_link_libraries(${LIBRARY_NAME} ${llvm_libs})
43
+target_link_libraries(${LIBRARY_NAME} ${Boost_LIBRARIES} )
34 44
 
35 45
 set_target_properties(${LIBRARY_NAME} PROPERTIES
36 46
   VERSION ${VERSION}  # ${VERSION} was defined in the main CMakeLists.
@@ -61,7 +71,7 @@ add_executable(${APPLICATION_NAME} ${APP_SOURCES})
61 71
 target_include_directories(${APPLICATION_NAME} SYSTEM PRIVATE ${LLVM_INCLUDE_DIRS})
62 72
 # Links the target exe against the libraries
63 73
 target_link_libraries(${APPLICATION_NAME} ${LIBRARY_NAME})
64
-target_link_libraries(${APPLICATION_NAME} riscv)
74
+target_link_libraries(${APPLICATION_NAME} riscv_sc)
65 75
 target_link_libraries(${APPLICATION_NAME} dbt-core)
66 76
 target_link_libraries(${APPLICATION_NAME} softfloat)
67 77
 target_link_libraries(${APPLICATION_NAME} sc-components)

+ 9
- 13
riscv/gen_input/RV32A.core_desc View File

@@ -2,10 +2,6 @@ import "RV32IBase.core_desc"
2 2
 
3 3
 InsructionSet RV32A extends RV32IBase{
4 4
      
5
-    address_spaces { 
6
-        RES[8]
7
-    }
8
-    
9 5
     instructions{
10 6
         LR.W {
11 7
             encoding: b00010 | aq[0:0] | rl[0:0]  | b00000 | rs1[4:0] | b010 | rd[4:0] | b0101111;
@@ -23,7 +19,7 @@ InsructionSet RV32A extends RV32IBase{
23 19
             val res1[32] <= RES[offs]{32};
24 20
             if(res1!=0)
25 21
                 MEM[offs]{32} <= X[rs2];
26
-            if(rd!=0) X[rd]<= choose(res1!=0, 0, 1);
22
+            if(rd!=0) X[rd]<= choose(res1!=zext(0, 32), 0, 1);
27 23
         }
28 24
         AMOSWAP.W{
29 25
             encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
@@ -73,9 +69,9 @@ InsructionSet RV32A extends RV32IBase{
73 69
             args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
74 70
             val offs[XLEN]<=X[rs1];
75 71
             val res1[XLEN] <= sext(MEM[offs]{32});
76
-            if(rd!=0) X[rd]<=res1;
77
-            val res2[XLEN]<= choose(res1's>X[rs2]s, X[rs2], res1);
78
-            MEM[offs]{32}<=res2;
72
+            if(rd!=0) X[rd] <= res1;
73
+            val res2[XLEN] <= choose(res1's > X[rs2]s, X[rs2], res1);
74
+            MEM[offs]{32} <= res2;
79 75
         }
80 76
         AMOMAX.W{
81 77
             encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
@@ -90,7 +86,7 @@ InsructionSet RV32A extends RV32IBase{
90 86
             encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
91 87
             args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
92 88
             val offs[XLEN]<=X[rs1];
93
-            val res1[XLEN] <= zext(MEM[offs]{32});
89
+            val res1[XLEN] <= sext(MEM[offs]{32});
94 90
             if(rd!=0) X[rd]<=res1;
95 91
             val res2[XLEN]<= choose(res1>X[rs2], X[rs2], res1);
96 92
             MEM[offs]{32}<=res2;
@@ -99,10 +95,10 @@ InsructionSet RV32A extends RV32IBase{
99 95
             encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
100 96
             args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
101 97
             val offs[XLEN]<=X[rs1];
102
-            val res1[XLEN] <= zext(MEM[offs]{32});
103
-            if(rd!=0) X[rd]<=res1;
104
-            val res2[XLEN]<= choose(res1'u<X[rs2]'u, X[rs2], res1);
105
-            MEM[offs]{32}<=res2;
98
+            val res1[XLEN] <= sext(MEM[offs]{32});
99
+            if(rd!=0) X[rd] <= res1;
100
+            val res2[XLEN] <= choose(res1 < X[rs2], X[rs2], res1);
101
+            MEM[offs]{32} <= res2;
106 102
         }
107 103
     }
108 104
 }

+ 68
- 26
riscv/gen_input/RV32C.core_desc View File

@@ -15,14 +15,9 @@ InsructionSet RV32IC {
15 15
         JALR(no_cont){ // overwriting the implementation if rv32i, alignment does not need to be word
16 16
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
17 17
             args_disass: "{name(rd)}, {name(rs1)}, {imm:#0x}";
18
-            val new_pc[XLEN] <= X[rs1]s+ imm;
19
-            val align[XLEN] <= new_pc & 0x1;
20
-            if(align != 0){
21
-                raise(0, 0);
22
-            } else {
23
-                if(rd!=0) X[rd] <= PC+4;
24
-                PC<=new_pc & ~0x1;
25
-            }
18
+            val new_pc[XLEN] <= X[rs1]s + imm;
19
+            if(rd!=0) X[rd] <= PC+4;
20
+            PC<=new_pc & ~0x1;
26 21
         }
27 22
         C.ADDI4SPN { //(RES, imm=0)
28 23
             encoding: b000 | imm[5:4] | imm[9:6] | imm[2:2] | imm[3:3] | rd[2:0] | b00;
@@ -32,13 +27,13 @@ InsructionSet RV32IC {
32 27
         }
33 28
         C.LW { // (RV32)
34 29
             encoding: b010 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
35
-            args_disass: "{name(8+rd)}, {name(8+rs1)}, {uimm:#05x}";
30
+            args_disass: "{name(8+rd)}, {uimm:#05x}({name(8+rs1)})";
36 31
             val offs[XLEN] <= X[rs1+8]+uimm;
37
-            X[rd+8] <= MEM[offs]{32};
32
+            X[rd+8] <= sext(MEM[offs]{32});
38 33
         }
39 34
         C.SW {//(RV32)
40 35
             encoding: b110 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
41
-            args_disass: "{name(8+rs1)}, {name(8+rs2)}, {uimm:#05x}";
36
+            args_disass: "{name(8+rs2)}, {uimm:#05x}({name(8+rs1)})";
42 37
             val offs[XLEN] <= X[rs1+8]+uimm;
43 38
             MEM[offs]{32} <= X[rs2+8];
44 39
         }
@@ -89,10 +84,10 @@ InsructionSet RV32IC {
89 84
             X[rs1_idx] <= shra(X[rs1_idx], shamt);
90 85
         }
91 86
         C.ANDI {//(RV32)
92
-            encoding:b100 | imm[5:5] | b10 | rs1[2:0] | imm[4:0] | b01;
87
+            encoding:b100 | imm[5:5]s | b10 | rs1[2:0] | imm[4:0]s | b01;
93 88
             args_disass: "{name(8+rs1)}, {imm:#05x}";
94 89
             val rs1_idx[5] <= rs1 + 8;
95
-            X[rs1_idx] <= X[rs1_idx] & imm;
90
+            X[rs1_idx] <= X[rs1_idx]s & imm;
96 91
         }
97 92
         C.SUB {//(RV32)
98 93
             encoding:b100 | b0 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
@@ -143,7 +138,7 @@ InsructionSet RV32IC {
143 138
             encoding:b010 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
144 139
             args_disass: "{name(rd)}, sp, {uimm:#05x}";
145 140
             val offs[XLEN] <= X[2] + uimm;
146
-            X[rd] <= MEM[offs]{32};
141
+            X[rd] <= sext(MEM[offs]{32});
147 142
         }
148 143
         // order matters as C.JR is a special case of C.MV
149 144
         C.MV {//(RV32)
@@ -174,7 +169,7 @@ InsructionSet RV32IC {
174 169
         }
175 170
         C.SWSP {//
176 171
             encoding:b110 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
177
-            args_disass: "x2+{uimm:#05x}, {name(rs2)}";
172
+            args_disass: "{name(rs2)}, {uimm:#05x}(sp)";
178 173
             val offs[XLEN] <= X[2] + uimm;
179 174
             MEM[offs]{32} <= X[rs2];
180 175
         }
@@ -301,36 +296,65 @@ InsructionSet RV64IC extends RV32IC {
301 296
     instructions{
302 297
         C.LD {//(RV64/128) 
303 298
             encoding:b011 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
299
+            args_disass: "{name(8+rd)}, {uimm},({name(8+rs1)})";
300
+            val offs[XLEN] <= X[rs1+8] + uimm;
301
+            X[rd+8]<=sext(MEM[offs]{64});
304 302
         }
305 303
         C.SD { //(RV64/128) 
306 304
             encoding:b111 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
305
+            args_disass: "{name(8+rs2)}, {uimm},({name(8+rs1)})";
306
+            val offs[XLEN] <= X[rs1+8] + uimm;
307
+            MEM[offs]{64} <= X[rs2+8];
307 308
         }
308 309
         C.SUBW {//(RV64/128, RV32 res)
309 310
             encoding:b100 | b1 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
310
-            args_disass: "{name(rd)}, sp, {imm:#05x}";
311
+            args_disass: "{name(8+rd)}, {name(8+rd)}, {name(8+rs2)}";
312
+            val res[32] <= X[rd+8]{32} - X[rs2+8]{32};
313
+            X[rd+8] <= sext(res);
311 314
         }
312 315
         C.ADDW {//(RV64/128 RV32 res)
313 316
             encoding:b100 | b1 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
314
-            args_disass: "{name(rd)}, sp, {imm:#05x}";
317
+            args_disass: "{name(8+rd)}, {name(8+rd)}, {name(8+rs2)}";   
318
+            val res[32] <= X[rd+8]{32} + X[rs2+8]{32};
319
+            X[rd+8] <= sext(res);
315 320
         }
316 321
         C.ADDIW {//(RV64/128)
317
-            encoding:b001 | imm[5:5] | rs1[4:0] | imm[4:0] | b01;
322
+            encoding:b001 | imm[5:5]s | rs1[4:0] | imm[4:0]s | b01;
323
+            args_disass: "{name(rs1)}, {imm:#05x}";
324
+            if(rs1 != 0){
325
+                val res[32] <= X[rs1]{32}'s + imm;
326
+                X[rs1] <= sext(res);
327
+            } 
318 328
         }
319
-           C.SRLI64 {//(RV32/64/128)
320
-              encoding:b100 | b0 | b00 | rs1[2:0] | b00000 | b01;
321
-          }
322
-        C.SRAI64 {//(RV32/64/128)
323
-            encoding:b100 | b0 | b01 | rs1[2:0] | b00000 | b01;
329
+        C.SRLI {//(RV64)
330
+            encoding:b100 | shamt[5:5] | b00 | rs1[2:0] | shamt[4:0] | b01;
331
+            args_disass: "{name(8+rs1)}, {shamt}";
332
+            val rs1_idx[5] <= rs1+8;
333
+            X[rs1_idx] <= shrl(X[rs1_idx], shamt);
324 334
         }
325
-        C.SLLI64 {//(RV128 RV32/64)
326
-            encoding:b000 | b0 | rs1[4:0] | b00000 | b10;
335
+        C.SRAI {//(RV64)
336
+            encoding:b100 | shamt[5:5] | b01 | rs1[2:0] | shamt[4:0] | b01;
337
+            args_disass: "{name(8+rs1)}, {shamt}";
338
+            val rs1_idx[5] <= rs1+8;
339
+            X[rs1_idx] <= shra(X[rs1_idx], shamt);
340
+        }
341
+        C.SLLI {//(RV64)
342
+            encoding:b000 | shamt[5:5] | rs1[4:0] | shamt[4:0] | b10;
343
+            args_disass: "{name(rs1)}, {shamt}";
344
+            if(rs1 == 0) raise(0, 2);
345
+            X[rs1] <= shll(X[rs1], shamt);
327 346
         }
328 347
         C.LDSP {//(RV64/128
329 348
             encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
330
-            args_disass: "{name(rd)}, sp, {imm:#05x}";
349
+            args_disass:"{name(rd)}, {uimm}(sp)";
350
+            val offs[XLEN] <= X[2] + uimm;
351
+            if(rd!=0) X[rd]<=sext(MEM[offs]{64});
331 352
         }
332 353
         C.SDSP {//(RV64/128)
333 354
             encoding:b111 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
355
+            args_disass:"{name(rs2)}, {uimm}(sp)";
356
+            val offs[XLEN] <= X[2] + uimm;
357
+            MEM[offs]{64} <= X[rs2];
334 358
         }
335 359
     }
336 360
 }
@@ -347,6 +371,24 @@ InsructionSet RV128IC extends RV64IC {
347 371
                 PC[XLEN](is_pc)
348 372
     }
349 373
     instructions{
374
+        C.SRLI {//(RV128)
375
+            encoding:b100 | shamt[5:5] | b00 | rs1[2:0] | shamt[4:0] | b01;
376
+            args_disass: "{name(8+rs1)}, {shamt}";
377
+            val rs1_idx[5] <= rs1+8;
378
+            X[rs1_idx] <= shrl(X[rs1_idx], shamt);
379
+        }
380
+        C.SRAI {//(RV128)
381
+            encoding:b100 | shamt[5:5] | b01 | rs1[2:0] | shamt[4:0] | b01;
382
+            args_disass: "{name(8+rs1)}, {shamt}";
383
+            val rs1_idx[5] <= rs1+8;
384
+            X[rs1_idx] <= shra(X[rs1_idx], shamt);
385
+        }
386
+        C.SLLI {//(RV128)
387
+            encoding:b000 | shamt[5:5] | rs1[4:0] | shamt[4:0] | b10;
388
+            args_disass: "{name(rs1)}, {shamt}";
389
+            if(rs1 == 0) raise(0, 2);
390
+            X[rs1] <= shll(X[rs1], shamt);
391
+        }
350 392
         C.LQ { //(RV128)
351 393
              encoding:b001 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
352 394
         }

+ 82
- 14
riscv/gen_input/RV32D.core_desc View File

@@ -10,7 +10,7 @@ InsructionSet RV32D extends RV32IBase{
10 10
     instructions{
11 11
         FLD {
12 12
             encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000111;
13
-            args_disass:"f{rd}, {imm}({rs1})";
13
+            args_disass:"f{rd}, {imm}({name(rs1)})";
14 14
             val offs[XLEN] <= X[rs1]'s + imm;
15 15
             val res[64] <= MEM[offs]{64};
16 16
             if(FLEN==64)
@@ -22,7 +22,7 @@ InsructionSet RV32D extends RV32IBase{
22 22
         }
23 23
         FSD {
24 24
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100111;
25
-            args_disass:"f{rs2}, {imm}({rs1})";
25
+            args_disass:"f{rs2}, {imm}({name(rs1)})";
26 26
             val offs[XLEN] <= X[rs1]'s + imm;
27 27
             MEM[offs]{64}<=F[rs2]{64};
28 28
         }
@@ -155,7 +155,10 @@ InsructionSet RV32D extends RV32IBase{
155 155
         FSGNJ.D {
156 156
             encoding: b0010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
157 157
             args_disass:"f{rd}, f{rs1}, f{rs2}";
158
-            val res[64] <= (F[rs1]{64} & 0x7fffffff) | (F[rs2]{64} & 0x80000000);
158
+            val ONE[64] <= 1;
159
+            val MSK1[64] <= ONE<<63;
160
+            val MSK2[64] <= MSK1-1;
161
+            val res[64] <= (F[rs1]{64} & MSK2) | (F[rs2]{64} & MSK1);
159 162
             if(FLEN==64)
160 163
                 F[rd] <= res;
161 164
             else { // NaN boxing
@@ -166,7 +169,10 @@ InsructionSet RV32D extends RV32IBase{
166 169
         FSGNJN.D {
167 170
             encoding: b0010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
168 171
             args_disass:"f{rd}, f{rs1}, f{rs2}";
169
-            val res[64] <= (F[rs1]{64} & 0x7fffffff) | (~F[rs2]{64} & 0x80000000);
172
+            val ONE[64] <= 1;
173
+            val MSK1[64] <= ONE<<63;
174
+            val MSK2[64] <= MSK1-1;
175
+            val res[64] <= (F[rs1]{64} & MSK2) | (~F[rs2]{64} & MSK1);
170 176
             if(FLEN==64)
171 177
                 F[rd] <= res;
172 178
             else { // NaN boxing
@@ -177,7 +183,9 @@ InsructionSet RV32D extends RV32IBase{
177 183
         FSGNJX.D {
178 184
             encoding: b0010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
179 185
             args_disass:"f{rd}, f{rs1}, f{rs2}";
180
-            val res[64] <= F[rs1]{64} ^ (F[rs2]{64} & 0x80000000);
186
+            val ONE[64] <= 1;
187
+            val MSK1[64] <= ONE<<63;
188
+            val res[64] <= F[rs1]{64} ^ (F[rs2]{64} & MSK1);
181 189
             if(FLEN==64)
182 190
                 F[rd] <= res;
183 191
             else { // NaN boxing
@@ -235,21 +243,21 @@ InsructionSet RV32D extends RV32IBase{
235 243
         FEQ.D {
236 244
             encoding: b1010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
237 245
             args_disass:"{name(rd)}, f{rs1}, f{rs2}";
238
-            X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32));
246
+            X[rd]<=zext(fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32)));
239 247
             val flags[32] <= fdispatch_fget_flags();
240 248
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
241 249
         }
242 250
         FLT.D {
243 251
             encoding: b1010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
244 252
             args_disass:"{name(rd)}, f{rs1}, f{rs2}";
245
-            X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(2, 32));
253
+            X[rd]<=zext(fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(2, 32)));
246 254
             val flags[32] <= fdispatch_fget_flags();
247 255
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
248 256
         }
249 257
         FLE.D {
250 258
             encoding: b1010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
251 259
             args_disass:"{name(rd)}, f{rs1}, f{rs2}";
252
-            X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32));
260
+            X[rd]<=zext(fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32)));
253 261
             val flags[32] <= fdispatch_fget_flags();
254 262
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
255 263
         }
@@ -261,21 +269,22 @@ InsructionSet RV32D extends RV32IBase{
261 269
         FCVT.W.D {
262 270
             encoding: b1100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
263 271
             args_disass:"{name(rd)}, f{rs1}";
264
-            X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(0, 32), rm{8}), XLEN);
272
+            X[rd]<= sext(fdispatch_fcvt_64_32(F[rs1]{64}, zext(0, 32), rm{8}), XLEN);
265 273
             val flags[32] <= fdispatch_fget_flags();
266 274
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
267 275
         }
268 276
         FCVT.WU.D {
269 277
             encoding: b1100001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
270 278
             args_disass:"{name(rd)}, f{rs1}";
271
-            X[rd]<= zext(fdispatch_fcvt_d(F[rs1]{64}, zext(1, 32), rm{8}), XLEN);
279
+            //FIXME: should be zext accodring to spec but needs to be sext according to tests
280
+            X[rd]<= sext(fdispatch_fcvt_64_32(F[rs1]{64}, zext(1, 32), rm{8}), XLEN);
272 281
             val flags[32] <= fdispatch_fget_flags();
273 282
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
274 283
         }
275 284
         FCVT.D.W {
276 285
             encoding: b1101001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
277
-            args_disass:"f{rd}, {rs1}";
278
-            val res[64] <= fdispatch_fcvt_d(sext(X[rs1],64), zext(2, 32), rm{8});
286
+            args_disass:"f{rd}, {name(rs1)}";
287
+            val res[64] <= fdispatch_fcvt_32_64(sext(X[rs1]{32},64), zext(2, 32), rm{8});
279 288
             if(FLEN==64)
280 289
                 F[rd] <= res;
281 290
             else { // NaN boxing
@@ -285,7 +294,53 @@ InsructionSet RV32D extends RV32IBase{
285 294
         }
286 295
         FCVT.D.WU {
287 296
             encoding: b1101001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
288
-            args_disass:"f{rd}, {rs1}";
297
+            args_disass:"f{rd}, {name(rs1)}";
298
+            val res[64] <=fdispatch_fcvt_32_64(zext(X[rs1]{32},64), zext(3,32), rm{8});
299
+            if(FLEN==64)
300
+                F[rd] <= res;
301
+            else { // NaN boxing
302
+                val upper[FLEN] <= -1;
303
+                F[rd] <= (upper<<64) | res;
304
+            }
305
+        }
306
+    }
307
+}
308
+InsructionSet RV64D extends RV32D{
309
+    constants {
310
+        FLEN, FFLAG_MASK := 0x1f
311
+    } 
312
+    registers {
313
+        [31:0]    F[FLEN],  FCSR[32]
314
+    }    
315
+    instructions{
316
+        FCVT.L.D {
317
+            encoding: b1100001 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
318
+            args_disass:"{name(rd)}, f{rs1}";
319
+            X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(0, 32), rm{8}), XLEN);
320
+            val flags[32] <= fdispatch_fget_flags();
321
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
322
+        }
323
+        FCVT.LU.D {
324
+            encoding: b1100001 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
325
+            args_disass:"{name(rd)}, f{rs1}";
326
+            X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(1, 32), rm{8}), XLEN);
327
+            val flags[32] <= fdispatch_fget_flags();
328
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
329
+        }
330
+        FCVT.D.L {
331
+            encoding: b1101001 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
332
+            args_disass:"f{rd}, {name(rs1)}";
333
+            val res[64] <= fdispatch_fcvt_d(sext(X[rs1],64), zext(2, 32), rm{8});
334
+            if(FLEN==64)
335
+                F[rd] <= res;
336
+            else { // NaN boxing
337
+                val upper[FLEN] <= -1;
338
+                F[rd] <= (upper<<64) | res;
339
+            }
340
+        }
341
+        FCVT.D.LU {
342
+            encoding: b1101001 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
343
+            args_disass:"f{rd}, {name(rs1)}";
289 344
             val res[64] <=fdispatch_fcvt_d(zext(X[rs1],64), zext(3,32), rm{8});
290 345
             if(FLEN==64)
291 346
                 F[rd] <= res;
@@ -294,5 +349,18 @@ InsructionSet RV32D extends RV32IBase{
294 349
                 F[rd] <= (upper<<64) | res;
295 350
             }
296 351
         }
352
+        FMV.X.D {
353
+            encoding: b1110001 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
354
+            args_disass:"{name(rd)}, f{rs1}";
355
+            X[rd]<=sext(F[rs1]);
356
+        }
357
+        FMV.D.X {
358
+            encoding: b1111001 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
359
+            args_disass:"f{rd}, {name(rs1)}";
360
+            F[rd] <= zext(X[rs1]);
361
+        }
362
+
297 363
     }
298
-}
364
+}
365
+    
366
+    

+ 162
- 51
riscv/gen_input/RV32F.core_desc View File

@@ -30,10 +30,13 @@ InsructionSet RV32F extends RV32IBase{
30 30
             encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
31 31
             args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
32 32
             //F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
33
-            val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
34 33
             if(FLEN==32)
35
-                F[rd] <= res;
34
+	            F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
36 35
             else { // NaN boxing
36
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
37
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
38
+	            val frs3[32] <= fdispatch_unbox_s(F[rs3]);
39
+                val res[32] <= fdispatch_fmadd_s(frs1, frs2, frs3, zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));            
37 40
                 val upper[FLEN] <= -1;
38 41
                 F[rd] <= (upper<<32) | zext(res, FLEN);
39 42
             }
@@ -44,10 +47,13 @@ InsructionSet RV32F extends RV32IBase{
44 47
             encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
45 48
             args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
46 49
             //F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
47
-            val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
48 50
             if(FLEN==32)
49
-                F[rd] <= res;
51
+	            F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
50 52
             else { // NaN boxing
53
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
54
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
55
+	            val frs3[32] <= fdispatch_unbox_s(F[rs3]);
56
+                val res[32] <= fdispatch_fmadd_s(frs1, frs2, frs3, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
51 57
                 val upper[FLEN] <= -1;
52 58
                 F[rd] <= (upper<<32) | zext(res, FLEN);
53 59
             }
@@ -58,10 +64,13 @@ InsructionSet RV32F extends RV32IBase{
58 64
             encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
59 65
             args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
60 66
             //F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
61
-            val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
62 67
             if(FLEN==32)
63
-                F[rd] <= res;
68
+                F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
64 69
             else { // NaN boxing
70
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
71
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
72
+	            val frs3[32] <= fdispatch_unbox_s(F[rs3]);
73
+                val res[32] <= fdispatch_fmadd_s(frs1, frs2, frs3, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
65 74
                 val upper[FLEN] <= -1;
66 75
                 F[rd] <= (upper<<32) | zext(res, FLEN);
67 76
             }
@@ -72,10 +81,13 @@ InsructionSet RV32F extends RV32IBase{
72 81
             encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
73 82
             args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
74 83
             //F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
75
-            val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
76 84
             if(FLEN==32)
77
-                F[rd] <= res;
85
+	            F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
78 86
             else { // NaN boxing
87
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
88
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
89
+	            val frs3[32] <= fdispatch_unbox_s(F[rs3]);
90
+                val res[32] <= fdispatch_fmadd_s(frs1, frs2, frs3, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
79 91
                 val upper[FLEN] <= -1;
80 92
                 F[rd] <= (upper<<32) | zext(res, FLEN);
81 93
             }
@@ -86,10 +98,12 @@ InsructionSet RV32F extends RV32IBase{
86 98
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
87 99
             args_disass:"f{rd}, f{rs1}, f{rs2}";
88 100
             // F[rd]f <= F[rs1]f + F[rs2]f;
89
-            val res[32] <= fdispatch_fadd_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
90 101
             if(FLEN==32)
91
-                F[rd] <= res;
102
+	            F[rd] <= fdispatch_fadd_s(F[rs1], F[rs2], choose(rm<7, rm{8}, FCSR{8}));
92 103
             else { // NaN boxing
104
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
105
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
106
+                val res[32] <= fdispatch_fadd_s(frs1, frs2, choose(rm<7, rm{8}, FCSR{8}));
93 107
                 val upper[FLEN] <= -1;
94 108
                 F[rd] <= (upper<<32) | zext(res, FLEN);
95 109
             }
@@ -100,10 +114,12 @@ InsructionSet RV32F extends RV32IBase{
100 114
             encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
101 115
             args_disass:"f{rd}, f{rs1}, f{rs2}";
102 116
             // F[rd]f <= F[rs1]f - F[rs2]f;
103
-            val res[32] <= fdispatch_fsub_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
104 117
             if(FLEN==32)
105
-                F[rd] <= res;
118
+	            F[rd] <= fdispatch_fsub_s(F[rs1], F[rs2], choose(rm<7, rm{8}, FCSR{8}));
106 119
             else { // NaN boxing
120
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
121
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
122
+                val res[32] <= fdispatch_fsub_s(frs1, frs2, choose(rm<7, rm{8}, FCSR{8}));
107 123
                 val upper[FLEN] <= -1;
108 124
                 F[rd] <= (upper<<32) | zext(res, FLEN);
109 125
             }
@@ -114,10 +130,12 @@ InsructionSet RV32F extends RV32IBase{
114 130
             encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
115 131
             args_disass:"f{rd}, f{rs1}, f{rs2}";
116 132
             // F[rd]f <= F[rs1]f * F[rs2]f;
117
-            val res[32] <= fdispatch_fmul_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
118 133
             if(FLEN==32)
119
-                F[rd] <= res;
134
+	            F[rd] <= fdispatch_fmul_s(F[rs1], F[rs2], choose(rm<7, rm{8}, FCSR{8}));
120 135
             else { // NaN boxing
136
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
137
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
138
+                val res[32] <= fdispatch_fmul_s(frs1, frs2, choose(rm<7, rm{8}, FCSR{8}));
121 139
                 val upper[FLEN] <= -1;
122 140
                 F[rd] <= (upper<<32) | zext(res, FLEN);
123 141
             }
@@ -128,10 +146,12 @@ InsructionSet RV32F extends RV32IBase{
128 146
             encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
129 147
             args_disass:"f{rd}, f{rs1}, f{rs2}";
130 148
             // F[rd]f <= F[rs1]f / F[rs2]f;
131
-            val res[32] <= fdispatch_fdiv_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
132 149
             if(FLEN==32)
133
-                F[rd] <= res;
150
+	            F[rd] <= fdispatch_fdiv_s(F[rs1], F[rs2], choose(rm<7, rm{8}, FCSR{8}));
134 151
             else { // NaN boxing
152
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
153
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
154
+                val res[32] <= fdispatch_fdiv_s(frs1, frs2, choose(rm<7, rm{8}, FCSR{8}));
135 155
                 val upper[FLEN] <= -1;
136 156
                 F[rd] <= (upper<<32) | zext(res, FLEN);
137 157
             }
@@ -142,10 +162,11 @@ InsructionSet RV32F extends RV32IBase{
142 162
             encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
143 163
             args_disass:"f{rd}, f{rs1}";
144 164
             //F[rd]f<=sqrt(F[rs1]f);
145
-            val res[32] <= fdispatch_fsqrt_s(F[rs1]{32}, choose(rm<7, rm{8}, FCSR{8}));
146 165
             if(FLEN==32)
147
-                F[rd] <= res;
166
+	            F[rd] <= fdispatch_fsqrt_s(F[rs1], choose(rm<7, rm{8}, FCSR{8}));
148 167
             else { // NaN boxing
168
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
169
+                val res[32] <= fdispatch_fsqrt_s(frs1, choose(rm<7, rm{8}, FCSR{8}));
149 170
                 val upper[FLEN] <= -1;
150 171
                 F[rd] <= (upper<<32) | zext(res, FLEN);
151 172
             }
@@ -155,10 +176,12 @@ InsructionSet RV32F extends RV32IBase{
155 176
         FSGNJ.S {
156 177
             encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
157 178
             args_disass:"f{rd}, f{rs1}, f{rs2}";
158
-            val res[32] <= (F[rs1]{32} & 0x7fffffff) | (F[rs2]{32} & 0x80000000);
159 179
             if(FLEN==32)
160
-                F[rd] <= res;
180
+	            F[rd] <= (F[rs1] & 0x7fffffff) | (F[rs2] & 0x80000000);
161 181
             else { // NaN boxing
182
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
183
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
184
+                val res[32] <= (frs1 & 0x7fffffff) | (frs2 & 0x80000000);
162 185
                 val upper[FLEN] <= -1;
163 186
                 F[rd] <= (upper<<32) | zext(res, FLEN);
164 187
             }
@@ -166,10 +189,12 @@ InsructionSet RV32F extends RV32IBase{
166 189
         FSGNJN.S {
167 190
             encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
168 191
             args_disass:"f{rd}, f{rs1}, f{rs2}";
169
-            val res[32] <= (F[rs1]{32} & 0x7fffffff) | (~F[rs2]{32} & 0x80000000);
170 192
             if(FLEN==32)
171
-                F[rd] <= res;
193
+	            F[rd] <= (F[rs1] & 0x7fffffff) | (~F[rs2] & 0x80000000);
172 194
             else { // NaN boxing
195
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
196
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
197
+                val res[32] <= (frs1 & 0x7fffffff) | (~frs2 & 0x80000000);
173 198
                 val upper[FLEN] <= -1;
174 199
                 F[rd] <= (upper<<32) | zext(res, FLEN);
175 200
             }
@@ -177,10 +202,12 @@ InsructionSet RV32F extends RV32IBase{
177 202
         FSGNJX.S {
178 203
             encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
179 204
             args_disass:"f{rd}, f{rs1}, f{rs2}";
180
-            val res[32] <= F[rs1]{32} ^ (F[rs2]{32} & 0x80000000);
181 205
             if(FLEN==32)
182
-                F[rd] <= res;
206
+	            F[rd] <= F[rs1] ^ (F[rs2] & 0x80000000);
183 207
             else { // NaN boxing
208
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
209
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
210
+                val res[32] <= frs1 ^ (frs2 & 0x80000000);
184 211
                 val upper[FLEN] <= -1;
185 212
                 F[rd] <= (upper<<32) | zext(res, FLEN);
186 213
             }
@@ -189,10 +216,12 @@ InsructionSet RV32F extends RV32IBase{
189 216
             encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
190 217
             args_disass:"f{rd}, f{rs1}, f{rs2}";
191 218
             //F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
192
-            val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
193 219
             if(FLEN==32)
194
-                F[rd] <= res;
220
+	            F[rd] <= fdispatch_fsel_s(F[rs1], F[rs2], zext(0, 32));
195 221
             else { // NaN boxing
222
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
223
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
224
+                val res[32] <= fdispatch_fsel_s(frs1, frs2, zext(0, 32));
196 225
                 val upper[FLEN] <= -1;
197 226
                 F[rd] <= (upper<<32) | zext(res, FLEN);
198 227
             }
@@ -203,10 +232,12 @@ InsructionSet RV32F extends RV32IBase{
203 232
             encoding: b0010100 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
204 233
             args_disass:"f{rd}, f{rs1}, f{rs2}";
205 234
             //F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
206
-            val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
207 235
             if(FLEN==32)
208
-                F[rd] <= res;
236
+	            F[rd] <= fdispatch_fsel_s(F[rs1], F[rs2], zext(1, 32));
209 237
             else { // NaN boxing
238
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
239
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
240
+                val res[32] <= fdispatch_fsel_s(frs1, frs2, zext(1, 32));
210 241
                 val upper[FLEN] <= -1;
211 242
                 F[rd] <= (upper<<32) | zext(res, FLEN);
212 243
             }
@@ -215,80 +246,160 @@ InsructionSet RV32F extends RV32IBase{
215 246
         }
216 247
         FCVT.W.S {
217 248
             encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
218
-            args_disass:"x{rd}, f{rs1}";
219
-            X[rd]<= sext(fdispatch_fcvt_s(F[rs1]{32}, zext(0, 32), rm{8}), XLEN);
249
+            args_disass:"{name(rd)}, f{rs1}";
250
+            if(FLEN==32)
251
+	            X[rd] <= sext(fdispatch_fcvt_s(F[rs1], zext(0, 32), rm{8}), XLEN);
252
+            else { // NaN boxing
253
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
254
+                X[rd]<= sext(fdispatch_fcvt_s(frs1, zext(0, 32), rm{8}), XLEN);
255
+            }
220 256
             val flags[32] <= fdispatch_fget_flags();
221 257
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
222 258
         }
223 259
         FCVT.WU.S {
224 260
             encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
225
-            args_disass:"x{rd}, f{rs1}";
226
-            X[rd]<= zext(fdispatch_fcvt_s(F[rs1]{32}, zext(1, 32), rm{8}), XLEN);
261
+            args_disass:"{name(rd)}, f{rs1}";
262
+            //FIXME: according to the spec it should be zero-extended not sign extended
263
+            if(FLEN==32)
264
+           		 X[rd]<= sext(fdispatch_fcvt_s(F[rs1], zext(1, 32), rm{8}), XLEN);
265
+            else { // NaN boxing
266
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
267
+                X[rd]<= sext(fdispatch_fcvt_s(frs1, zext(1, 32), rm{8}), XLEN);
268
+            }
227 269
             val flags[32] <= fdispatch_fget_flags();
228 270
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
229 271
         }
230 272
         FEQ.S {
231 273
             encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
232
-            args_disass:"x{rd}, f{rs1}, f{rs2}";
233
-            X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
274
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}";
275
+            if(FLEN==32)
276
+	            X[rd]<=zext(fdispatch_fcmp_s(F[rs1], F[rs2], zext(0, 32)));
277
+	        else {
278
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
279
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
280
+	            X[rd]<=zext(fdispatch_fcmp_s(frs1, frs2, zext(0, 32)));	        
281
+	        }
234 282
             val flags[32] <= fdispatch_fget_flags();
235 283
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
236 284
         }
237 285
         FLT.S {
238 286
             encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
239
-            args_disass:"x{rd}, f{rs1}, f{rs2}";
287
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}";
288
+            if(FLEN==32)
289
+            	X[rd]<=zext(fdispatch_fcmp_s(F[rs1], F[rs2], zext(2, 32)));
290
+	        else {
291
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
292
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
293
+            	X[rd]<=zext(fdispatch_fcmp_s(frs1, frs2, zext(2, 32)));
294
+            }
240 295
             X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32));
241 296
             val flags[32] <= fdispatch_fget_flags();
242 297
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
243 298
         }
244 299
         FLE.S {
245 300
             encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
246
-            args_disass:"x{rd}, f{rs1}, f{rs2}";
247
-            X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
301
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}";
302
+            if(FLEN==32)
303
+	            X[rd]<=zext(fdispatch_fcmp_s(F[rs1], F[rs2], zext(1, 32)));
304
+	        else {
305
+	            val frs1[32] <= fdispatch_unbox_s(F[rs1]);
306
+	            val frs2[32] <= fdispatch_unbox_s(F[rs2]);
307
+	            X[rd]<=zext(fdispatch_fcmp_s(frs1, frs2, zext(1, 32)));
308
+	        }
248 309
             val flags[32] <= fdispatch_fget_flags();
249 310
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
250 311
         }
251 312
         FCLASS.S {
252 313
             encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
253
-            args_disass:"x{rd}, f{rs1}";
254
-            X[rd]<=fdispatch_fclass_s(F[rs1]{32});
314
+            args_disass:"{name(rd)}, f{rs1}";
315
+            X[rd]<=fdispatch_fclass_s(fdispatch_unbox_s(F[rs1]));
255 316
         }
256 317
         FCVT.S.W {
257 318
             encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
258
-            args_disass:"f{rd}, x{rs1}";
259
-            val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
319
+            args_disass:"f{rd}, {name(rs1)}";
260 320
             if(FLEN==32)
261
-                F[rd] <= res;
321
+	            F[rd]  <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
262 322
             else { // NaN boxing
323
+                val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
263 324
                 val upper[FLEN] <= -1;
264 325
                 F[rd] <= (upper<<32) | zext(res, FLEN);
265 326
             }
266 327
         }
267 328
         FCVT.S.WU {
268 329
             encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
269
-            args_disass:"f{rd}, x{rs1}";
270
-            val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
330
+            args_disass:"f{rd}, {name(rs1)}";
271 331
             if(FLEN==32)
272
-                F[rd] <= res;
332
+    	        F[rd]  <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
273 333
             else { // NaN boxing
274
-                val upper[FLEN] <= -1;
334
+                val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
335
+    	        val upper[FLEN] <= -1;
275 336
                 F[rd] <= (upper<<32) | zext(res, FLEN);
276 337
             }
277 338
         }
278 339
         FMV.X.W {
279 340
             encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
280
-            args_disass:"x{rd}, f{rs1}";
341
+            args_disass:"{name(rd)}, f{rs1}";
281 342
             X[rd]<=sext(F[rs1]{32});
282 343
         }
283 344
         FMV.W.X {
284 345
             encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
285
-            args_disass:"f{rd}, x{rs1}";
346
+            args_disass:"f{rd}, {name(rs1)}";
286 347
             if(FLEN==32)
287
-                F[rd] <= X[rs1];
348
+                F[rd] <= X[rs1]{32};
288 349
             else { // NaN boxing
289 350
                 val upper[FLEN] <= -1;
290
-                F[rd] <= (upper<<32) | zext(X[rs1], FLEN);
351
+                F[rd] <= (upper<<32) | zext(X[rs1]{32}, FLEN);
291 352
             }
292 353
         }
293 354
     }
294
-}
355
+}
356
+
357
+InsructionSet RV64F extends RV32F{
358
+    constants {
359
+        FLEN, FFLAG_MASK := 0x1f
360
+    } 
361
+    registers {
362
+        [31:0]    F[FLEN],  FCSR[32]
363
+    }    
364
+    instructions{
365
+        FCVT.L.S { // fp to 64bit signed integer
366
+            encoding: b1100000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
367
+            args_disass:"x{rd}, f{rs1}";
368
+            val res[64] <= fdispatch_fcvt_32_64(fdispatch_unbox_s(F[rs1]), zext(0, 32), rm{8});
369
+            X[rd]<= sext(res);
370
+            val flags[32] <= fdispatch_fget_flags();
371
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
372
+        }
373
+        FCVT.LU.S { // fp to 64bit unsigned integer
374
+            encoding: b1100000 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
375
+            args_disass:"x{rd}, f{rs1}";
376
+            val res[64] <= fdispatch_fcvt_32_64(fdispatch_unbox_s(F[rs1]), zext(1, 32), rm{8});
377
+            X[rd]<= zext(res);
378
+            val flags[32] <= fdispatch_fget_flags();
379
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
380
+        }
381
+        FCVT.S.L { // 64bit signed int to to fp 
382
+            encoding: b1101000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
383
+            args_disass:"f{rd}, x{rs1}";
384
+            val res[32] <= fdispatch_fcvt_64_32(X[rs1], zext(2, 32));
385
+            if(FLEN==32)
386
+                F[rd] <= res;
387
+            else { // NaN boxing
388
+                val upper[FLEN] <= -1;
389
+                F[rd] <= (upper<<32) | zext(res, FLEN);
390
+            }
391
+        }
392
+        FCVT.S.LU { // 64bit unsigned int to to fp 
393
+            encoding: b1101000 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
394
+            args_disass:"f{rd}, x{rs1}";
395
+            val res[32] <=fdispatch_fcvt_64_32(X[rs1], zext(3,32));
396
+            if(FLEN==32)
397
+                F[rd] <= res;
398
+            else { // NaN boxing
399
+                val upper[FLEN] <= -1;
400
+                F[rd] <= (upper<<32) | zext(res, FLEN);
401
+            }
402
+        }
403
+	}
404
+}
405
+    

+ 1
- 1
riscv/gen_input/RV32IBase.core_desc View File

@@ -8,7 +8,7 @@ InsructionSet RV32IBase {
8 8
     }
9 9
     
10 10
     address_spaces { 
11
-        MEM[8], CSR[XLEN], FENCE[XLEN]
11
+        MEM[8], CSR[XLEN], FENCE[XLEN], RES[8]
12 12
     }
13 13
                 
14 14
     registers { 

+ 14
- 16
riscv/gen_input/RV32M.core_desc View File

@@ -43,12 +43,11 @@ InsructionSet RV32M extends RV32IBase {
43 43
             if(rd != 0){
44 44
                 if(X[rs2]!=0){
45 45
                     val M1[XLEN] <= -1;
46
-                    val MMIN[XLEN] <= -1<<(XLEN-1);
47
-                    if(X[rs1]s==MMIN's)
48
-                        if(X[rs2]s==M1's)
49
-                            X[rd]<=MMIN;
50
-                        else
51
-                            X[rd] <= X[rs1]s / X[rs2]s;
46
+                    val XLM1[8] <= XLEN-1;
47
+                    val ONE[XLEN] <= 1;
48
+                    val MMIN[XLEN] <= ONE<<XLM1;
49
+                    if(X[rs1]==MMIN && X[rs2]==M1)
50
+                        X[rd] <= MMIN;
52 51
                     else
53 52
                         X[rd] <= X[rs1]s / X[rs2]s;
54 53
                 }else 
@@ -60,7 +59,7 @@ InsructionSet RV32M extends RV32IBase {
60 59
             args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
61 60
             if(rd != 0){
62 61
                 if(X[rs2]!=0)
63
-                    X[rd] <= zext(X[rs1], 32) / zext(X[rs2], 32);
62
+                    X[rd] <= X[rs1] / X[rs2];
64 63
                 else 
65 64
                     X[rd] <= -1;
66 65
             }
@@ -70,15 +69,14 @@ InsructionSet RV32M extends RV32IBase {
70 69
             args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
71 70
             if(rd != 0){
72 71
                 if(X[rs2]!=0) {
73
-                    val M1[XLEN] <= -1;
74
-                    val MMIN[XLEN] <= -1<<(XLEN-1);
75
-                    if(X[rs1]s==MMIN's)
76
-                        if(X[rs2]s==M1's)
77
-                            X[rd] <= 0;
78
-                        else
79
-                            X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
72
+                    val M1[XLEN] <= -1; // constant -1 
73
+                    val XLM1[32] <= XLEN-1;
74
+                    val ONE[XLEN] <= 1;
75
+                    val MMIN[XLEN] <= ONE<<XLM1; // -2^(XLEN-1)
76
+                    if(X[rs1]==MMIN && X[rs2]==M1)
77
+                        X[rd] <= 0;
80 78
                     else
81
-                        X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
79
+                        X[rd] <= X[rs1]'s % X[rs2]'s;
82 80
                 } else 
83 81
                     X[rd] <= X[rs1];
84 82
             }
@@ -88,7 +86,7 @@ InsructionSet RV32M extends RV32IBase {
88 86
             args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
89 87
             if(rd != 0){
90 88
                 if(X[rs2]!=0)
91
-                    X[rd] <= zext(X[rs1], 32) % zext(X[rs2], 32);
89
+                    X[rd] <= X[rs1] % X[rs2];
92 90
                 else 
93 91
                     X[rd] <= X[rs1];
94 92
             }

+ 9
- 14
riscv/gen_input/RV64A.core_desc View File

@@ -1,12 +1,7 @@
1 1
 import "RV64IBase.core_desc"
2
-import "RV32A.core_desc"
3 2
 
4 3
 InsructionSet RV64A extends RV64IBase {
5 4
      
6
-    address_spaces { 
7
-        RES[8]
8
-    }
9
-    
10 5
     instructions{
11 6
         LR.D {
12 7
             encoding: b00010 | aq[0:0] | rl[0:0]  | b00000 | rs1[4:0] | b011 | rd[4:0] | b0101111;
@@ -76,10 +71,10 @@ InsructionSet RV64A extends RV64IBase {
76 71
             encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
77 72
             args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
78 73
             val offs[XLEN] <= X[rs1];
79
-            val res[XLEN] <= sext(MEM[offs]{64});
80
-            if(rd!=0) X[rd] <= res;
81
-            val res2[XLEN] <= choose(res s > X[rs2]s, X[rs2], res);            
82
-            MEM[offs]{64} <= res;            
74
+            val res1[XLEN] <= sext(MEM[offs]{64});
75
+            if(rd!=0) X[rd] <= res1;
76
+            val res2[XLEN] <= choose(res1's > X[rs2]s, X[rs2], res1);
77
+            MEM[offs]{64} <= res2;
83 78
         }
84 79
         AMOMAX.D{
85 80
             encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
@@ -94,7 +89,7 @@ InsructionSet RV64A extends RV64IBase {
94 89
             encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
95 90
             args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
96 91
             val offs[XLEN] <= X[rs1];
97
-            val res[XLEN] <= zext(MEM[offs]{64});
92
+            val res[XLEN] <= sext(MEM[offs]{64});
98 93
             if(rd!=0) X[rd] <= res;
99 94
             val res2[XLEN] <= choose(res > X[rs2], X[rs2], res);            
100 95
             MEM[offs]{64} <= res2;            
@@ -103,10 +98,10 @@ InsructionSet RV64A extends RV64IBase {
103 98
             encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
104 99
             args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
105 100
             val offs[XLEN] <= X[rs1];
106
-            val res[XLEN] <= zext(MEM[offs]{64});
107
-            if(rd!=0) X[rd] <= res;
108
-            val res2[XLEN] <= choose(res < X[rs2], X[rs2], res);            
109
-            MEM[offs]{64} <= res2;            
101
+            val res1[XLEN] <= sext(MEM[offs]{64});
102
+            if(rd!=0) X[rd] <= res1;
103
+            val res2[XLEN] <= choose(res1 < X[rs2], X[rs2], res1);
104
+            MEM[offs]{64} <= res2;
110 105
         }
111 106
     }
112 107
 }

+ 30
- 6
riscv/gen_input/RV64M.core_desc View File

@@ -6,35 +6,59 @@ InsructionSet RV64M extends RV64IBase {
6 6
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
7 7
             args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
8 8
             if(rd != 0){
9
-                X[rd]<= X[rs1] * X[rs2];
9
+                X[rd]<= sext(X[rs1]{32} * X[rs2]{32});
10 10
             }
11 11
         }
12 12
         DIVW {
13 13
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0111011;
14 14
             args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
15 15
             if(rd != 0){
16
-                X[rd] <= X[rs1]s / X[rs2]s;
16
+                if(X[rs2]!=0){
17
+                    val M1[32] <= -1;
18
+                    val ONE[32] <= 1;
19
+                    val MMIN[32] <= ONE<<31;
20
+                    if(X[rs1]{32}==MMIN && X[rs2]{32}==M1)
21
+                        X[rd] <= -1<<31;
22
+                    else
23
+                        X[rd] <= sext(X[rs1]{32}s / X[rs2]{32}s);
24
+                }else 
25
+                    X[rd] <= -1;
17 26
             }
18 27
         }
19 28
         DIVUW {
20 29
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
21 30
             args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
22 31
             if(rd != 0){
23
-                X[rd] <= X[rs1] / X[rs2];
24
-            }
32
+	            if(X[rs2]{32}!=0)
33
+	                X[rd] <= sext(X[rs1]{32} / X[rs2]{32});
34
+	            else 
35
+	                X[rd] <= -1;
36
+	        }
25 37
         }
26 38
         REMW {
27 39
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0111011;
28 40
             args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
29 41
             if(rd != 0){
30
-                X[rd] <= X[rs1]s % X[rs2]s;
42
+                if(X[rs2]!=0) {
43
+                    val M1[32] <= -1; // constant -1 
44
+                    val ONE[32] <= 1;
45
+                    val MMIN[32] <= ONE<<31; // -2^(XLEN-1)
46
+                    if(X[rs1]{32}==MMIN && X[rs2]==M1)
47
+                        X[rd] <= 0;
48
+                    else
49
+                        X[rd] <= sext(X[rs1]{32}s % X[rs2]{32}s);
50
+                } else 
51
+                    X[rd] <= sext(X[rs1]{32});
31 52
             }
32 53
         }
33 54
         REMUW {
34 55
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0111011;
35 56
             args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
36 57
             if(rd != 0){
37
-                X[rd] <= X[rs1] % X[rs2];
58
+                if(X[rs2]{32}!=0)
59
+                    X[rd] <= sext(X[rs1]{32} % X[rs2]{32});
60
+                else 
61
+                    X[rd] <= sext(X[rs1]{32});
38 62
             }
39 63
         }
40 64
     }

+ 16
- 3
riscv/gen_input/minres_rv.core_desc View File

@@ -5,7 +5,7 @@ import "RV32C.core_desc"
5 5
 import "RV32F.core_desc"
6 6
 import "RV32D.core_desc"
7 7
 import "RV64IBase.core_desc"
8
-//import "RV64M.core_desc"
8
+import "RV64M.core_desc"
9 9
 import "RV64A.core_desc"
10 10
 
11 11
 Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
@@ -33,15 +33,28 @@ Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32
33 33
     }
34 34
 }
35 35
 
36
+Core RV64I provides RV64IBase {
37
+    constants {
38
+        XLEN:=64;
39
+        PCLEN:=64;
40
+        // definitions for the architecture wrapper
41
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
42
+        MISA_VAL:=0b10000000000001000000000100000000;
43
+        PGSIZE := 0x1000; //1 << 12;
44
+        PGMASK := 0xfff; //PGSIZE-1
45
+    }
46
+}
36 47
 
37
-Core RV64IA provides RV64IBase, RV64A, RV32A {
48
+Core RV64GC provides RV64IC, RV64A, RV64M, RV32A, RV32M, RV64F, RV64D, RV32FC, RV32DC {
38 49
     constants {
39 50
         XLEN:=64;
51
+        FLEN:=64;
40 52
         PCLEN:=64;
41 53
         // definitions for the architecture wrapper
42 54
         //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
43
-        MISA_VAL:=0b10000000000001000000000100000001;
55
+        MISA_VAL:=0b01000000000101000001000100101101;
44 56
         PGSIZE := 0x1000; //1 << 12;
45 57
         PGMASK := 0xfff; //PGSIZE-1
46 58
     }
47 59
 }
60
+

+ 49
- 9
riscv/gen_input/templates/src-CORENAME.cpp.gtl View File

@@ -29,7 +29,45 @@
29 29
  * POSSIBILITY OF SUCH DAMAGE.
30 30
  *
31 31
  *******************************************************************************/
32
-
32
+ <% 
33
+import com.minres.coredsl.coreDsl.Register
34
+import com.minres.coredsl.coreDsl.RegisterFile
35
+import com.minres.coredsl.coreDsl.RegisterAlias
36
+def getOriginalName(reg){
37
+    if( reg.original instanceof RegisterFile) {
38
+    	if( reg.index != null ) {
39
+        	return reg.original.name+generator.generateHostCode(reg.index)
40
+        } else {
41
+        	return reg.original.name
42
+        }
43
+    } else if(reg.original instanceof Register){
44
+        return reg.original.name
45
+    }
46
+}
47
+def getRegisterNames(){
48
+	def regNames = []
49
+ 	allRegs.each { reg -> 
50
+		if( reg instanceof RegisterFile) {
51
+			(reg.range.right..reg.range.left).each{
52
+    			regNames+=reg.name.toLowerCase()+it
53
+            }
54
+        } else if(reg instanceof Register){
55
+    		regNames+=reg.name.toLowerCase()
56
+        }
57
+    }
58
+    return regNames
59
+}
60
+def getRegisterAliasNames(){
61
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
62
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
63
+		if( reg instanceof RegisterFile) {
64
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
65
+        } else if(reg instanceof Register){
66
+    		regMap[reg.name]?:reg.name.toLowerCase()
67
+        }
68
+ 	}.flatten()
69
+}
70
+%>
33 71
 #include "util/ities.h"
34 72
 #include <util/logging.h>
35 73
 
@@ -49,27 +87,29 @@ extern "C" {
49 87
 
50 88
 using namespace iss::arch;
51 89
 
52
-constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_sizes;
53
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offset;
90
+constexpr std::array<const char*, ${getRegisterNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_names;
91
+constexpr std::array<const char*, ${getRegisterAliasNames().size}>    iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_aliases;
92
+constexpr std::array<const uint32_t, ${regSizes.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
93
+constexpr std::array<const uint32_t, ${regOffsets.size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
54 94
 
55 95
 ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
56 96
     reg.icount = 0;
57
-    reg.machine_state = 0x3;
58 97
 }
59 98
 
60 99
 ${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
61
-}
62 100
 
63 101
 void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
64
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i)
65
-    	set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
102
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
66 103
     reg.PC=address;
67 104
     reg.NEXT_PC=reg.PC;
68 105
     reg.trap_state=0;
69
-    reg.machine_state=0x3;
106
+    reg.machine_state=0x0;
107
+    reg.icount=0;
70 108
 }
71 109
 
72
-uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() { return reinterpret_cast<uint8_t*>(&reg); }
110
+uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
111
+	return reinterpret_cast<uint8_t*>(&reg);
112
+}
73 113
 
74 114
 ${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
75 115
     return phys_addr_t(pc); // change logical address to physical address

+ 13
- 16
riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl View File

@@ -46,7 +46,7 @@
46 46
 namespace iss {
47 47
 namespace vm {
48 48
 namespace fp_impl {
49
-void add_fp_functions_2_module(llvm::Module *, unsigned);
49
+void add_fp_functions_2_module(llvm::Module *, unsigned, unsigned);
50 50
 }
51 51
 }
52 52
 
@@ -88,7 +88,7 @@ protected:
88 88
 
89 89
     void setup_module(Module* m) override {
90 90
         super::setup_module(m);
91
-        iss::vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE);
91
+        iss::vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE, traits<ARCH>::XLEN);
92 92
     }
93 93
 
94 94
     inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
@@ -241,24 +241,21 @@ template <typename ARCH>
241 241
 std::tuple<continuation_e, BasicBlock *>
242 242
 vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
243 243
     // we fetch at max 4 byte, alignment is 2
244
+    enum {TRAP_ID=1<<16};
244 245
     code_word_t insn = 0;
245 246
     const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
246 247
     phys_addr_t paddr(pc);
247
-    try {
248
-        auto *const data = (uint8_t *)&insn;
249
-        paddr = this->core.v2p(pc);
250
-        if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
251
-            auto res = this->core.read(paddr, 2, data);
252
-            if (res != iss::Ok) throw trap_access(1, pc.val);
253
-            if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
254
-                res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
255
-            }
256
-        } else {
257
-            auto res = this->core.read(paddr, 4, data);
258
-            if (res != iss::Ok) throw trap_access(1, pc.val);
248
+    auto *const data = (uint8_t *)&insn;
249
+    paddr = this->core.v2p(pc);
250
+    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
251
+        auto res = this->core.read(paddr, 2, data);
252
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
253
+        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
254
+            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
259 255
         }
260
-    } catch (trap_access &ta) {
261
-        throw trap_access(ta.id, pc.val);
256
+    } else {
257
+        auto res = this->core.read(paddr, 4, data);
258
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
262 259
     }
263 260
     if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
264 261
     // curr pc on stack

+ 316
- 0
riscv/incl/iss/arch/rv64gc.h View File

@@ -0,0 +1,316 @@
1
+/*******************************************************************************
2
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
3
+ * All rights reserved.
4
+ *
5
+ * Redistribution and use in source and binary forms, with or without
6
+ * modification, are permitted provided that the following conditions are met:
7
+ *
8
+ * 1. Redistributions of source code must retain the above copyright notice,
9
+ *    this list of conditions and the following disclaimer.
10
+ *
11
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
12
+ *    this list of conditions and the following disclaimer in the documentation
13
+ *    and/or other materials provided with the distribution.
14
+ *
15
+ * 3. Neither the name of the copyright holder nor the names of its contributors
16
+ *    may be used to endorse or promote products derived from this software
17
+ *    without specific prior written permission.
18
+ *
19
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+ * POSSIBILITY OF SUCH DAMAGE.
30
+ *
31
+ *******************************************************************************/
32
+
33
+
34
+#ifndef _RV64GC_H_
35
+#define _RV64GC_H_
36
+
37
+#include <array>
38
+#include <iss/arch/traits.h>
39
+#include <iss/arch_if.h>
40
+#include <iss/vm_if.h>
41
+
42
+namespace iss {
43
+namespace arch {
44
+
45
+struct rv64gc;
46
+
47
+template <> struct traits<rv64gc> {
48
+
49
+	constexpr static char const* const core_type = "RV64GC";
50
+    
51
+  	static constexpr std::array<const char*, 66> reg_names{
52
+ 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}};
53
+ 
54
+  	static constexpr std::array<const char*, 66> reg_aliases{
55
+ 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}};
56
+
57
+    enum constants {XLEN=64, FLEN=64, PCLEN=64, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
58
+
59
+    constexpr static unsigned FP_REGS_SIZE = 64;
60
+
61
+    enum reg_e {
62
+        X0,
63
+        X1,
64
+        X2,
65
+        X3,
66
+        X4,
67
+        X5,
68
+        X6,
69
+        X7,
70
+        X8,
71
+        X9,
72
+        X10,
73
+        X11,
74
+        X12,
75
+        X13,
76
+        X14,
77
+        X15,
78
+        X16,
79
+        X17,
80
+        X18,
81
+        X19,
82
+        X20,
83
+        X21,
84
+        X22,
85
+        X23,
86
+        X24,
87
+        X25,
88
+        X26,
89
+        X27,
90
+        X28,
91
+        X29,
92
+        X30,
93
+        X31,
94
+        PC,
95
+        F0,
96
+        F1,
97
+        F2,
98
+        F3,
99
+        F4,
100
+        F5,
101
+        F6,
102
+        F7,
103
+        F8,
104
+        F9,
105
+        F10,
106
+        F11,
107
+        F12,
108
+        F13,
109
+        F14,
110
+        F15,
111
+        F16,
112
+        F17,
113
+        F18,
114
+        F19,
115
+        F20,
116
+        F21,
117
+        F22,
118
+        F23,
119
+        F24,
120
+        F25,
121
+        F26,
122
+        F27,
123
+        F28,
124
+        F29,
125
+        F30,
126
+        F31,
127
+        FCSR,
128
+        NUM_REGS,
129
+        NEXT_PC=NUM_REGS,
130
+        TRAP_STATE,
131
+        PENDING_TRAP,
132
+        MACHINE_STATE,
133
+        LAST_BRANCH,
134
+        ICOUNT,
135
+        ZERO = X0,
136
+        RA = X1,
137
+        SP = X2,
138
+        GP = X3,
139
+        TP = X4,
140
+        T0 = X5,
141
+        T1 = X6,
142
+        T2 = X7,
143
+        S0 = X8,
144
+        S1 = X9,
145
+        A0 = X10,
146
+        A1 = X11,
147
+        A2 = X12,
148
+        A3 = X13,
149
+        A4 = X14,
150
+        A5 = X15,
151
+        A6 = X16,
152
+        A7 = X17,
153
+        S2 = X18,
154
+        S3 = X19,
155
+        S4 = X20,
156
+        S5 = X21,
157
+        S6 = X22,
158
+        S7 = X23,
159
+        S8 = X24,
160
+        S9 = X25,
161
+        S10 = X26,
162
+        S11 = X27,
163
+        T3 = X28,
164
+        T4 = X29,
165
+        T5 = X30,
166
+        T6 = X31
167
+    };
168
+
169
+    using reg_t = uint64_t;
170
+
171
+    using addr_t = uint64_t;
172
+
173
+    using code_word_t = uint64_t; //TODO: check removal
174
+
175
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
176
+
177
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
178
+
179
+ 	static constexpr std::array<const uint32_t, 72> reg_bit_widths{
180
+ 		{64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,64,32,32,32,32,64}};
181
+
182
+    static constexpr std::array<const uint32_t, 73> reg_byte_offsets{
183
+    	{0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,280,288,296,304,312,320,328,336,344,352,360,368,376,384,392,400,408,416,424,432,440,448,456,464,472,480,488,496,504,512,520,528,536,540,544,548,552,560}};
184
+
185
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
186
+
187
+    enum sreg_flag_e { FLAGS };
188
+
189
+    enum mem_type_e { MEM, CSR, FENCE, RES };
190
+};
191
+
192
+struct rv64gc: public arch_if {
193
+
194
+    using virt_addr_t = typename traits<rv64gc>::virt_addr_t;
195
+    using phys_addr_t = typename traits<rv64gc>::phys_addr_t;
196
+    using reg_t =  typename traits<rv64gc>::reg_t;
197
+    using addr_t = typename traits<rv64gc>::addr_t;
198
+
199
+    rv64gc();
200
+    ~rv64gc();
201
+
202
+    void reset(uint64_t address=0) override;
203
+
204
+    uint8_t* get_regs_base_ptr() override;
205
+    /// deprecated
206
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
207
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
208
+    /// deprecated
209
+    bool get_flag(int flag) override {return false;}
210
+    void set_flag(int, bool value) override {};
211
+    /// deprecated
212
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
213
+
214
+    inline uint64_t get_icount() { return reg.icount; }
215
+
216
+    inline bool should_stop() { return interrupt_sim; }
217
+
218
+    inline phys_addr_t v2p(const iss::addr_t& addr){
219
+        if (addr.space != traits<rv64gc>::MEM || addr.type == iss::address_type::PHYSICAL ||
220
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
221
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<rv64gc>::addr_mask);
222
+        } else
223
+            return virt2phys(addr);
224
+    }
225
+
226
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
227
+
228
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
229
+
230
+    inline uint32_t get_last_branch() { return reg.last_branch; }
231
+
232
+protected:
233
+    struct RV64GC_regs {
234
+        uint64_t X0 = 0;
235
+        uint64_t X1 = 0;
236
+        uint64_t X2 = 0;
237
+        uint64_t X3 = 0;
238
+        uint64_t X4 = 0;
239
+        uint64_t X5 = 0;
240
+        uint64_t X6 = 0;
241
+        uint64_t X7 = 0;
242
+        uint64_t X8 = 0;
243
+        uint64_t X9 = 0;
244
+        uint64_t X10 = 0;
245
+        uint64_t X11 = 0;
246
+        uint64_t X12 = 0;
247
+        uint64_t X13 = 0;
248
+        uint64_t X14 = 0;
249
+        uint64_t X15 = 0;
250
+        uint64_t X16 = 0;
251
+        uint64_t X17 = 0;
252
+        uint64_t X18 = 0;
253
+        uint64_t X19 = 0;
254
+        uint64_t X20 = 0;
255
+        uint64_t X21 = 0;
256
+        uint64_t X22 = 0;
257
+        uint64_t X23 = 0;
258
+        uint64_t X24 = 0;
259
+        uint64_t X25 = 0;
260
+        uint64_t X26 = 0;
261
+        uint64_t X27 = 0;
262
+        uint64_t X28 = 0;
263
+        uint64_t X29 = 0;
264
+        uint64_t X30 = 0;
265
+        uint64_t X31 = 0;
266
+        uint64_t PC = 0;
267
+        uint64_t F0 = 0;
268
+        uint64_t F1 = 0;
269
+        uint64_t F2 = 0;
270
+        uint64_t F3 = 0;
271
+        uint64_t F4 = 0;
272
+        uint64_t F5 = 0;
273
+        uint64_t F6 = 0;
274
+        uint64_t F7 = 0;
275
+        uint64_t F8 = 0;
276
+        uint64_t F9 = 0;
277
+        uint64_t F10 = 0;
278
+        uint64_t F11 = 0;
279
+        uint64_t F12 = 0;
280
+        uint64_t F13 = 0;
281
+        uint64_t F14 = 0;
282
+        uint64_t F15 = 0;
283
+        uint64_t F16 = 0;
284
+        uint64_t F17 = 0;
285
+        uint64_t F18 = 0;
286
+        uint64_t F19 = 0;
287
+        uint64_t F20 = 0;
288
+        uint64_t F21 = 0;
289
+        uint64_t F22 = 0;
290
+        uint64_t F23 = 0;
291
+        uint64_t F24 = 0;
292
+        uint64_t F25 = 0;
293
+        uint64_t F26 = 0;
294
+        uint64_t F27 = 0;
295
+        uint64_t F28 = 0;
296
+        uint64_t F29 = 0;
297
+        uint64_t F30 = 0;
298
+        uint64_t F31 = 0;
299
+        uint32_t FCSR = 0;
300
+        uint64_t NEXT_PC = 0;
301
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
302
+        uint64_t icount = 0;
303
+    } reg;
304
+
305
+    std::array<address_type, 4> addr_mode;
306
+    
307
+    bool interrupt_sim=false;
308
+
309
+	uint32_t get_fcsr(){return reg.FCSR;}
310
+	void set_fcsr(uint32_t val){reg.FCSR = val;}		
311
+
312
+};
313
+
314
+}
315
+}            
316
+#endif /* _RV64GC_H_ */

riscv/incl/iss/arch/rv64ia.h → riscv/incl/iss/arch/rv64i.h View File

@@ -31,8 +31,8 @@
31 31
  *******************************************************************************/
32 32
 
33 33
 
34
-#ifndef _RV64IA_H_
35
-#define _RV64IA_H_
34
+#ifndef _RV64I_H_
35
+#define _RV64I_H_
36 36
 
37 37
 #include <array>
38 38
 #include <iss/arch/traits.h>
@@ -42,11 +42,11 @@
42 42
 namespace iss {
43 43
 namespace arch {
44 44
 
45
-struct rv64ia;
45
+struct rv64i;
46 46
 
47
-template <> struct traits<rv64ia> {
47
+template <> struct traits<rv64i> {
48 48
 
49
-	constexpr static char const* const core_type = "RV64IA";
49
+	constexpr static char const* const core_type = "RV64I";
50 50
     
51 51
   	static constexpr std::array<const char*, 33> reg_names{
52 52
  		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
@@ -54,7 +54,7 @@ template <> struct traits<rv64ia> {
54 54
   	static constexpr std::array<const char*, 33> reg_aliases{
55 55
  		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
56 56
 
57
-    enum constants {XLEN=64, PCLEN=64, MISA_VAL=0b10000000000001000000000100000001, PGSIZE=0x1000, PGMASK=0xfff};
57
+    enum constants {XLEN=64, PCLEN=64, MISA_VAL=0b10000000000001000000000100000000, PGSIZE=0x1000, PGMASK=0xfff};
58 58
 
59 59
     constexpr static unsigned FP_REGS_SIZE = 0;
60 60
 
@@ -156,15 +156,15 @@ template <> struct traits<rv64ia> {
156 156
     enum mem_type_e { MEM, CSR, FENCE, RES };
157 157
 };
158 158
 
159
-struct rv64ia: public arch_if {
159
+struct rv64i: public arch_if {
160 160
 
161
-    using virt_addr_t = typename traits<rv64ia>::virt_addr_t;
162
-    using phys_addr_t = typename traits<rv64ia>::phys_addr_t;
163
-    using reg_t =  typename traits<rv64ia>::reg_t;
164
-    using addr_t = typename traits<rv64ia>::addr_t;
161
+    using virt_addr_t = typename traits<rv64i>::virt_addr_t;
162
+    using phys_addr_t = typename traits<rv64i>::phys_addr_t;
163
+    using reg_t =  typename traits<rv64i>::reg_t;
164
+    using addr_t = typename traits<rv64i>::addr_t;
165 165
 
166
-    rv64ia();
167
-    ~rv64ia();
166
+    rv64i();
167
+    ~rv64i();
168 168
 
169 169
     void reset(uint64_t address=0) override;
170 170
 
@@ -183,9 +183,9 @@ struct rv64ia: public arch_if {
183 183
     inline bool should_stop() { return interrupt_sim; }
184 184
 
185 185
     inline phys_addr_t v2p(const iss::addr_t& addr){
186
-        if (addr.space != traits<rv64ia>::MEM || addr.type == iss::address_type::PHYSICAL ||
186
+        if (addr.space != traits<rv64i>::MEM || addr.type == iss::address_type::PHYSICAL ||
187 187
                 addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
188
-            return phys_addr_t(addr.access, addr.space, addr.val&traits<rv64ia>::addr_mask);
188
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<rv64i>::addr_mask);
189 189
         } else
190 190
             return virt2phys(addr);
191 191
     }
@@ -197,7 +197,7 @@ struct rv64ia: public arch_if {
197 197
     inline uint32_t get_last_branch() { return reg.last_branch; }
198 198
 
199 199
 protected:
200
-    struct RV64IA_regs {
200
+    struct RV64I_regs {
201 201
         uint64_t X0 = 0;
202 202
         uint64_t X1 = 0;
203 203
         uint64_t X2 = 0;
@@ -247,4 +247,4 @@ protected:
247 247
 
248 248
 }
249 249
 }            
250
-#endif /* _RV64IA_H_ */
250
+#endif /* _RV64I_H_ */

+ 21
- 12
riscv/src/CMakeLists.txt View File

@@ -4,22 +4,16 @@ set(LIB_HEADERS ${RiscVSCHeaders} )
4 4
 set(LIB_SOURCES 
5 5
 	iss/rv32gc.cpp
6 6
 	iss/rv32imac.cpp
7
-	iss/rv64ia.cpp
7
+	iss/rv64i.cpp
8
+	iss/rv64gc.cpp
8 9
 	internal/fp_functions.cpp
9 10
 	internal/vm_rv32gc.cpp
10 11
 	internal/vm_rv32imac.cpp
11
-	internal/vm_rv64ia.cpp
12
+	internal/vm_rv64i.cpp
13
+	internal/vm_rv64gc.cpp
12 14
     plugin/instruction_count.cpp
13 15
     plugin/cycle_estimate.cpp)
14 16
 
15
-if(SystemC_FOUND)
16
-	set(LIB_SOURCES ${LIB_SOURCES} sysc/core_complex.cpp)
17
-endif()
18
-
19
-set(APP_HEADERS )
20
-
21
-set(APP_SOURCES main.cpp)
22
-
23 17
 # Define two variables in order not to repeat ourselves.
24 18
 set(LIBRARY_NAME riscv)
25 19
 
@@ -31,8 +25,11 @@ set_target_properties(${LIBRARY_NAME} PROPERTIES
31 25
   FRAMEWORK FALSE
32 26
   PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
33 27
 )
28
+#set_property(TARGET ${LIBRARY_NAME} PROPERTY POSITION_INDEPENDENT_CODE ON)
34 29
 
35 30
 if(SystemC_FOUND)
31
+	set(SC_LIBRARY_NAME riscv_sc)
32
+	add_library(${SC_LIBRARY_NAME} SHARED sysc/core_complex.cpp)
36 33
 	add_definitions(-DWITH_SYSTEMC) 
37 34
 	include_directories(${SystemC_INCLUDE_DIRS})
38 35
 	
@@ -42,18 +39,30 @@ if(SystemC_FOUND)
42 39
 	    add_definitions(-DWITH_SCV)
43 40
 	    include_directories(${SCV_INCLUDE_DIRS})
44 41
 	endif()
42
+	set_target_properties(${SC_LIBRARY_NAME} PROPERTIES
43
+	  VERSION ${VERSION}  # ${VERSION} was defined in the main CMakeLists.
44
+	  FRAMEWORK FALSE
45
+	  PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
46
+	)
47
+	target_link_libraries(${SC_LIBRARY_NAME} ${LIBRARY_NAME})
48
+	target_link_libraries(${SC_LIBRARY_NAME} dbt-core)
49
+	target_link_libraries(${SC_LIBRARY_NAME} softfloat)
50
+	target_link_libraries(${SC_LIBRARY_NAME} sc-components)
51
+	target_link_libraries(${SC_LIBRARY_NAME} external)
52
+	target_link_libraries(${SC_LIBRARY_NAME} ${llvm_libs})
53
+	target_link_libraries(${SC_LIBRARY_NAME} ${Boost_LIBRARIES} )
45 54
 endif()
46 55
 
47 56
 # This is a make target, so you can do a "make riscv-sc"
48 57
 set(APPLICATION_NAME riscv-sim)
49 58
 
50
-add_executable(${APPLICATION_NAME} ${APP_SOURCES})
59
+add_executable(${APPLICATION_NAME} main.cpp)
51 60
 
52 61
 # Links the target exe against the libraries
53 62
 target_link_libraries(${APPLICATION_NAME} ${LIBRARY_NAME})
63
+target_link_libraries(${APPLICATION_NAME} jsoncpp)
54 64
 target_link_libraries(${APPLICATION_NAME} dbt-core)
55 65
 target_link_libraries(${APPLICATION_NAME} softfloat)
56
-target_link_libraries(${APPLICATION_NAME} sc-components)
57 66
 target_link_libraries(${APPLICATION_NAME} external)
58 67
 target_link_libraries(${APPLICATION_NAME} ${llvm_libs})
59 68
 target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} )

+ 69
- 13
riscv/src/internal/fp_functions.cpp View File

@@ -70,7 +70,7 @@ using namespace std;
70 70
 
71 71
 using namespace llvm;
72 72
 
73
-void add_fp_functions_2_module(Module *mod, uint32_t flen) {
73
+void add_fp_functions_2_module(Module *mod, uint32_t flen, uint32_t xlen) {
74 74
     if(flen){
75 75
         FDECL(fget_flags, INT_TYPE(32));
76 76
         FDECL(fadd_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
@@ -83,6 +83,8 @@ void add_fp_functions_2_module(Module *mod, uint32_t flen) {
83 83
         FDECL(fmadd_s,    INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
84 84
         FDECL(fsel_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
85 85
         FDECL(fclass_s,   INT_TYPE(32), INT_TYPE(32));
86
+        FDECL(fcvt_32_64,     INT_TYPE(64), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
87
+        FDECL(fcvt_64_32,     INT_TYPE(32), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
86 88
         if(flen>32){
87 89
             FDECL(fconv_d2f,  INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
88 90
             FDECL(fconv_f2d,  INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
@@ -96,6 +98,8 @@ void add_fp_functions_2_module(Module *mod, uint32_t flen) {
96 98
             FDECL(fmadd_d,    INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
97 99
             FDECL(fsel_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
98 100
             FDECL(fclass_d,   INT_TYPE(64), INT_TYPE(64));
101
+            FDECL(unbox_s,      INT_TYPE(32), INT_TYPE(64));
102
+
99 103
         }
100 104
     }
101 105
 }
@@ -198,13 +202,15 @@ uint32_t fcvt_s(uint32_t v1, uint32_t op, uint8_t mode) {
198 202
     float32_t v1f{v1};
199 203
     softfloat_exceptionFlags=0;
200 204
     float32_t r;
201
-    int32_t res;
202 205
     switch(op){
203
-    case 0: //w->s, fp to int32
204
-        res = f32_to_i32(v1f,rmm_map[mode&0x7],true);
206
+    case 0:{ //w->s, fp to int32
207
+        uint_fast32_t res = f32_to_i32(v1f,rmm_map[mode&0x7],true);
205 208
         return (uint32_t)res;
206
-    case 1: //wu->s
207
-        return f32_to_ui32(v1f,rmm_map[mode&0x7],true);
209
+    }
210
+    case 1:{ //wu->s
211
+        uint_fast32_t res = f32_to_ui32(v1f,rmm_map[mode&0x7],true);
212
+        return (uint32_t)res;
213
+    }
208 214
     case 2: //s->w
209 215
         r=i32_to_f32(v1);
210 216
         return r.v;
@@ -373,17 +379,19 @@ uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
373 379
     float64_t v1f{v1};
374 380
     softfloat_exceptionFlags=0;
375 381
     float64_t r;
376
-    int32_t res;
377 382
     switch(op){
378
-    case 0: //w->s, fp to int32
379
-        res = f64_to_i64(v1f,rmm_map[mode&0x7],true);
383
+    case 0:{ //l->d, fp to int32
384
+        int64_t res = f64_to_i64(v1f,rmm_map[mode&0x7],true);
380 385
         return (uint64_t)res;
381
-    case 1: //wu->s
382
-        return f64_to_ui64(v1f,rmm_map[mode&0x7],true);
383
-    case 2: //s->w
386
+    }
387
+    case 1:{ //lu->s
388
+        uint64_t res = f64_to_ui64(v1f,rmm_map[mode&0x7],true);
389
+        return res;
390
+    }
391
+    case 2: //s->l
384 392
         r=i64_to_f64(v1);
385 393
         return r.v;
386
-    case 3: //s->wu
394
+    case 3: //s->lu
387 395
         r=ui64_to_f64(v1);
388 396
         return r.v;
389 397
     }
@@ -454,5 +462,53 @@ uint64_t fclass_d(uint64_t v1  ){
454 462
         ( isNaN && !isSNaN )                       << 9;
455 463
 }
456 464
 
465
+uint64_t fcvt_32_64(uint32_t v1, uint32_t op, uint8_t mode) {
466
+    float32_t v1f{v1};
467
+    softfloat_exceptionFlags=0;
468
+    float64_t r;
469
+    switch(op){
470
+    case 0: //l->s, fp to int32
471
+        return f32_to_i64(v1f,rmm_map[mode&0x7],true);
472
+    case 1: //wu->s
473
+        return f32_to_ui64(v1f,rmm_map[mode&0x7],true);
474
+    case 2: //s->w
475
+        r=i32_to_f64(v1);
476
+        return r.v;
477
+    case 3: //s->wu
478
+        r=ui32_to_f64(v1);
479
+        return r.v;
480
+    }
481
+    return 0;
482
+}
483
+
484
+uint32_t fcvt_64_32(uint64_t v1, uint32_t op, uint8_t mode) {
485
+    softfloat_exceptionFlags=0;
486
+    float32_t r;
487
+    switch(op){
488
+    case 0:{ //wu->s
489
+        int32_t r=f64_to_i32(float64_t{v1}, rmm_map[mode&0x7],true);
490
+        return r;
491
+    }
492
+    case 1:{ //wu->s
493
+        uint32_t r=f64_to_ui32(float64_t{v1}, rmm_map[mode&0x7],true);
494
+        return r;
495
+    }
496
+    case 2: //l->s, fp to int32
497
+        r=i64_to_f32(v1);
498
+        return r.v;
499
+    case 3: //wu->s
500
+        r=ui64_to_f32(v1);
501
+        return r.v;
502
+    }
503
+    return 0;
504
+}
505
+
506
+uint32_t unbox_s(uint64_t v){
507
+    constexpr uint64_t mask = std::numeric_limits<uint64_t>::max() & ~((uint64_t)std::numeric_limits<uint32_t>::max());
508
+    if((v & mask) != mask)
509
+        return 0x7fc00000;
510
+    else
511
+        return v & std::numeric_limits<uint32_t>::max();
512
+}
457 513
 }
458 514
 

+ 4459
- 4207
riscv/src/internal/vm_rv32gc.cpp
File diff suppressed because it is too large
View File


+ 2160
- 2230
riscv/src/internal/vm_rv32imac.cpp
File diff suppressed because it is too large
View File


+ 11342
- 0
riscv/src/internal/vm_rv64gc.cpp
File diff suppressed because it is too large
View File


riscv/src/internal/vm_rv64i.cpp
File diff suppressed because it is too large
View File


+ 31
- 31
riscv/src/iss/rv32gc.cpp View File

@@ -1,34 +1,34 @@
1
-////////////////////////////////////////////////////////////////////////////////
2
-// Copyright (C) 2017, MINRES Technologies GmbH
3
-// All rights reserved.
4
-// 
5
-// Redistribution and use in source and binary forms, with or without
6
-// modification, are permitted provided that the following conditions are met:
7
-// 
8
-// 1. Redistributions of source code must retain the above copyright notice,
9
-//    this list of conditions and the following disclaimer.
10
-// 
11
-// 2. Redistributions in binary form must reproduce the above copyright notice,
12
-//    this list of conditions and the following disclaimer in the documentation
13
-//    and/or other materials provided with the distribution.
14
-// 
15
-// 3. Neither the name of the copyright holder nor the names of its contributors
16
-//    may be used to endorse or promote products derived from this software
17
-//    without specific prior written permission.
18
-// 
19
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
-// POSSIBILITY OF SUCH DAMAGE.
30
-//
31
-////////////////////////////////////////////////////////////////////////////////
1
+/*******************************************************************************
2
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
3
+ * All rights reserved.
4
+ *
5
+ * Redistribution and use in source and binary forms, with or without
6
+ * modification, are permitted provided that the following conditions are met:
7
+ *
8
+ * 1. Redistributions of source code must retain the above copyright notice,
9
+ *    this list of conditions and the following disclaimer.
10
+ *
11
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
12
+ *    this list of conditions and the following disclaimer in the documentation
13
+ *    and/or other materials provided with the distribution.
14
+ *
15
+ * 3. Neither the name of the copyright holder nor the names of its contributors
16
+ *    may be used to endorse or promote products derived from this software
17
+ *    without specific prior written permission.
18
+ *
19
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+ * POSSIBILITY OF SUCH DAMAGE.
30
+ *
31
+ *******************************************************************************/
32 32
 
33 33
 #include "util/ities.h"
34 34
 #include <util/logging.h>

+ 81
- 0
riscv/src/iss/rv64gc.cpp View File

@@ -0,0 +1,81 @@
1
+/*******************************************************************************
2
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
3
+ * All rights reserved.
4
+ *
5
+ * Redistribution and use in source and binary forms, with or without
6
+ * modification, are permitted provided that the following conditions are met:
7
+ *
8
+ * 1. Redistributions of source code must retain the above copyright notice,
9
+ *    this list of conditions and the following disclaimer.
10
+ *
11
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
12
+ *    this list of conditions and the following disclaimer in the documentation
13
+ *    and/or other materials provided with the distribution.
14
+ *
15
+ * 3. Neither the name of the copyright holder nor the names of its contributors
16
+ *    may be used to endorse or promote products derived from this software
17
+ *    without specific prior written permission.
18
+ *
19
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+ * POSSIBILITY OF SUCH DAMAGE.
30
+ *
31
+ *******************************************************************************/
32
+
33
+
34
+
35
+#include "util/ities.h"
36
+#include <util/logging.h>
37
+
38
+#include <elfio/elfio.hpp>
39
+#include <iss/arch/rv64gc.h>
40
+
41
+#ifdef __cplusplus
42
+extern "C" {
43
+#endif
44
+#include <ihex.h>
45
+#ifdef __cplusplus
46
+}
47
+#endif
48
+#include <cstdio>
49
+#include <cstring>
50
+#include <fstream>
51
+
52
+using namespace iss::arch;
53
+
54
+constexpr std::array<const char*, 66>    iss::arch::traits<iss::arch::rv64gc>::reg_names;
55
+constexpr std::array<const char*, 66>    iss::arch::traits<iss::arch::rv64gc>::reg_aliases;
56
+constexpr std::array<const uint32_t, 72> iss::arch::traits<iss::arch::rv64gc>::reg_bit_widths;
57
+constexpr std::array<const uint32_t, 73> iss::arch::traits<iss::arch::rv64gc>::reg_byte_offsets;
58
+
59
+rv64gc::rv64gc() {
60
+    reg.icount = 0;
61
+}
62
+
63
+rv64gc::~rv64gc() = default;
64
+
65
+void rv64gc::reset(uint64_t address) {
66
+    for(size_t i=0; i<traits<rv64gc>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64gc>::reg_t),0));
67
+    reg.PC=address;
68
+    reg.NEXT_PC=reg.PC;
69
+    reg.trap_state=0;
70
+    reg.machine_state=0x0;
71
+    reg.icount=0;
72
+}
73
+
74
+uint8_t *rv64gc::get_regs_base_ptr() {
75
+	return reinterpret_cast<uint8_t*>(&reg);
76
+}
77
+
78
+rv64gc::phys_addr_t rv64gc::virt2phys(const iss::addr_t &pc) {
79
+    return phys_addr_t(pc); // change logical address to physical address
80
+}
81
+

+ 79
- 0
riscv/src/iss/rv64i.cpp View File

@@ -0,0 +1,79 @@
1
+/*******************************************************************************
2
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
3
+ * All rights reserved.
4
+ *
5
+ * Redistribution and use in source and binary forms, with or without
6
+ * modification, are permitted provided that the following conditions are met:
7
+ *
8
+ * 1. Redistributions of source code must retain the above copyright notice,
9
+ *    this list of conditions and the following disclaimer.
10
+ *
11
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
12
+ *    this list of conditions and the following disclaimer in the documentation
13
+ *    and/or other materials provided with the distribution.
14
+ *
15
+ * 3. Neither the name of the copyright holder nor the names of its contributors
16
+ *    may be used to endorse or promote products derived from this software
17
+ *    without specific prior written permission.
18
+ *
19
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+ * POSSIBILITY OF SUCH DAMAGE.
30
+ *
31
+ *******************************************************************************/
32
+ 
33
+#include "util/ities.h"
34
+#include <util/logging.h>
35
+
36
+#include <elfio/elfio.hpp>
37
+#include <iss/arch/rv64i.h>
38
+
39
+#ifdef __cplusplus
40
+extern "C" {
41
+#endif
42
+#include <ihex.h>
43
+#ifdef __cplusplus
44
+}
45
+#endif
46
+#include <cstdio>
47
+#include <cstring>
48
+#include <fstream>
49
+
50
+using namespace iss::arch;
51
+
52
+constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::rv64i>::reg_names;
53
+constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::rv64i>::reg_aliases;
54
+constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::rv64i>::reg_bit_widths;
55
+constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::rv64i>::reg_byte_offsets;
56
+
57
+rv64i::rv64i() {
58
+    reg.icount = 0;
59
+}
60
+
61
+rv64i::~rv64i() = default;
62
+
63
+void rv64i::reset(uint64_t address) {
64
+    for(size_t i=0; i<traits<rv64i>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64i>::reg_t),0));
65
+    reg.PC=address;
66
+    reg.NEXT_PC=reg.PC;
67
+    reg.trap_state=0;
68
+    reg.machine_state=0x0;
69
+    reg.icount=0;
70
+}
71
+
72
+uint8_t *rv64i::get_regs_base_ptr() {
73
+	return reinterpret_cast<uint8_t*>(&reg);
74
+}
75
+
76
+rv64i::phys_addr_t rv64i::virt2phys(const iss::addr_t &pc) {
77
+    return phys_addr_t(pc); // change logical address to physical address
78
+}
79
+

+ 0
- 78
riscv/src/iss/rv64ia.cpp View File

@@ -1,78 +0,0 @@
1
-////////////////////////////////////////////////////////////////////////////////
2
-// Copyright (C) 2017, MINRES Technologies GmbH
3
-// All rights reserved.
4
-//
5
-// Redistribution and use in source and binary forms, with or without
6
-// modification, are permitted provided that the following conditions are met:
7
-//
8
-// 1. Redistributions of source code must retain the above copyright notice,
9
-//    this list of conditions and the following disclaimer.
10
-//
11
-// 2. Redistributions in binary form must reproduce the above copyright notice,
12
-//    this list of conditions and the following disclaimer in the documentation
13
-//    and/or other materials provided with the distribution.
14
-//
15
-// 3. Neither the name of the copyright holder nor the names of its contributors
16
-//    may be used to endorse or promote products derived from this software
17
-//    without specific prior written permission.
18
-//
19
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
-// POSSIBILITY OF SUCH DAMAGE.
30
-//
31
-// Created on: Tue Sep 05 18:57:24 CEST 2017
32
-//             *      rv64ia.cpp Author: <CoreDSL Generator>
33
-//
34
-////////////////////////////////////////////////////////////////////////////////
35
-
36
-#include "util/ities.h"
37
-#include <util/logging.h>
38
-
39
-#include <elfio/elfio.hpp>
40
-#include <iss/arch/rv64ia.h>
41
-
42
-#ifdef __cplusplus
43
-extern "C" {
44
-#endif
45
-#include <ihex.h>
46
-#ifdef __cplusplus
47
-}
48
-#endif
49
-#include <cstdio>
50
-#include <cstring>
51
-#include <fstream>
52
-
53
-using namespace iss::arch;
54
-
55
-constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::rv64ia>::reg_names;
56
-constexpr std::array<const char*, 33>    iss::arch::traits<iss::arch::rv64ia>::reg_aliases;
57
-constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::rv64ia>::reg_bit_widths;
58
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::rv64ia>::reg_byte_offsets;
59
-
60
-rv64ia::rv64ia() { reg.icount = 0; reg.machine_state = 0x3;}
61
-
62
-rv64ia::~rv64ia(){}
63
-
64
-void rv64ia::reset(uint64_t address) {
65
-    for (size_t i = 0; i < traits<rv64ia>::NUM_REGS; ++i)
66
-        set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t), 0));
67
-    reg.PC = address;
68
-    reg.NEXT_PC = reg.PC;
69
-    reg.trap_state = 0;
70
-    reg.machine_state = 0x3;
71
-    reg.icount=0;
72
-}
73
-
74
-uint8_t *rv64ia::get_regs_base_ptr() { return reinterpret_cast<uint8_t *>(&reg); }
75
-
76
-rv64ia::phys_addr_t rv64ia::virt2phys(const iss::addr_t &pc) {
77
-    return phys_addr_t(pc); // change logical address to physical address
78
-}

+ 7
- 2
riscv/src/main.cpp View File

@@ -38,7 +38,8 @@
38 38
 #include <iss/arch/riscv_hart_msu_vp.h>
39 39
 #include <iss/arch/rv32imac.h>
40 40
 #include <iss/arch/rv32gc.h>
41
-#include <iss/arch/rv64ia.h>
41
+#include <iss/arch/rv64gc.h>
42
+#include <iss/arch/rv64i.h>
42 43
 #include <iss/llvm/jit_helper.h>
43 44
 #include <iss/log_categories.h>
44 45
 #include <iss/plugin/cycle_estimate.h>
@@ -107,7 +108,11 @@ int main(int argc, char *argv[]) {
107 108
         std::unique_ptr<iss::arch_if> cpu{nullptr};
108 109
         std::string isa_opt(clim["isa"].as<std::string>());
109 110
         if (isa_opt=="rv64ia") {
110
-            iss::arch::rv64ia* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64ia>();
111
+            iss::arch::rv64i* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64i>();
112
+            vm = iss::create(lcpu, clim["gdb-port"].as<unsigned>());
113
+            cpu.reset(lcpu);
114
+        } else if (isa_opt=="rv64gc") {
115
+            iss::arch::rv64gc* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64gc>();
111 116
             vm = iss::create(lcpu, clim["gdb-port"].as<unsigned>());
112 117
             cpu.reset(lcpu);
113 118
         } else if (isa_opt=="rv32imac") {

+ 1
- 1
sc-components

@@ -1 +1 @@
1
-Subproject commit d334928b3627d8abbdbe5b047782901250e2270d
1
+Subproject commit 05ba88052cf922b1e93550342d8e297338619b5d