Browse Source

added sc_comm_singleton to coordinate interaction with clients (e.g. web

browser)
pull/1/head
Eyck Jentzsch 3 years ago
parent
commit
eced81b5ea
35 changed files with 953 additions and 467 deletions
  1. +1
    -0
      conanfile.txt
  2. +33
    -0
      html/app.js
  3. +14
    -0
      html/index.html
  4. +16
    -0
      html/lib/jquery.min.js
  5. +105
    -0
      html/ws.html
  6. +7
    -2
      riscv.sc/gen_input/fe310.rdl
  7. +3
    -3
      riscv.sc/gen_input/plic.rdl
  8. +11
    -0
      riscv.sc/incl/sysc/SiFive/core_complex.h
  9. +45
    -38
      riscv.sc/incl/sysc/SiFive/gen/aon_regs.h
  10. +20
    -13
      riscv.sc/incl/sysc/SiFive/gen/clint_regs.h
  11. +6
    -5
      riscv.sc/incl/sysc/SiFive/gen/e300_plat_t.h
  12. +33
    -26
      riscv.sc/incl/sysc/SiFive/gen/gpio_regs.h
  13. +31
    -24
      riscv.sc/incl/sysc/SiFive/gen/plic_regs.h
  14. +34
    -27
      riscv.sc/incl/sysc/SiFive/gen/prci_regs.h
  15. +63
    -56
      riscv.sc/incl/sysc/SiFive/gen/spi_regs.h
  16. +37
    -30
      riscv.sc/incl/sysc/SiFive/gen/uart_regs.h
  17. +10
    -0
      riscv.sc/incl/sysc/SiFive/gpio.h
  18. +4
    -3
      riscv.sc/incl/sysc/SiFive/platform.h
  19. +2
    -0
      riscv.sc/incl/sysc/SiFive/uart.h
  20. +82
    -0
      riscv.sc/incl/sysc/sc_comm_singleton.h
  21. +0
    -49
      riscv.sc/incl/sysc/sc_singleton.h
  22. +7
    -3
      riscv.sc/src/sc_main.cpp
  23. +3
    -1
      riscv.sc/src/sysc/aon.cpp
  24. +10
    -6
      riscv.sc/src/sysc/clint.cpp
  25. +66
    -12
      riscv.sc/src/sysc/core_complex.cpp
  26. +69
    -2
      riscv.sc/src/sysc/gpio.cpp
  27. +24
    -8
      riscv.sc/src/sysc/platform.cpp
  28. +16
    -13
      riscv.sc/src/sysc/plic.cpp
  29. +4
    -1
      riscv.sc/src/sysc/prci.cpp
  30. +153
    -0
      riscv.sc/src/sysc/sc_comm_singleton.cpp
  31. +0
    -57
      riscv.sc/src/sysc/sc_singleton.cpp
  32. +3
    -1
      riscv.sc/src/sysc/spi.cpp
  33. +17
    -66
      riscv.sc/src/sysc/uart.cpp
  34. +23
    -20
      riscv/incl/iss/arch/riscv_hart_msu_vp.h
  35. +1
    -1
      sc-components

+ 1
- 0
conanfile.txt View File

@ -6,6 +6,7 @@ SystemCVerification/2.0.0a@minres/stable
[generators]
cmake
txt
[options]
Poco:shared=True

+ 33
- 0
html/app.js View File

@ -0,0 +1,33 @@
var ws;
$(function() {
ws = new WebSocket('ws://' + document.location.host + '/ws');
ws.onopen = function() {
console.log('onopen');
};
ws.onclose = function() {
$('#message').text('Lost connection.');
console.log('onclose');
};
ws.onmessage = function(message) {
console.log("got '" + message.data + "'");
eval(message.data);
};
ws.onerror = function(error) {
console.log('onerror ' + error);
console.log(error);
};
$('#count').click(function() {
ws.send($('#count').val());
});
$('#close').click(function() {
ws.send('close');
});
$('#die').click(function() {
ws.send('die');
});
});
set = function(value) {
$('#count').val(value)
}

+ 14
- 0
html/index.html View File

@ -0,0 +1,14 @@
<!DOCTYPE html>
<html>
<head>
<title>Hello, world</title>
<script src='lib/jquery.min.js'></script>
<script src='app.js'></script>
</head>
<body>
<input id="count" type="button" value="..."></input>
<input id="close" type="button" value="Close"></input>
<input id="die" type="button" value="Die"></input>
</body>
</html>

+ 16
- 0
html/lib/jquery.min.js
File diff suppressed because it is too large
View File


+ 105
- 0
html/ws.html View File

@ -0,0 +1,105 @@
<!doctype html>
<html lang=en>
<head>
<meta charset=utf-8>
<meta name=viewport content="width=device-width, initial-scale=1">
<title>system output</title>
<style>
h1 { font-family: helvetica, sans-serif; margin: 0; }
h1+p { margin: 0; }
li { font-family: Courier; list-style-type: '>';}
pre { margin-top:0; margin-bottom:0;}
.term { background-color:black; color:white; font-weight:bold;padding-top:10px; padding-bottom:10px; max-height:400px; overflow: scroll;}
span.timestamp { font-family: monospace; white-space: pre;width: 50px;}
span.value_1 { background-color: green;}
span.value_0 { background-color: blue;}
span.value_x { background-color: red;}
</style>
</head>
<body>
<h1>system output</h1>
<div id="top">
</div>
<script>
String.format = function() {
// The string containing the format items (e.g. "{0}")
// will and always has to be the first argument.
var theString = arguments[0];
// start with the second argument (i = 1)
for (var i = 1; i < arguments.length; i++) {
// "gm" = RegEx options for Global search (more than one instance)
// and for Multiline search
var regEx = new RegExp("\\{" + (i - 1) + "\\}", "gm");
theString = theString.replace(regEx, arguments[i]);
}
return theString;
}
String.prototype.paddingLeft = function (paddingValue) {
return String(paddingValue + this).slice(-paddingValue.length);
};
var log = function (n, m) {
console.log(m);
var data = JSON.parse(m);
if( data.hasOwnProperty("message") ) {
var ul = document.getElementById(n);
var li = document.createElement('li');
var p = document.createElement('pre');
// i.innerText = new Date().toISOString()+': '+m;
p.innerText = '['+data.time.paddingLeft(' ')+'] '+ data.message;
li.appendChild(p);
ul.appendChild(li);
var objDiv = document.getElementById(n + '_container');
objDiv.scrollTop = objDiv.scrollHeight;
} else if(data.hasOwnProperty("data")){
var ul = document.getElementById(n);
var li = document.createElement('li');
var span = document.createElement('span');
span.className="timestamp";
span.innerText='['+data.time.paddingLeft(' ')+']'
li.appendChild(span);
var s = data.data;
for ( var i = 0; i < s.length; i++ ){
var spani = document.createElement('span');
if(s.charAt(i) == 'Z')
spani.className="value_z";
else if(s.charAt(i) == '1')
spani.className="value_1";
else if(s.charAt(i) == '0')
spani.className="value_0";
else if(s.charAt(i) == 'X')
spani.className="value_x";
spani.appendChild(document.createTextNode('\u00A0'));
li.appendChild(spani);
}
ul.appendChild(li);
var objDiv = document.getElementById(n + '_container');
objDiv.scrollTop = objDiv.scrollHeight;
}
}
var open_connection = function(name){
var s = new WebSocket('ws://'+window.location.host+'/ws/i_simple_system.i_'+name);
s.addEventListener('error', function (m) { log(name, new Date().toISOString()+': ===connection error ==='); });
s.addEventListener('open', function (m) { log(name, new Date().toISOString()+': ===connection opened==='); });
s.addEventListener('message', function (m) { log(name, m.data); });
s.addEventListener('close', function (m) { log(name, new Date().toISOString()+': ===connection closed==='); });
}
var createElem = function(n){
var top = document.getElementById('top');
var p = document.createElement('p');
p.innerText="Component " + n;
var div = document.createElement('div');
div.className = "term";
div.id= n + '_container';
var ul = document.createElement('ul');
ul.id= n;
div.appendChild(ul);
top.appendChild(p);
top.appendChild(div);
open_connection(n);
}
createElem("uart0");
createElem("gpio0");
</script>
</body>
</html>

+ 7
- 2
riscv.sc/gen_input/fe310.rdl View File

@ -12,8 +12,13 @@ addrmap e300_plat_t {
plic_regs plic @0x0C000000;
aon_regs aon @0x10000000;
prci_regs prci @0x10008000;
gpio_regs gpio @0x10012000;
gpio_regs gpio0 @0x10012000;
uart_regs uart0 @0x10013000;
spi_regs spi @0x10014000;
spi_regs qspi0 @0x10014000;
//pwm_regs pwm0 @0x10015000;
uart_regs uart1 @0x10023000;
spi_regs qspi1 @0x10024000;
//pwm_regs pwm1 @0x10025000;
spi_regs qspi2 @0x10034000;
//pwm_regs pwm2 @0x10035000;
} e300_plat;

+ 3
- 3
riscv.sc/gen_input/plic.rdl View File

@ -3,17 +3,17 @@ regfile plic_regs {
name="priority";
desc="interrupt source priority";
field {} priority[2:0];
} priority[255] @0x004;
} priority[256] @0x000;
reg {
name="pending";
desc="pending irq";
field {} pending[31:0];
} pending @0x1000;
} pending[8] @0x1000;
reg {
name="enabled";
desc="enabled interrupts";
field {} enabled[31:0];
} enabled @0x2000;
} enabled[8] @0x2000;
reg {
name="threshold";
desc="interrupt priority threshold";

+ 11
- 0
riscv.sc/incl/sysc/SiFive/core_complex.h View File

@ -86,6 +86,14 @@ public:
sc_core::sc_in<bool> rst_i;
sc_core::sc_in<bool> global_irq_i;
sc_core::sc_in<bool> timer_irq_i;
sc_core::sc_in<bool> sw_irq_i;
sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i;
scc::ext_attribute<std::string> elf_file;
scc::ext_attribute<bool> enable_disass;
@ -124,6 +132,9 @@ protected:
void start_of_simulation();
void run();
void clk_cb();
void sw_irq_cb();
void timer_irq_cb();
void global_irq_cb();
util::range_lut<tlm_dmi_ext> read_lut, write_lut;
tlm_utils::tlm_quantumkeeper quantum_keeper;
std::vector<uint8_t> write_buf;

+ 45
- 38
riscv.sc/incl/sysc/SiFive/gen/aon_regs.h View File

@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Oct 04 10:06:35 CEST 2017
// Created on: Fri Nov 10 18:01:53 CET 2017
// * aon_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@ -36,66 +36,69 @@
#ifndef _AON_REGS_H_
#define _AON_REGS_H_
#include <scc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
#include <scc/register.h>
#include <scc/tlm_target.h>
namespace sysc {
class aon_regs : public sc_core::sc_module, public scc::resetable {
class aon_regs :
public sc_core::sc_module,
public scc::resetable
{
public:
// storage declarations
uint32_t r_wdogcfg;
uint32_t r_wdogcount;
uint32_t r_wdogs;
uint32_t r_wdogfeed;
uint32_t r_wdogkey;
uint32_t r_wdogcmp;
uint32_t r_rtccfg;
uint32_t r_rtclo;
uint32_t r_rtchi;
uint32_t r_rtcs;
uint32_t r_rtccmp;
uint32_t r_lfrosccfg;
std::array<uint32_t, 32> r_backup;
BEGIN_BF_DECL(pmuwakeupi_t, uint32_t);
BF_FIELD(delay, 0, 4);
BF_FIELD(vddpaden, 5, 1);
BF_FIELD(corerst, 7, 1);
BF_FIELD(hfclkrst, 8, 1);
END_BF_DECL();
BF_FIELD(delay, 0, 4);
BF_FIELD(vddpaden, 5, 1);
BF_FIELD(corerst, 7, 1);
BF_FIELD(hfclkrst, 8, 1);
END_BF_DECL() ;
std::array<pmuwakeupi_t, 8> r_pmuwakeupi;
BEGIN_BF_DECL(pmusleepi_t, uint32_t);
BF_FIELD(delay, 0, 4);
BF_FIELD(vddpaden, 5, 1);
BF_FIELD(corerst, 7, 1);
BF_FIELD(hfclkrst, 8, 1);
END_BF_DECL();
BF_FIELD(delay, 0, 4);
BF_FIELD(vddpaden, 5, 1);
BF_FIELD(corerst, 7, 1);
BF_FIELD(hfclkrst, 8, 1);
END_BF_DECL() ;
std::array<pmusleepi_t, 8> r_pmusleepi;
uint32_t r_pmuie;
uint32_t r_pmucause;
uint32_t r_pmusleep;
uint32_t r_pmukey;
// register declarations
scc::sc_register<uint32_t> wdogcfg;
scc::sc_register<uint32_t> wdogcount;
@ -116,10 +119,11 @@ public:
scc::sc_register<uint32_t> pmucause;
scc::sc_register<uint32_t> pmusleep;
scc::sc_register<uint32_t> pmukey;
aon_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
template<unsigned BUSWIDTH=32>
void registerResources(scc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -146,9 +150,12 @@ inline sysc::aon_regs::aon_regs(sc_core::sc_module_name nm)
, NAMED(pmuie, r_pmuie, 0, *this)
, NAMED(pmucause, r_pmucause, 0, *this)
, NAMED(pmusleep, r_pmusleep, 0, *this)
, NAMED(pmukey, r_pmukey, 0, *this) {}
, NAMED(pmukey, r_pmukey, 0, *this)
{
}
template <unsigned BUSWIDTH> inline void sysc::aon_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
template<unsigned BUSWIDTH>
inline void sysc::aon_regs::registerResources(scc::tlm_target<BUSWIDTH>& target) {
target.addResource(wdogcfg, 0x0UL);
target.addResource(wdogcount, 0x8UL);
target.addResource(wdogs, 0x10UL);

+ 20
- 13
riscv.sc/incl/sysc/SiFive/gen/clint_regs.h View File

@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Oct 04 10:06:35 CEST 2017
// Created on: Fri Nov 10 18:01:53 CET 2017
// * clint_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@ -36,32 +36,36 @@
#ifndef _CLINT_REGS_H_
#define _CLINT_REGS_H_
#include <scc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
#include <scc/register.h>
#include <scc/tlm_target.h>
namespace sysc {
class clint_regs : public sc_core::sc_module, public scc::resetable {
class clint_regs :
public sc_core::sc_module,
public scc::resetable
{
public:
// storage declarations
BEGIN_BF_DECL(msip_t, uint32_t);
BF_FIELD(msip, 0, 1);
BF_FIELD(msip, 0, 1);
END_BF_DECL() r_msip;
uint64_t r_mtimecmp;
uint64_t r_mtime;
// register declarations
scc::sc_register<msip_t> msip;
scc::sc_register<uint64_t> mtimecmp;
scc::sc_register<uint64_t> mtime;
clint_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
template<unsigned BUSWIDTH=32>
void registerResources(scc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -72,9 +76,12 @@ inline sysc::clint_regs::clint_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(msip, r_msip, 0, *this)
, NAMED(mtimecmp, r_mtimecmp, 0, *this)
, NAMED(mtime, r_mtime, 0, *this) {}
, NAMED(mtime, r_mtime, 0, *this)
{
}
template <unsigned BUSWIDTH> inline void sysc::clint_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
template<unsigned BUSWIDTH>
inline void sysc::clint_regs::registerResources(scc::tlm_target<BUSWIDTH>& target) {
target.addResource(msip, 0x0UL);
target.addResource(mtimecmp, 0x4000UL);
target.addResource(mtime, 0xbff8UL);

+ 6
- 5
riscv.sc/incl/sysc/SiFive/gen/e300_plat_t.h View File

@ -1,16 +1,17 @@
#ifndef _E300_PLAT_MAP_H_
#define _E300_PLAT_MAP_H_
// need double braces, see
// https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<scc::target_memory_map_entry<32>, 8> e300_plat_map = {{
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<scc::target_memory_map_entry<32>, 10> e300_plat_map = {{
{&i_clint, 0x2000000, 0xc000},
{&i_plic, 0xc000000, 0x200008},
{&i_aon, 0x10000000, 0x150},
{&i_prci, 0x10008000, 0x14},
{&i_gpio, 0x10012000, 0x44},
{&i_gpio0, 0x10012000, 0x44},
{&i_uart0, 0x10013000, 0x1c},
{&i_qspi0, 0x10014000, 0x78},
{&i_uart1, 0x10023000, 0x1c},
{&i_spi, 0x10014000, 0x78},
{&i_qspi1, 0x10024000, 0x78},
{&i_qspi2, 0x10034000, 0x78},
}};
#endif /* _E300_PLAT_MAP_H_ */

+ 33
- 26
riscv.sc/incl/sysc/SiFive/gen/gpio_regs.h View File

@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Oct 04 10:06:35 CEST 2017
// Created on: Fri Nov 10 18:01:53 CET 2017
// * gpio_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@ -36,50 +36,53 @@
#ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_
#include <scc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
#include <scc/register.h>
#include <scc/tlm_target.h>
namespace sysc {
class gpio_regs : public sc_core::sc_module, public scc::resetable {
class gpio_regs :
public sc_core::sc_module,
public scc::resetable
{
public:
// storage declarations
uint32_t r_value;
uint32_t r_input_en;
uint32_t r_output_en;
uint32_t r_port;
uint32_t r_pue;
uint32_t r_ds;
uint32_t r_rise_ie;
uint32_t r_rise_ip;
uint32_t r_fall_ie;
uint32_t r_fall_ip;
uint32_t r_high_ie;
uint32_t r_high_ip;
uint32_t r_low_ie;
uint32_t r_low_ip;
uint32_t r_iof_en;
uint32_t r_iof_sel;
uint32_t r_out_xor;
// register declarations
scc::sc_register<uint32_t> value;
scc::sc_register<uint32_t> input_en;
@ -98,10 +101,11 @@ public:
scc::sc_register<uint32_t> iof_en;
scc::sc_register<uint32_t> iof_sel;
scc::sc_register<uint32_t> out_xor;
gpio_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
template<unsigned BUSWIDTH=32>
void registerResources(scc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -126,9 +130,12 @@ inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm)
, NAMED(low_ip, r_low_ip, 0, *this)
, NAMED(iof_en, r_iof_en, 0, *this)
, NAMED(iof_sel, r_iof_sel, 0, *this)
, NAMED(out_xor, r_out_xor, 0, *this) {}
, NAMED(out_xor, r_out_xor, 0, *this)
{
}
template <unsigned BUSWIDTH> inline void sysc::gpio_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
template<unsigned BUSWIDTH>
inline void sysc::gpio_regs::registerResources(scc::tlm_target<BUSWIDTH>& target) {
target.addResource(value, 0x0UL);
target.addResource(input_en, 0x4UL);
target.addResource(output_en, 0x8UL);

+ 31
- 24
riscv.sc/incl/sysc/SiFive/gen/plic_regs.h View File

@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Oct 04 10:06:35 CEST 2017
// Created on: Fri Nov 10 18:01:53 CET 2017
// * plic_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@ -36,41 +36,45 @@
#ifndef _PLIC_REGS_H_
#define _PLIC_REGS_H_
#include <scc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
#include <scc/register.h>
#include <scc/tlm_target.h>
namespace sysc {
class plic_regs : public sc_core::sc_module, public scc::resetable {
class plic_regs :
public sc_core::sc_module,
public scc::resetable
{
public:
// storage declarations
BEGIN_BF_DECL(priority_t, uint32_t);
BF_FIELD(priority, 0, 3);
END_BF_DECL();
std::array<priority_t, 255> r_priority;
uint32_t r_pending;
uint32_t r_enabled;
BF_FIELD(priority, 0, 3);
END_BF_DECL() ;
std::array<priority_t, 256> r_priority;
std::array<uint32_t, 8> r_pending;
std::array<uint32_t, 8> r_enabled;
BEGIN_BF_DECL(threshold_t, uint32_t);
BF_FIELD(threshold, 0, 3);
BF_FIELD(threshold, 0, 3);
END_BF_DECL() r_threshold;
uint32_t r_claim_complete;
// register declarations
scc::sc_register_indexed<priority_t, 255> priority;
scc::sc_register<uint32_t> pending;
scc::sc_register<uint32_t> enabled;
scc::sc_register_indexed<priority_t, 256> priority;
scc::sc_register_indexed<uint32_t, 8> pending;
scc::sc_register_indexed<uint32_t, 8> enabled;
scc::sc_register<threshold_t> threshold;
scc::sc_register<uint32_t> claim_complete;
plic_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
template<unsigned BUSWIDTH=32>
void registerResources(scc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -83,10 +87,13 @@ inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm)
, NAMED(pending, r_pending, 0, *this)
, NAMED(enabled, r_enabled, 0, *this)
, NAMED(threshold, r_threshold, 0, *this)
, NAMED(claim_complete, r_claim_complete, 0, *this) {}
, NAMED(claim_complete, r_claim_complete, 0, *this)
{
}
template <unsigned BUSWIDTH> inline void sysc::plic_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
target.addResource(priority, 0x4UL);
template<unsigned BUSWIDTH>
inline void sysc::plic_regs::registerResources(scc::tlm_target<BUSWIDTH>& target) {
target.addResource(priority, 0x0UL);
target.addResource(pending, 0x1000UL);
target.addResource(enabled, 0x2000UL);
target.addResource(threshold, 0x200000UL);

+ 34
- 27
riscv.sc/incl/sysc/SiFive/gen/prci_regs.h View File

@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Oct 04 10:06:35 CEST 2017
// Created on: Fri Nov 10 18:01:53 CET 2017
// * prci_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@ -36,52 +36,56 @@
#ifndef _PRCI_REGS_H_
#define _PRCI_REGS_H_
#include <scc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
#include <scc/register.h>
#include <scc/tlm_target.h>
namespace sysc {
class prci_regs : public sc_core::sc_module, public scc::resetable {
class prci_regs :
public sc_core::sc_module,
public scc::resetable
{
public:
// storage declarations
BEGIN_BF_DECL(hfrosccfg_t, uint32_t);
BF_FIELD(hfroscdiv, 0, 6);
BF_FIELD(hfrosctrim, 16, 5);
BF_FIELD(hfroscen, 30, 1);
BF_FIELD(hfroscrdy, 31, 1);
BF_FIELD(hfroscdiv, 0, 6);
BF_FIELD(hfrosctrim, 16, 5);
BF_FIELD(hfroscen, 30, 1);
BF_FIELD(hfroscrdy, 31, 1);
END_BF_DECL() r_hfrosccfg;
BEGIN_BF_DECL(hfxosccfg_t, uint32_t);
BF_FIELD(hfxoscrdy, 31, 1);
BF_FIELD(hfxoscen, 30, 1);
BF_FIELD(hfxoscrdy, 31, 1);
BF_FIELD(hfxoscen, 30, 1);
END_BF_DECL() r_hfxosccfg;
BEGIN_BF_DECL(pllcfg_t, uint32_t);
BF_FIELD(pllr, 0, 3);
BF_FIELD(pllf, 4, 6);
BF_FIELD(pllq, 10, 2);
BF_FIELD(pllsel, 16, 1);
BF_FIELD(pllrefsel, 17, 1);
BF_FIELD(pllbypass, 18, 1);
BF_FIELD(plllock, 31, 1);
BF_FIELD(pllr, 0, 3);
BF_FIELD(pllf, 4, 6);
BF_FIELD(pllq, 10, 2);
BF_FIELD(pllsel, 16, 1);
BF_FIELD(pllrefsel, 17, 1);
BF_FIELD(pllbypass, 18, 1);
BF_FIELD(plllock, 31, 1);
END_BF_DECL() r_pllcfg;
uint32_t r_plloutdiv;
uint32_t r_coreclkcfg;
// register declarations
scc::sc_register<hfrosccfg_t> hfrosccfg;
scc::sc_register<hfxosccfg_t> hfxosccfg;
scc::sc_register<pllcfg_t> pllcfg;
scc::sc_register<uint32_t> plloutdiv;
scc::sc_register<uint32_t> coreclkcfg;
prci_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
template<unsigned BUSWIDTH=32>
void registerResources(scc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -94,9 +98,12 @@ inline sysc::prci_regs::prci_regs(sc_core::sc_module_name nm)
, NAMED(hfxosccfg, r_hfxosccfg, 0, *this)
, NAMED(pllcfg, r_pllcfg, 0, *this)
, NAMED(plloutdiv, r_plloutdiv, 0, *this)
, NAMED(coreclkcfg, r_coreclkcfg, 0, *this) {}
, NAMED(coreclkcfg, r_coreclkcfg, 0, *this)
{
}
template <unsigned BUSWIDTH> inline void sysc::prci_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
template<unsigned BUSWIDTH>
inline void sysc::prci_regs::registerResources(scc::tlm_target<BUSWIDTH>& target) {
target.addResource(hfrosccfg, 0x0UL);
target.addResource(hfxosccfg, 0x4UL);
target.addResource(pllcfg, 0x8UL);

+ 63
- 56
riscv.sc/incl/sysc/SiFive/gen/spi_regs.h View File

@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Oct 04 10:06:35 CEST 2017
// Created on: Fri Nov 10 18:01:53 CET 2017
// * spi_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@ -36,93 +36,96 @@
#ifndef _SPI_REGS_H_
#define _SPI_REGS_H_
#include <scc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
#include <scc/register.h>
#include <scc/tlm_target.h>
namespace sysc {
class spi_regs : public sc_core::sc_module, public scc::resetable {
class spi_regs :
public sc_core::sc_module,
public scc::resetable
{
public:
// storage declarations
BEGIN_BF_DECL(sckdiv_t, uint32_t);
BF_FIELD(div, 0, 12);
BF_FIELD(div, 0, 12);
END_BF_DECL() r_sckdiv;
BEGIN_BF_DECL(sckmode_t, uint32_t);
BF_FIELD(pha, 0, 1);
BF_FIELD(pol, 1, 1);
BF_FIELD(pha, 0, 1);
BF_FIELD(pol, 1, 1);
END_BF_DECL() r_sckmode;
uint32_t r_csid;
uint32_t r_csdef;
BEGIN_BF_DECL(csmode_t, uint32_t);
BF_FIELD(mode, 0, 2);
BF_FIELD(mode, 0, 2);
END_BF_DECL() r_csmode;
BEGIN_BF_DECL(delay0_t, uint32_t);
BF_FIELD(cssck, 0, 8);
BF_FIELD(sckcs, 16, 8);
BF_FIELD(cssck, 0, 8);
BF_FIELD(sckcs, 16, 8);
END_BF_DECL() r_delay0;
BEGIN_BF_DECL(delay1_t, uint32_t);
BF_FIELD(intercs, 0, 16);
BF_FIELD(interxfr, 16, 8);
BF_FIELD(intercs, 0, 16);
BF_FIELD(interxfr, 16, 8);
END_BF_DECL() r_delay1;
BEGIN_BF_DECL(fmt_t, uint32_t);
BF_FIELD(proto, 0, 2);
BF_FIELD(endian, 2, 1);
BF_FIELD(dir, 3, 1);
BF_FIELD(len, 16, 4);
BF_FIELD(proto, 0, 2);
BF_FIELD(endian, 2, 1);
BF_FIELD(dir, 3, 1);
BF_FIELD(len, 16, 4);
END_BF_DECL() r_fmt;
BEGIN_BF_DECL(txdata_t, uint32_t);
BF_FIELD(data, 0, 8);
BF_FIELD(full, 31, 1);
BF_FIELD(data, 0, 8);
BF_FIELD(full, 31, 1);
END_BF_DECL() r_txdata;
BEGIN_BF_DECL(rxdata_t, uint32_t);
BF_FIELD(data, 0, 8);
BF_FIELD(empty, 31, 1);
BF_FIELD(data, 0, 8);
BF_FIELD(empty, 31, 1);
END_BF_DECL() r_rxdata;
BEGIN_BF_DECL(txmark_t, uint32_t);
BF_FIELD(txmark, 0, 3);
BF_FIELD(txmark, 0, 3);
END_BF_DECL() r_txmark;
BEGIN_BF_DECL(rxmark_t, uint32_t);
BF_FIELD(rxmark, 0, 3);
BF_FIELD(rxmark, 0, 3);
END_BF_DECL() r_rxmark;
BEGIN_BF_DECL(fctrl_t, uint32_t);
BF_FIELD(en, 0, 1);
BF_FIELD(en, 0, 1);
END_BF_DECL() r_fctrl;
BEGIN_BF_DECL(ffmt_t, uint32_t);
BF_FIELD(cmd_en, 0, 1);
BF_FIELD(addr_len, 1, 2);
BF_FIELD(pad_cnt, 3, 4);
BF_FIELD(cmd_proto, 7, 2);
BF_FIELD(addr_proto, 9, 2);
BF_FIELD(data_proto, 11, 2);
BF_FIELD(cmd_code, 16, 8);
BF_FIELD(pad_code, 24, 8);
BF_FIELD(cmd_en, 0, 1);
BF_FIELD(addr_len, 1, 2);
BF_FIELD(pad_cnt, 3, 4);
BF_FIELD(cmd_proto, 7, 2);
BF_FIELD(addr_proto, 9, 2);
BF_FIELD(data_proto, 11, 2);
BF_FIELD(cmd_code, 16, 8);
BF_FIELD(pad_code, 24, 8);
END_BF_DECL() r_ffmt;
BEGIN_BF_DECL(ie_t, uint32_t);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ie;
BEGIN_BF_DECL(ip_t, uint32_t);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ip;
// register declarations
scc::sc_register<sckdiv_t> sckdiv;
scc::sc_register<sckmode_t> sckmode;
@ -140,10 +143,11 @@ public:
scc::sc_register<ffmt_t> ffmt;
scc::sc_register<ie_t> ie;
scc::sc_register<ip_t> ip;
spi_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
template<unsigned BUSWIDTH=32>
void registerResources(scc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -167,9 +171,12 @@ inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm)
, NAMED(fctrl, r_fctrl, 0, *this)
, NAMED(ffmt, r_ffmt, 0, *this)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this) {}
, NAMED(ip, r_ip, 0, *this)
{
}
template <unsigned BUSWIDTH> inline void sysc::spi_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
template<unsigned BUSWIDTH>
inline void sysc::spi_regs::registerResources(scc::tlm_target<BUSWIDTH>& target) {
target.addResource(sckdiv, 0x0UL);
target.addResource(sckmode, 0x4UL);
target.addResource(csid, 0x10UL);

+ 37
- 30
riscv.sc/incl/sysc/SiFive/gen/uart_regs.h View File

@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Oct 04 10:06:35 CEST 2017
// Created on: Fri Nov 10 18:01:53 CET 2017
// * uart_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@ -36,51 +36,54 @@
#ifndef _UART_REGS_H_
#define _UART_REGS_H_
#include <scc/utilities.h>
#include <util/bit_field.h>
#include "scc/register.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
#include <scc/register.h>
#include <scc/tlm_target.h>
namespace sysc {
class uart_regs : public sc_core::sc_module, public scc::resetable {
class uart_regs :
public sc_core::sc_module,
public scc::resetable
{
public:
// storage declarations
BEGIN_BF_DECL(txdata_t, uint32_t);
BF_FIELD(data, 0, 8);
BF_FIELD(full, 31, 1);
BF_FIELD(data, 0, 8);
BF_FIELD(full, 31, 1);
END_BF_DECL() r_txdata;
BEGIN_BF_DECL(rxdata_t, uint32_t);
BF_FIELD(data, 0, 8);
BF_FIELD(empty, 31, 1);
BF_FIELD(data, 0, 8);
BF_FIELD(empty, 31, 1);
END_BF_DECL() r_rxdata;
BEGIN_BF_DECL(txctrl_t, uint32_t);
BF_FIELD(txen, 0, 1);
BF_FIELD(nstop, 1, 1);
BF_FIELD(txcnt, 16, 3);
BF_FIELD(txen, 0, 1);
BF_FIELD(nstop, 1, 1);
BF_FIELD(txcnt, 16, 3);
END_BF_DECL() r_txctrl;
BEGIN_BF_DECL(rxctrl_t, uint32_t);
BF_FIELD(rxen, 0, 1);
BF_FIELD(rxcnt, 16, 3);
BF_FIELD(rxen, 0, 1);
BF_FIELD(rxcnt, 16, 3);
END_BF_DECL() r_rxctrl;
BEGIN_BF_DECL(ie_t, uint32_t);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ie;
BEGIN_BF_DECL(ip_t, uint32_t);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ip;
BEGIN_BF_DECL(div_t, uint32_t);
BF_FIELD(div, 0, 16);
BF_FIELD(div, 0, 16);
END_BF_DECL() r_div;
// register declarations
scc::sc_register<txdata_t> txdata;
scc::sc_register<rxdata_t> rxdata;
@ -89,10 +92,11 @@ public:
scc::sc_register<ie_t> ie;
scc::sc_register<ip_t> ip;
scc::sc_register<div_t> div;
uart_regs(sc_core::sc_module_name nm);
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
template<unsigned BUSWIDTH=32>
void registerResources(scc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
@ -107,9 +111,12 @@ inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm)
, NAMED(rxctrl, r_rxctrl, 0, *this)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this)
, NAMED(div, r_div, 0, *this) {}
, NAMED(div, r_div, 0, *this)
{
}
template <unsigned BUSWIDTH> inline void sysc::uart_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
template<unsigned BUSWIDTH>
inline void sysc::uart_regs::registerResources(scc::tlm_target<BUSWIDTH>& target) {
target.addResource(txdata, 0x0UL);
target.addResource(rxdata, 0x4UL);
target.addResource(txctrl, 0x8UL);

+ 10
- 0
riscv.sc/incl/sysc/SiFive/gpio.h View File

@ -18,24 +18,34 @@
#define _GPIO_H_
#include "scc/tlm_target.h"
#include <sysc/communication/sc_signal_rv_ports.h>
namespace sysc {
class gpio_regs;
class WsHandler;
class gpio : public sc_core::sc_module, public scc::tlm_target<> {
public:
SC_HAS_PROCESS(gpio);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
sc_core::sc_inout_rv<32> pins_io;
gpio(sc_core::sc_module_name nm);
virtual ~gpio() override; // need to keep it in source file because of fwd declaration of gpio_regs
protected:
void clock_cb();
void reset_cb();
void update_pins();
void pins_cb();
sc_core::sc_time clk;
std::unique_ptr<gpio_regs> regs;
std::shared_ptr<sysc::WsHandler> handler;
private:
void update_value_reg();
};
} /* namespace sysc */

+ 4
- 3
riscv.sc/incl/sysc/SiFive/platform.h View File

@ -48,8 +48,8 @@ public:
SiFive::core_complex i_core_complex;
scc::router<> i_router;
uart i_uart0, i_uart1;
spi i_spi;
gpio i_gpio;
spi i_qspi0, i_qspi1, i_qspi2;
gpio i_gpio0;
plic i_plic;
aon i_aon;
prci i_prci;
@ -59,8 +59,9 @@ public:
scc::memory<128_kB, 32> i_mem_ram;
sc_core::sc_signal<sc_core::sc_time> s_clk;
sc_core::sc_signal<bool> s_rst, s_mtime_int, s_msie_int;
sc_core::sc_vector<sc_core::sc_signal<bool>> s_global_int;
sc_core::sc_vector<sc_core::sc_signal<bool>> s_global_int, s_local_int;
sc_core::sc_signal<bool> s_core_int;
sc_core::sc_signal_rv<32> s_gpio_pins;
platform(sc_core::sc_module_name nm);

+ 2
- 0
riscv.sc/incl/sysc/SiFive/uart.h View File

@ -22,6 +22,7 @@
namespace sysc {
class uart_regs;
class WsHandler;
class uart : public sc_core::sc_module, public scc::tlm_target<> {
public:
@ -38,6 +39,7 @@ protected:
sc_core::sc_time clk;
std::unique_ptr<uart_regs> regs;
std::vector<uint8_t> queue;
std::shared_ptr<sysc::WsHandler> handler;
};
} /* namespace sysc */

+ 82
- 0
riscv.sc/incl/sysc/sc_comm_singleton.h View File

@ -0,0 +1,82 @@
/*
* sc_singleton.h
*
* Created on: 09.10.2017
* Author: eyck
*/
#ifndef RISCV_SC_INCL_SYSC_SC_COMM_SINGLETON_H_
#define RISCV_SC_INCL_SYSC_SC_COMM_SINGLETON_H_
#include <sysc/kernel/sc_module.h>
#include <seasocks/PageHandler.h>
#include "seasocks/WebSocket.h"
#include <memory>
#include <thread>
#include <cstring>
namespace sysc {
class WsHandler: public seasocks::WebSocket::Handler {
public:
explicit WsHandler() { }
void onConnect(seasocks::WebSocket* connection) override;
void onData(seasocks::WebSocket* connection, const char* data) override;
void onDisconnect(seasocks::WebSocket* connection) override;
void send(std::string msg) { for (auto *con : _connections) con->send(msg); }
void set_receive_callback(std::function<void(const char* data)> cb){callback=cb;}
private:
std::set<seasocks::WebSocket*> _connections;
std::function<void(const char* data)> callback;
};
class sc_comm_singleton: public sc_core::sc_module {
struct DefaultPageHandler: public seasocks::PageHandler {
DefaultPageHandler(sc_comm_singleton& o):owner(o){}
virtual std::shared_ptr<seasocks::Response> handle(const seasocks::Request& request);
sc_comm_singleton& owner;
};
public:
sc_comm_singleton() = delete;
sc_comm_singleton(const sc_comm_singleton&) = delete;
sc_comm_singleton& operator=(sc_comm_singleton& o) = delete;
virtual ~sc_comm_singleton();
static sc_comm_singleton& inst(){
static sc_comm_singleton i("__sc_singleton");
return i;
}
seasocks::Server& get_server();
void registerWebSocketHandler(const char* endpoint, std::shared_ptr<seasocks::WebSocket::Handler> handler, bool allowCrossOriginRequests = false);
void execute(std::function<void()> f);
void start_client();
protected:
void start_of_simulation() override;
void end_of_simulation() override;
private:
sc_comm_singleton(sc_core::sc_module_name nm);
std::unique_ptr<seasocks::Server> m_serv;
std::thread t;
void thread_func();
bool client_started;
};
} /* namespace sysc */
#endif /* RISCV_SC_INCL_SYSC_SC_COMM_SINGLETON_H_ */

+ 0
- 49
riscv.sc/incl/sysc/sc_singleton.h View File

@ -1,49 +0,0 @@
/*
* sc_singleton.h
*
* Created on: 09.10.2017
* Author: eyck
*/
#ifndef RISCV_SC_INCL_SYSC_SC_SINGLETON_H_
#define RISCV_SC_INCL_SYSC_SC_SINGLETON_H_
#include <sysc/kernel/sc_module.h>
#include <memory>
#include <thread>
namespace seasocks {
class Server;
}
namespace sysc {
class sc_singleton: public sc_core::sc_module {
public:
sc_singleton() = delete;
sc_singleton(const sc_singleton&) = delete;
sc_singleton& operator=(sc_singleton& o) = delete;
virtual ~sc_singleton();
static sc_singleton& inst(){
static sc_singleton i("__sc_singleton");
return i;
}
seasocks::Server& get_server();
protected:
void start_of_simulation();
private:
sc_singleton(sc_core::sc_module_name nm);
std::unique_ptr<seasocks::Server> m_serv;
std::thread t;
void thread_func();
};
} /* namespace sysc */
#endif /* RISCV_SC_INCL_SYSC_SC_SINGLETON_H_ */

+ 7
- 3
riscv.sc/src/sc_main.cpp View File

@ -56,11 +56,11 @@ int sc_main(int argc, char *argv[]) {
("elf,l", po::value<std::string>(), "ELF file to load")
("gdb-port,g", po::value<unsigned short>()->default_value(0), "enable gdb server and specify port to use")
("dump-ir", "dump the intermediate representation")
("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run")
("cycles", po::value<int64_t>()->default_value(-1), "number of cycles to run")
("quantum", po::value<unsigned>(), "SystemC quantum time in ns")
("reset,r", po::value<std::string>(), "reset address")
("trace,t", po::value<unsigned>()->default_value(0), "enable tracing, or combintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")
("rv64", "run RV64")
("max_time,m", po::value<std::string>(), "maximum time to run")
("config-file,c", po::value<std::string>()->default_value(""), "configuration file");
// clang-format on
po::variables_map vm;
@ -136,7 +136,11 @@ int sc_main(int argc, char *argv[]) {
///////////////////////////////////////////////////////////////////////////
// run simulation
///////////////////////////////////////////////////////////////////////////
sc_core::sc_start();
if(vm.count("max_time")){
sc_core::sc_time max_time = scc::parse_from_string(vm["max_time"].as<std::string>());
sc_core::sc_start(max_time);
} else
sc_core::sc_start();
if (!sc_core::sc_end_of_simulation_invoked()) sc_core::sc_stop();
return 0;
}

+ 3
- 1
riscv.sc/src/sysc/aon.cpp View File

@ -35,7 +35,9 @@ aon::aon(sc_core::sc_module_name nm)
dont_initialize();
}
void aon::clock_cb() {}
void aon::clock_cb() {
this->clk = clk_i.read();
}
aon::~aon() {}

+ 10
- 6
riscv.sc/src/sysc/clint.cpp View File

@ -17,6 +17,7 @@
#include "sysc/SiFive/clint.h"
#include "scc/utilities.h"
#include "scc/report.h"
#include "sysc/SiFive/gen/clint_regs.h"
namespace sysc {
@ -63,7 +64,7 @@ clint::clint(sc_core::sc_module_name nm)
void clint::clock_cb() {
update_mtime();
clk = clk_i.read();
this->clk = clk_i.read();
update_mtime();
}
@ -85,11 +86,14 @@ void clint::update_mtime() {
regs->r_mtime += (diffi + cnt_fraction) / lfclk_mutiplier;
cnt_fraction = (cnt_fraction + diffi) % lfclk_mutiplier;
mtime_evt.cancel();
if (regs->r_mtimecmp > regs->r_mtime && clk > sc_core::SC_ZERO_TIME) {
sc_core::sc_time next_trigger = (clk * lfclk_mutiplier) * (regs->r_mtimecmp - regs->mtime) - cnt_fraction * clk;
mtime_evt.notify(next_trigger);
} else
mtime_int_o.write(true);
if (regs->r_mtimecmp > 0)
if(regs->r_mtimecmp > regs->r_mtime && clk > sc_core::SC_ZERO_TIME) {
sc_core::sc_time next_trigger = (clk * lfclk_mutiplier) * (regs->r_mtimecmp - regs->mtime) - cnt_fraction * clk;
LOG(DEBUG)<<"Timer fires at "<< sc_time_stamp()+next_trigger;
mtime_evt.notify(next_trigger);
mtime_int_o.write(false);
} else
mtime_int_o.write(true);
last_updt = sc_core::sc_time_stamp();
}

+ 66
- 12
riscv.sc/src/sysc/core_complex.cpp View File

@ -108,22 +108,53 @@ public:
};
iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) {
if (addr.type & iss::DEBUG)
return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
else {
return owner->read_mem(addr.val, length, data,addr.type && iss::FETCH) ? iss::Ok : iss::Err;
}
if (addr.type & iss::DEBUG)
return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
else {
return owner->read_mem(addr.val, length, data,addr.type && iss::FETCH) ? iss::Ok : iss::Err;
}
}
iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) {
if (addr.type & iss::DEBUG)
return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
else
return owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
if (addr.type & iss::DEBUG)
return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
else{
auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
// TODO: this is an ugly hack (clear MTIP on mtimecmp write), needs to be fixed
if(addr.val==0x2004000)
this->csr[iss::arch::mip] &= ~(1ULL<<7);
return res;
}
}
void wait_until(uint64_t flags) {
do{
wait(wfi_evt);
this->check_interrupt();
} while(this->reg.pending_trap==0);
base_type::wait_until(flags);
}
void local_irq(short id){
switch(id){
case 16: // SW
this->csr[iss::arch::mip] |= 1<<3;
break;
case 17: // timer
this->csr[iss::arch::mip] |= 1<<7;
break;
case 18: //external
this->csr[iss::arch::mip] |= 1<<11;
break;
default:
/* do nothing*/