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Updated SC-Components

Eyck Jentzsch 1 month ago
parent
commit
eb8365f4c3

+ 0
- 7
README.md View File

@@ -10,16 +10,9 @@ The implementation is based on LLVM 4.0. Eclipse CDT 4.7 (Oxygen) is recommended
10 10
 
11 11
 DBT-RISE-RISCV uses libGIS (https://github.com/vsergeev/libGIS) as well as ELFIO (http://elfio.sourceforge.net/), both under MIT license 
12 12
 
13
-**What's missing**
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-
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-* F & D standard extensions for 32bit to be implemented
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-* MACF &D standard extensions for 64bit to be implemented and verified
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-
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 **Planned features**
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 * add platform peripherals beyond programmers view to resemble E300 platform
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-  * QSPI
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-  * PWM
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   * ...
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 * and more
25 18
 

+ 1
- 1
platform/src/sysc/plic.cpp View File

@@ -50,7 +50,7 @@ plic::plic(sc_core::sc_module_name nm)
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 {
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     regs->registerResources(*this);
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     // register callbacks
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-    regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t> reg, uint32_t v, sc_core::sc_time d) -> bool {
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+    regs->claim_complete.set_write_cb([this](scc::sc_register<uint32_t>& reg, const uint32_t& v, sc_core::sc_time d) -> bool {
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         reg.put(v);
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         reset_pending_int(v);
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         // std::cout << "Value of register: 0x" << std::hex << reg << std::endl;

+ 6
- 6
platform/src/sysc/pwm.cpp View File

@@ -51,14 +51,14 @@ pwm::pwm(sc_core::sc_module_name nm)
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     regs->registerResources(*this);
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     regs->pwmcfg.set_write_cb(
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-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
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+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
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             if (d.value()) wait(d);
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             reg.put(data);
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             update_counter();
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             return true;
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         });
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     regs->pwmcount.set_write_cb(
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-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
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+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
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             if (d.value()) wait(d);
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             reg.put(data);
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             update_counter();
@@ -83,25 +83,25 @@ pwm::pwm(sc_core::sc_module_name nm)
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         return true;
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     });
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     regs->pwmcmp0.set_write_cb(
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-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
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+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
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             reg.put(data);
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             update_counter();
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             return true;
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         });
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     regs->pwmcmp1.set_write_cb(
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-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
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+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
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             reg.put(data);
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             update_counter();
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             return true;
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         });
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     regs->pwmcmp2.set_write_cb(
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-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
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+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
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             reg.put(data);
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             update_counter();
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             return true;
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         });
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     regs->pwmcmp3.set_write_cb(
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-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
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+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
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             reg.put(data);
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             update_counter();
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             return true;

+ 3
- 3
platform/src/sysc/spi.cpp View File

@@ -124,7 +124,7 @@ beh::beh(sc_core::sc_module_name nm)
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         return true;
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     });
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     regs->csmode.set_write_cb(
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-        [this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
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+        [this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
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             if (regs->r_csmode.mode == 2 && regs->r_csmode.mode != bit_sub<0, 2>(data) && regs->r_csid < 4) {
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                 tlm::tlm_phase phase(tlm::BEGIN_REQ);
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                 sc_core::sc_time delay(SC_ZERO_TIME);
@@ -136,7 +136,7 @@ beh::beh(sc_core::sc_module_name nm)
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             reg.put(data);
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             return true;
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         });
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-    regs->csid.set_write_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
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+    regs->csid.set_write_cb([this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
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         if (regs->r_csmode.mode == 2 && regs->csid != data && regs->r_csid < 4) {
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             tlm::tlm_phase phase(tlm::BEGIN_REQ);
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             sc_core::sc_time delay(SC_ZERO_TIME);
@@ -148,7 +148,7 @@ beh::beh(sc_core::sc_module_name nm)
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         reg.put(data);
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         return true;
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     });
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-    regs->csdef.set_write_cb([this](const scc::sc_register<uint32_t> &reg, uint32_t &data, sc_core::sc_time d) -> bool {
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+    regs->csdef.set_write_cb([this](const scc::sc_register<uint32_t> &reg, const uint32_t &data, sc_core::sc_time d) -> bool {
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         auto diff = regs->csdef ^ data;
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         if (regs->r_csmode.mode == 2 && diff != 0 && (regs->r_csid < 4) && (diff & (1 << regs->r_csid)) != 0) {
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             tlm::tlm_phase phase(tlm::BEGIN_REQ);

+ 1
- 0
riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl View File

@@ -38,6 +38,7 @@
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 #include <iss/llvm/vm_base.h>
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 #include <util/logging.h>
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+#define FMT_HEADER_ONLY
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 #include <fmt/format.h>
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 #include <array>

+ 1
- 0
riscv/incl/iss/arch/riscv_hart_msu_vp.h View File

@@ -40,6 +40,7 @@
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 #include "iss/instrumentation_if.h"
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 #include "iss/log_categories.h"
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 #include "iss/vm_if.h"
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+#define FMT_HEADER_ONLY
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 #include <fmt/format.h>
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 #include <array>
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 #include <elfio/elfio.hpp>

+ 1
- 0
riscv/incl/iss/debugger/riscv_target_adapter.h View File

@@ -40,6 +40,7 @@
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 #include <array>
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 #include <memory>
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+#define FMT_HEADER_ONLY
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 #include <fmt/format.h>
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 #include <util/logging.h>
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+ 1
- 0
riscv/src/internal/vm_rv32gc.cpp View File

@@ -38,6 +38,7 @@
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 #include <iss/llvm/vm_base.h>
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 #include <util/logging.h>
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41
+#define FMT_HEADER_ONLY
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 #include <fmt/format.h>
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 #include <array>

+ 1
- 0
riscv/src/internal/vm_rv32imac.cpp View File

@@ -38,6 +38,7 @@
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 #include <iss/llvm/vm_base.h>
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 #include <util/logging.h>
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+#define FMT_HEADER_ONLY
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 #include <fmt/format.h>
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 #include <array>

+ 1
- 0
riscv/src/internal/vm_rv64gc.cpp View File

@@ -38,6 +38,7 @@
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 #include <iss/llvm/vm_base.h>
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 #include <util/logging.h>
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+#define FMT_HEADER_ONLY
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 #include <fmt/format.h>
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 #include <array>

+ 1
- 0
riscv/src/internal/vm_rv64i.cpp View File

@@ -38,6 +38,7 @@
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 #include <iss/llvm/vm_base.h>
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 #include <util/logging.h>
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+#define FMT_HEADER_ONLY
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 #include <fmt/format.h>
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 #include <array>

+ 1
- 1
sc-components

@@ -1 +1 @@
1
-Subproject commit 05ba88052cf922b1e93550342d8e297338619b5d
1
+Subproject commit 7c989da05673bb40e1358561d51b86e71c1ac68c