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Refactored arch_if to save unneeded constructor calls

Eyck Jentzsch 9 months ago
parent
commit
d160a34c5d
3 changed files with 52 additions and 43 deletions
  1. 1
    1
      dbt-core
  2. 49
    41
      riscv/incl/iss/arch/riscv_hart_msu_vp.h
  3. 2
    1
      riscv/incl/iss/debugger/riscv_target_adapter.h

+ 1
- 1
dbt-core

@@ -1 +1 @@
1
-Subproject commit 54cf894c3f3897a57f366905345514f5e94a5166
1
+Subproject commit d73fee68dd164c016721ae76d1538136513e6b37

+ 49
- 41
riscv/incl/iss/arch/riscv_hart_msu_vp.h View File

@@ -467,8 +467,10 @@ public:
467 467
 
468 468
     virtual phys_addr_t virt2phys(const iss::addr_t &addr) override;
469 469
 
470
-    iss::status read(const iss::addr_t &addr, unsigned length, uint8_t *const data) override;
471
-    iss::status write(const iss::addr_t &addr, unsigned length, const uint8_t *const data) override;
470
+    iss::status read(const address_type type, const access_type access, const uint32_t space,
471
+            const uint64_t addr, const unsigned length, uint8_t *const data) override;
472
+    iss::status write(const address_type type, const access_type access, const uint32_t space,
473
+            const uint64_t addr, const unsigned length, const uint8_t *const data) override;
472 474
 
473 475
     virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data); }
474 476
     virtual uint64_t enter_trap(uint64_t flags, uint64_t addr) override;
@@ -624,9 +626,9 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
624 626
                 const auto fsize = pseg->get_file_size(); // 0x42c/0x0
625 627
                 const auto seg_data = pseg->get_data();
626 628
                 if (fsize > 0) {
627
-                    auto res = this->write(
628
-                        phys_addr_t(iss::access_type::DEBUG_WRITE, traits<BASE>::MEM, pseg->get_physical_address()),
629
-                        fsize, reinterpret_cast<const uint8_t *const>(seg_data));
629
+                    auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE,
630
+                            traits<BASE>::MEM, pseg->get_physical_address(),
631
+                            fsize, reinterpret_cast<const uint8_t *const>(seg_data));
630 632
                     if (res != iss::Ok)
631 633
                         LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex
632 634
                                    << pseg->get_physical_address();
@@ -647,36 +649,39 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
647 649
 }
648 650
 
649 651
 template <typename BASE>
650
-iss::status riscv_hart_msu_vp<BASE>::read(const iss::addr_t &addr, unsigned length, uint8_t *const data) {
652
+iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_type access, const uint32_t space,
653
+        const uint64_t addr, const unsigned length, uint8_t *const data) {
651 654
 #ifndef NDEBUG
652
-    if (addr.access && iss::access_type::DEBUG) {
655
+    if (access && iss::access_type::DEBUG) {
653 656
         LOG(TRACE) << "debug read of " << length << " bytes @addr " << addr;
654 657
     } else {
655 658
         LOG(TRACE) << "read of " << length << " bytes  @addr " << addr;
656 659
     }
657 660
 #endif
658 661
     try {
659
-        switch (addr.space) {
662
+        switch (space) {
660 663
         case traits<BASE>::MEM: {
661
-            if (unlikely((addr.access == iss::access_type::FETCH || addr.access == iss::access_type::DEBUG_FETCH) && (addr.val & 0x1) == 1)) {
662
-                fault_data = addr.val;
663
-                if (addr.access && iss::access_type::DEBUG) throw trap_access(0, addr.val);
664
+            if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
665
+                fault_data = addr;
666
+                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
664 667
                 this->reg.trap_state = (1 << 31); // issue trap 0
665 668
                 return iss::Err;
666 669
             }
667 670
             try {
668
-                if (unlikely((addr.val & ~PGMASK) != ((addr.val + length - 1) & ~PGMASK))) { // we may cross a page boundary
671
+                if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
669 672
                     vm_info vm = hart_state<reg_t>::decode_vm_info(this->reg.machine_state, state.satp);
670 673
                     if (vm.levels != 0) { // VM is active
671
-                        auto split_addr = (addr.val + length) & ~PGMASK;
672
-                        auto len1 = split_addr - addr.val;
673
-                        auto res = read(addr, len1, data);
674
+                        auto split_addr = (addr + length) & ~PGMASK;
675
+                        auto len1 = split_addr - addr;
676
+                        auto res = read(type, access, space, addr, len1, data);
674 677
                         if (res == iss::Ok)
675
-                            res = read(iss::addr_t{addr.access, addr.type, addr.space, split_addr}, length - len1, data + len1);
678
+                            res = read(type, access, space, split_addr, length - len1, data + len1);
676 679
                         return res;
677 680
                     }
678 681
                 }
679
-                auto res = read_mem( BASE::v2p(addr), length, data);
682
+                auto res = type==iss::address_type::PHYSICAL?
683
+                        read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
684
+                        read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
680 685
                 if (unlikely(res != iss::Ok)) this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
681 686
                 return res;
682 687
             } catch (trap_access &ta) {
@@ -686,11 +691,11 @@ iss::status riscv_hart_msu_vp<BASE>::read(const iss::addr_t &addr, unsigned leng
686 691
         } break;
687 692
         case traits<BASE>::CSR: {
688 693
             if (length != sizeof(reg_t)) return iss::Err;
689
-            return read_csr(addr.val, *reinterpret_cast<reg_t *const>(data));
694
+            return read_csr(addr, *reinterpret_cast<reg_t *const>(data));
690 695
         } break;
691 696
         case traits<BASE>::FENCE: {
692
-            if ((addr.val + length) > mem.size()) return iss::Err;
693
-            switch (addr.val) {
697
+            if ((addr + length) > mem.size()) return iss::Err;
698
+            switch (addr) {
694 699
             case 2:   // SFENCE:VMA lower
695 700
             case 3: { // SFENCE:VMA upper
696 701
                 auto tvm = state.mstatus.TVM;
@@ -704,10 +709,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const iss::addr_t &addr, unsigned leng
704 709
             }
705 710
         } break;
706 711
         case traits<BASE>::RES: {
707
-            auto it = atomic_reservation.find(addr.val);
712
+            auto it = atomic_reservation.find(addr);
708 713
             if (it != atomic_reservation.end() && it->second != 0) {
709 714
                 memset(data, 0xff, length);
710
-                atomic_reservation.erase(addr.val);
715
+                atomic_reservation.erase(addr);
711 716
             } else
712 717
                 memset(data, 0, length);
713 718
         } break;
@@ -722,9 +727,10 @@ iss::status riscv_hart_msu_vp<BASE>::read(const iss::addr_t &addr, unsigned leng
722 727
 }
723 728
 
724 729
 template <typename BASE>
725
-iss::status riscv_hart_msu_vp<BASE>::write(const iss::addr_t &addr, unsigned length, const uint8_t *const data) {
730
+iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access_type access, const uint32_t space,
731
+        const uint64_t addr, const unsigned length, const uint8_t *const data) {
726 732
 #ifndef NDEBUG
727
-    const char *prefix = (addr.access && iss::access_type::DEBUG) ? "debug " : "";
733
+    const char *prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
728 734
     switch (length) {
729 735
     case 8:
730 736
         LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t *)&data[0] << std::dec
@@ -747,27 +753,29 @@ iss::status riscv_hart_msu_vp<BASE>::write(const iss::addr_t &addr, unsigned len
747 753
     }
748 754
 #endif
749 755
     try {
750
-        switch (addr.space) {
756
+        switch (space) {
751 757
         case traits<BASE>::MEM: {
752
-            if (unlikely((addr.access && iss::access_type::FETCH) && (addr.val & 0x1) == 1)) {
753
-                fault_data = addr.val;
754
-                if (addr.access && iss::access_type::DEBUG) throw trap_access(0, addr.val);
758
+            if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
759
+                fault_data = addr;
760
+                if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
755 761
                 this->reg.trap_state = (1 << 31); // issue trap 0
756 762
                 return iss::Err;
757 763
             }
758 764
             try {
759
-                if (unlikely((addr.val & ~PGMASK) != ((addr.val + length - 1) & ~PGMASK))) { // we may cross a page boundary
765
+                if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
760 766
                     vm_info vm = hart_state<reg_t>::decode_vm_info(this->reg.machine_state, state.satp);
761 767
                     if (vm.levels != 0) { // VM is active
762
-                        auto split_addr = (addr.val + length) & ~PGMASK;
763
-                        auto len1 = split_addr - addr.val;
764
-                        auto res = write(addr, len1, data);
768
+                        auto split_addr = (addr + length) & ~PGMASK;
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+                        auto len1 = split_addr - addr;
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+                        auto res = write(type, access, space, addr, len1, data);
765 771
                         if (res == iss::Ok)
766
-                            res = write(iss::addr_t{addr.access, addr.type, addr.space, split_addr}, length - len1, data + len1);
772
+                            res = write(type, access, space, split_addr, length - len1, data + len1);
767 773
                         return res;
768 774
                     }
769 775
                 }
770
-                auto res = write_mem(BASE::v2p(addr), length, data);
776
+                auto res = type==iss::address_type::PHYSICAL?
777
+                        write_mem(phys_addr_t{access, space, addr}, length, data):
778
+                        write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
771 779
                 if (unlikely(res != iss::Ok))
772 780
                     this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 7 (Store/AMO access fault)
773 781
                 return res;
@@ -776,7 +784,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const iss::addr_t &addr, unsigned len
776 784
                 return iss::Err;
777 785
             }
778 786
 
779
-            phys_addr_t paddr = BASE::v2p(addr);
787
+            phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
780 788
             if ((paddr.val + length) > mem.size()) return iss::Err;
781 789
             switch (paddr.val) {
782 790
             case 0x10013000: // UART0 base, TXFIFO reg
@@ -810,11 +818,11 @@ iss::status riscv_hart_msu_vp<BASE>::write(const iss::addr_t &addr, unsigned len
810 818
         } break;
811 819
         case traits<BASE>::CSR: {
812 820
             if (length != sizeof(reg_t)) return iss::Err;
813
-            return write_csr(addr.val, *reinterpret_cast<const reg_t *>(data));
821
+            return write_csr(addr, *reinterpret_cast<const reg_t *>(data));
814 822
         } break;
815 823
         case traits<BASE>::FENCE: {
816
-            if ((addr.val + length) > mem.size()) return iss::Err;
817
-            switch (addr.val) {
824
+            if ((addr + length) > mem.size()) return iss::Err;
825
+            switch (addr) {
818 826
             case 2:
819 827
             case 3: {
820 828
                 ptw.clear();
@@ -829,7 +837,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const iss::addr_t &addr, unsigned len
829 837
             }
830 838
         } break;
831 839
         case traits<BASE>::RES: {
832
-            atomic_reservation[addr.val] = data[0];
840
+            atomic_reservation[addr] = data[0];
833 841
         } break;
834 842
         default:
835 843
             return iss::Err;
@@ -1182,8 +1190,8 @@ typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_hart_msu_vp<BASE>::virt2phys
1182 1190
 
1183 1191
             // check that physical address of PTE is legal
1184 1192
             reg_t pte = 0;
1185
-            const uint8_t res = this->read(phys_addr_t{addr.access, traits<BASE>::MEM, base + idx * vm.ptesize},
1186
-                                           vm.ptesize, (uint8_t *)&pte);
1193
+            const uint8_t res = this->read(iss::address_type::PHYSICAL, addr.access,
1194
+                    traits<BASE>::MEM, base + idx * vm.ptesize, vm.ptesize, (uint8_t *)&pte);
1187 1195
             if (res != 0) throw trap_load_access_fault(addr.val);
1188 1196
             const reg_t ppn = pte >> PTE_PPN_SHIFT;
1189 1197
 

+ 2
- 1
riscv/incl/iss/debugger/riscv_target_adapter.h View File

@@ -269,7 +269,8 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::read_mem(uint64_t ad
269 269
 
270 270
 template <typename ARCH> status riscv_target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t> &data) {
271 271
     auto a = map_addr({iss::access_type::DEBUG_READ, iss::address_type::VIRTUAL, 0, addr});
272
-    return srv->execute_syncronized(&arch_if::write, core, a, data.size(), data.data());
272
+    auto f = [&]() -> status { return core->write(a, data.size(), data.data()); };
273
+    return srv->execute_syncronized(f);
273 274
 }
274 275
 
275 276
 template <typename ARCH>