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DBT-RISE-RISCV
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[WIP]

master
Eyck Jentzsch 1 year ago
parent
10797a473d
commit
abcfb75011
13 changed files with 2356 additions and 3079 deletions
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  1. +3
    -4
      CMakeLists.txt
  2. +10
    -10
      gen_input/RVF.core_desc
  3. +5
    -5
      gen_input/RVM.core_desc
  4. +3
    -0
      gen_input/minres_rv.core_desc
  5. +11
    -12
      incl/iss/arch/riscv_hart_msu_vp.h
  6. +1
    -1
      incl/iss/arch/rv32gc.h
  7. +1
    -1
      incl/iss/arch/rv32imac.h
  8. +1
    -1
      incl/iss/arch/rv64gc.h
  9. +167
    -236
      src/vm/tcc/vm_mnrv32.cpp
  10. +736
    -948
      src/vm/tcc/vm_rv32gc.cpp
  11. +283
    -388
      src/vm/tcc/vm_rv32imac.cpp
  12. +957
    -1235
      src/vm/tcc/vm_rv64gc.cpp
  13. +178
    -238
      src/vm/tcc/vm_rv64i.cpp

+ 3
- 4
CMakeLists.txt View File

@ -61,11 +61,11 @@ set(LIB_SOURCES ${LIB_SOURCES}
endif()
# Define the library
add_library(riscv ${LIB_SOURCES})
SET(riscv -Wl,-whole-archive -lriscv -Wl,-no-whole-archive)
add_library(riscv SHARED ${LIB_SOURCES})
target_compile_options(riscv PRIVATE -Wno-shift-count-overflow)
target_include_directories(riscv PUBLIC incl ../external/elfio)
target_link_libraries(riscv PUBLIC softfloat dbt-core scc-util)
target_link_libraries(riscv PUBLIC softfloat scc-util)
target_link_libraries(riscv PUBLIC -Wl,--whole-archive dbt-core -Wl,--no-whole-archive)
set_target_properties(riscv PROPERTIES
VERSION ${PROJECT_VERSION}
FRAMEWORK FALSE
@ -104,7 +104,6 @@ endif()
# Links the target exe against the libraries
target_link_libraries(riscv-sim riscv)
target_link_libraries(riscv-sim jsoncpp)
target_link_libraries(riscv-sim dbt-core)
target_link_libraries(riscv-sim external)
target_link_libraries(riscv-sim ${Boost_LIBRARIES} )
if (Tcmalloc_FOUND)

+ 10
- 10
gen_input/RVF.core_desc View File

@ -10,7 +10,7 @@ InsructionSet RV32F extends RV32I{
instructions{
FLW {
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
args_disass:"f{rd}, {imm}(x{rs1})";
args_disass:"f{rd}, {imm}({name(rs1)})";
val offs[XLEN] <= X[rs1]'s + imm;
val res[32] <= MEM[offs]{32};
if(FLEN==32)
@ -22,13 +22,13 @@ InsructionSet RV32F extends RV32I{
}
FSW {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
args_disass:"f{rs2}, {imm}(x{rs1})";
args_disass:"f{rs2}, {imm}({name(rs1)])";
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{32}<=F[rs2]{32};
}
FMADD.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
if(FLEN==32)
F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
@ -45,7 +45,7 @@ InsructionSet RV32F extends RV32I{
}
FMSUB.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
if(FLEN==32)
F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
@ -62,7 +62,7 @@ InsructionSet RV32F extends RV32I{
}
FNMADD.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
args_disass:"name(rd), f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
if(FLEN==32)
F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
@ -79,7 +79,7 @@ InsructionSet RV32F extends RV32I{
}
FNMSUB.S {
encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
if(FLEN==32)
F[rd] <= fdispatch_fmadd_s(F[rs1], F[rs2], F[rs3], zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
@ -359,7 +359,7 @@ InsructionSet RV64F extends RV32F{
instructions{
FCVT.L.S { // fp to 64bit signed integer
encoding: b1100000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"x{rd}, f{rs1}";
args_disass:"{name(rd)}, f{rs1}";
val res[64] <= fdispatch_fcvt_32_64(fdispatch_unbox_s(F[rs1]), zext(0, 32), rm{8});
X[rd]<= sext(res);
val flags[32] <= fdispatch_fget_flags();
@ -367,7 +367,7 @@ InsructionSet RV64F extends RV32F{
}
FCVT.LU.S { // fp to 64bit unsigned integer
encoding: b1100000 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"x{rd}, f{rs1}";
args_disass:"{name(rd)}, f{rs1}";
val res[64] <= fdispatch_fcvt_32_64(fdispatch_unbox_s(F[rs1]), zext(1, 32), rm{8});
X[rd]<= zext(res);
val flags[32] <= fdispatch_fget_flags();
@ -375,7 +375,7 @@ InsructionSet RV64F extends RV32F{
}
FCVT.S.L { // 64bit signed int to to fp
encoding: b1101000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, x{rs1}";
args_disass:"f{rd}, {name(rs1)}";
val res[32] <= fdispatch_fcvt_64_32(X[rs1], zext(2, 32), rm{8});
if(FLEN==32)
F[rd] <= res;
@ -386,7 +386,7 @@ InsructionSet RV64F extends RV32F{
}
FCVT.S.LU { // 64bit unsigned int to to fp
encoding: b1101000 | b00011 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
args_disass:"f{rd}, x{rs1}";
args_disass:"f{rd}, {name(rs1)}";
val res[32] <=fdispatch_fcvt_64_32(X[rs1], zext(3,32), rm{8});
if(FLEN==32)
F[rd] <= res;

+ 5
- 5
gen_input/RVM.core_desc View File

@ -2,14 +2,14 @@ import "RISCVBase.core_desc"
InsructionSet RV32M extends RISCVBase {
constants {
MAXLEN:=128
MUL_LEN
}
instructions{
MUL{
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
val res[MUL_LEN] <= zext(X[rs1], MUL_LEN) * zext(X[rs2], MUL_LEN);
X[rd]<= zext(res , XLEN);
}
}
@ -17,7 +17,7 @@ InsructionSet RV32M extends RISCVBase {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN);
val res[MUL_LEN] <= sext(X[rs1], MUL_LEN) * sext(X[rs2], MUL_LEN);
X[rd]<= zext(res >> XLEN, XLEN);
}
}
@ -25,7 +25,7 @@ InsructionSet RV32M extends RISCVBase {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val res[MAXLEN] <= sext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
val res[MUL_LEN] <= sext(X[rs1], MUL_LEN) * zext(X[rs2], MUL_LEN);
X[rd]<= zext(res >> XLEN, XLEN);
}
}
@ -33,7 +33,7 @@ InsructionSet RV32M extends RISCVBase {
encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
if(rd != 0){
val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
val res[MUL_LEN] <= zext(X[rs1], MUL_LEN) * zext(X[rs2], MUL_LEN);
X[rd]<= zext(res >> XLEN, XLEN);
}
}

+ 3
- 0
gen_input/minres_rv.core_desc View File

@ -22,6 +22,7 @@ Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
constants {
XLEN:=32;
PCLEN:=32;
MUL_LEN:=64;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100000101;
@ -35,6 +36,7 @@ Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
XLEN:=32;
FLEN:=64;
PCLEN:=32;
MUL_LEN:=64;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100101101;
@ -60,6 +62,7 @@ Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV64IC, RV32FC, RV32DC {
XLEN:=64;
FLEN:=64;
PCLEN:=64;
MUL_LEN:=128;
// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100101101;

+ 11
- 12
incl/iss/arch/riscv_hart_msu_vp.h View File

@ -857,6 +857,8 @@ iss::status riscv_hart_msu_vp::write(const address_type type, const access
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_csr(unsigned addr, reg_t &val) {
if (addr >= csr.size()) return iss::Err;
auto req_priv_lvl = (addr >> 8) & 0x3;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
auto it = csr_rd_cb.find(addr);
if (it == csr_rd_cb.end()) {
val = csr[addr & csr.page_addr_mask];
@ -869,6 +871,11 @@ template iss::status riscv_hart_msu_vp::read_csr(unsigned
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_csr(unsigned addr, reg_t val) {
if (addr >= csr.size()) return iss::Err;
auto req_priv_lvl = (addr >> 8) & 0x3;
if (this->reg.machine_state < req_priv_lvl)
throw illegal_instruction_fault(this->fault_data);
if((addr&0xc00)==0xc00)
throw illegal_instruction_fault(this->fault_data);
auto it = csr_wr_cb.find(addr);
if (it == csr_wr_cb.end()) {
csr[addr & csr.page_addr_mask] = val;
@ -902,15 +909,13 @@ template iss::status riscv_hart_msu_vp::read_time(unsigned
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_status(unsigned addr, reg_t &val) {
auto req_priv_lvl = addr >> 8;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
auto req_priv_lvl = (addr >> 8) & 0x3;
val = state.mstatus & hart_state<reg_t>::get_mask(req_priv_lvl);
return iss::Ok;
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_status(unsigned addr, reg_t val) {
auto req_priv_lvl = addr >> 8;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
auto req_priv_lvl = (addr >> 8) & 0x3;
state.write_mstatus(val, req_priv_lvl);
check_interrupt();
update_vm_info();
@ -918,8 +923,6 @@ template iss::status riscv_hart_msu_vp::write_status(unsig
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ie(unsigned addr, reg_t &val) {
auto req_priv_lvl = addr >> 8;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
val = csr[mie];
if (addr < mie) val &= csr[mideleg];
if (addr < sie) val &= csr[sideleg];
@ -927,8 +930,7 @@ template iss::status riscv_hart_msu_vp::read_ie(unsigned a
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ie(unsigned addr, reg_t val) {
auto req_priv_lvl = addr >> 8;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
auto req_priv_lvl = (addr >> 8) & 0x3;
auto mask = get_irq_mask(req_priv_lvl);
csr[mie] = (csr[mie] & ~mask) | (val & mask);
check_interrupt();
@ -936,8 +938,6 @@ template iss::status riscv_hart_msu_vp::write_ie(unsigned
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_ip(unsigned addr, reg_t &val) {
auto req_priv_lvl = addr >> 8;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
val = csr[mip];
if (addr < mip) val &= csr[mideleg];
if (addr < sip) val &= csr[sideleg];
@ -945,8 +945,7 @@ template iss::status riscv_hart_msu_vp::read_ip(unsigned a
}
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_ip(unsigned addr, reg_t val) {
auto req_priv_lvl = addr >> 8;
if (this->reg.machine_state < req_priv_lvl) throw illegal_instruction_fault(this->fault_data);
auto req_priv_lvl = (addr >> 8) & 0x3;
auto mask = get_irq_mask(req_priv_lvl);
mask &= ~(1 << 7); // MTIP is read only
csr[mip] = (csr[mip] & ~mask) | (val & mask);

+ 1
- 1
incl/iss/arch/rv32gc.h View File

@ -54,7 +54,7 @@ template <> struct traits {
static constexpr std::array<const char*, 66> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}};
enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
enum constants {XLEN=32, FLEN=64, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
constexpr static unsigned FP_REGS_SIZE = 64;

+ 1
- 1
incl/iss/arch/rv32imac.h View File

@ -54,7 +54,7 @@ template <> struct traits {
static constexpr std::array<const char*, 33> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000101000001000100000101, PGSIZE=0x1000, PGMASK=0xfff};
enum constants {XLEN=32, PCLEN=32, MUL_LEN=64, MISA_VAL=0b1000000000101000001000100000101, PGSIZE=0x1000, PGMASK=0xfff};
constexpr static unsigned FP_REGS_SIZE = 0;

+ 1
- 1
incl/iss/arch/rv64gc.h View File

@ -54,7 +54,7 @@ template <> struct traits {
static constexpr std::array<const char*, 66> reg_aliases{
{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}};
enum constants {XLEN=64, FLEN=64, PCLEN=64, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
enum constants {XLEN=64, FLEN=64, PCLEN=64, MUL_LEN=128, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
constexpr static unsigned FP_REGS_SIZE = 64;

+ 167
- 236
src/vm/tcc/vm_mnrv32.cpp
File diff suppressed because it is too large
View File


+ 736
- 948
src/vm/tcc/vm_rv32gc.cpp
File diff suppressed because it is too large
View File


+ 283
- 388
src/vm/tcc/vm_rv32imac.cpp
File diff suppressed because it is too large
View File


+ 957
- 1235
src/vm/tcc/vm_rv64gc.cpp
File diff suppressed because it is too large
View File


+ 178
- 238
src/vm/tcc/vm_rv64i.cpp
File diff suppressed because it is too large
View File


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