Browse Source

Cleanup of templates

Eyck Jentzsch 6 months ago
parent
commit
a576fdf8e5

+ 6
- 8
riscv/gen_input/RV32IBase.core_desc View File

@@ -1,8 +1,6 @@
1 1
 InsructionSet RV32IBase {
2 2
     constants {
3 3
         XLEN,
4
-        PCLEN,
5
-        XLEN_BIT_MASK:=0x1f,
6 4
         fence:=0,
7 5
         fencei:=1,
8 6
         fencevmal:=2,
@@ -16,7 +14,7 @@ InsructionSet RV32IBase {
16 14
     registers { 
17 15
         [31:0]   X[XLEN],
18 16
                 PC[XLEN](is_pc),
19
-                alias ZERO[XLEN] is X[0] 
17
+                alias ZERO[XLEN] is X[0]
20 18
     }
21 19
      
22 20
     instructions { 
@@ -197,7 +195,7 @@ InsructionSet RV32IBase {
197 195
         SLL {
198 196
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
199 197
             args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
200
-            if(rd != 0) X[rd] <= shll(X[rs1], X[rs2]&XLEN_BIT_MASK);
198
+            if(rd != 0) X[rd] <= shll(X[rs1], X[rs2]&(XLEN-1));
201 199
         }
202 200
         SLT {
203 201
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
@@ -217,12 +215,12 @@ InsructionSet RV32IBase {
217 215
         SRL {
218 216
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
219 217
             args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
220
-            if(rd != 0) X[rd] <= shrl(X[rs1], X[rs2]&XLEN_BIT_MASK);
218
+            if(rd != 0) X[rd] <= shrl(X[rs1], X[rs2]&(XLEN-1));
221 219
         }
222 220
         SRA {
223 221
             encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
224 222
             args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
225
-            if(rd != 0) X[rd] <= shra(X[rs1], X[rs2]&XLEN_BIT_MASK);
223
+            if(rd != 0) X[rd] <= shra(X[rs1], X[rs2]&(XLEN-1));
226 224
         }
227 225
         OR {
228 226
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
@@ -279,8 +277,8 @@ InsructionSet RV32IBase {
279 277
                 val csr_val[XLEN] <= CSR[csr];
280 278
                 CSR[csr] <= rs_val; 
281 279
                 // make sure Xrd is updated once CSR write succeeds
282
-                   X[rd] <= csr_val;
283
-               } else {
280
+                X[rd] <= csr_val;
281
+            } else {
284 282
                 CSR[csr] <= rs_val;
285 283
             }
286 284
         }

+ 0
- 2
riscv/gen_input/minres_rv.core_desc View File

@@ -9,7 +9,6 @@ import "RV64IBase.core_desc"
9 9
 import "RV64A.core_desc"
10 10
 
11 11
 Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
12
-    template:"vm_riscv.in.cpp";
13 12
     constants {
14 13
         XLEN:=32;
15 14
         PCLEN:=32;
@@ -36,7 +35,6 @@ Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32
36 35
 
37 36
 
38 37
 Core RV64IA provides RV64IBase, RV64A, RV32A {
39
-    template:"vm_riscv.in.cpp";
40 38
     constants {
41 39
         XLEN:=64;
42 40
         PCLEN:=64;

+ 51
- 51
riscv/gen_input/templates/incl-CORENAME.h.gtl View File

@@ -1,34 +1,35 @@
1
-////////////////////////////////////////////////////////////////////////////////
2
-// Copyright (C) 2017, MINRES Technologies GmbH
3
-// All rights reserved.
4
-// 
5
-// Redistribution and use in source and binary forms, with or without
6
-// modification, are permitted provided that the following conditions are met:
7
-// 
8
-// 1. Redistributions of source code must retain the above copyright notice,
9
-//    this list of conditions and the following disclaimer.
10
-// 
11
-// 2. Redistributions in binary form must reproduce the above copyright notice,
12
-//    this list of conditions and the following disclaimer in the documentation
13
-//    and/or other materials provided with the distribution.
14
-// 
15
-// 3. Neither the name of the copyright holder nor the names of its contributors
16
-//    may be used to endorse or promote products derived from this software
17
-//    without specific prior written permission.
18
-// 
19
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
-// POSSIBILITY OF SUCH DAMAGE.
30
-// 
31
-////////////////////////////////////////////////////////////////////////////////
1
+/*******************************************************************************
2
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
3
+ * All rights reserved.
4
+ *
5
+ * Redistribution and use in source and binary forms, with or without
6
+ * modification, are permitted provided that the following conditions are met:
7
+ *
8
+ * 1. Redistributions of source code must retain the above copyright notice,
9
+ *    this list of conditions and the following disclaimer.
10
+ *
11
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
12
+ *    this list of conditions and the following disclaimer in the documentation
13
+ *    and/or other materials provided with the distribution.
14
+ *
15
+ * 3. Neither the name of the copyright holder nor the names of its contributors
16
+ *    may be used to endorse or promote products derived from this software
17
+ *    without specific prior written permission.
18
+ *
19
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+ * POSSIBILITY OF SUCH DAMAGE.
30
+ *
31
+ *******************************************************************************/
32
+
32 33
 <% 
33 34
 import com.minres.coredsl.coreDsl.Register
34 35
 import com.minres.coredsl.coreDsl.RegisterFile
@@ -39,18 +40,17 @@ def getTypeSize(size){
39 40
 #ifndef _${coreDef.name.toUpperCase()}_H_
40 41
 #define _${coreDef.name.toUpperCase()}_H_
41 42
 
43
+#include <array>
44
+#include <iss/arch/traits.h>
42 45
 #include <iss/arch_if.h>
43 46
 #include <iss/vm_if.h>
44
-#include <iss/arch/traits.h>
45
-#include <array>
46 47
 
47 48
 namespace iss {
48 49
 namespace arch {
49 50
 
50 51
 struct ${coreDef.name.toLowerCase()};
51 52
 
52
-template<>
53
-struct traits<${coreDef.name.toLowerCase()}> {
53
+template <> struct traits<${coreDef.name.toLowerCase()}> {
54 54
 
55 55
 	constexpr static char const* const core_type = "${coreDef.name}";
56 56
     
@@ -87,21 +87,21 @@ struct traits<${coreDef.name.toLowerCase()}> {
87 87
 
88 88
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
89 89
 
90
-    constexpr static unsigned reg_bit_width(unsigned r) {
91
-        constexpr std::array<const uint32_t, ${regSizes.size}> ${coreDef.name}_reg_size{{${regSizes.join(",")}}};
92
-        return ${coreDef.name}_reg_size[r];
93
-    }
90
+ 	static constexpr std::array<const uint32_t, ${regSizes.size}> ${coreDef.name}_reg_size{
91
+ 		{${regSizes.join(",")}}};
94 92
 
95
-    constexpr static unsigned reg_byte_offset(unsigned r) {
96
-    	constexpr std::array<const uint32_t, ${regOffsets.size}> ${coreDef.name}_reg_byte_offset{{${regOffsets.join(",")}}};
97
-        return ${coreDef.name}_reg_byte_offset[r];
98
-    }
93
+    static constexpr unsigned reg_bit_width(unsigned r) { return ${coreDef.name}_reg_size[r]; }
94
+
95
+    static constexpr std::array<const uint32_t, ${regOffsets.size}> ${coreDef.name}_reg_byte_offset{
96
+    	{${regOffsets.join(",")}}};
97
+
98
+    constexpr static unsigned reg_byte_offset(unsigned r) { return ${coreDef.name}_reg_byte_offset[r]; }
99 99
 
100 100
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
101 101
 
102
-    enum sreg_flag_e {FLAGS};
102
+    enum sreg_flag_e { FLAGS };
103 103
 
104
-    enum mem_type_e {${allSpaces.collect{s -> s.name}.join(', ')}};
104
+    enum mem_type_e { ${allSpaces.collect{s -> s.name}.join(', ')} };
105 105
 };
106 106
 
107 107
 struct ${coreDef.name.toLowerCase()}: public arch_if {
@@ -126,12 +126,13 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
126 126
     /// deprecated
127 127
     void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
128 128
 
129
-    uint64_t get_icount() { return reg.icount;}
129
+    inline uint64_t get_icount() { return reg.icount; }
130
+
131
+    inline bool should_stop() { return interrupt_sim; }
130 132
 
131 133
     inline phys_addr_t v2p(const iss::addr_t& addr){
132
-        if(addr.space != traits<${coreDef.name.toLowerCase()}>::MEM ||
133
-                addr.type == iss::address_type::PHYSICAL ||
134
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL){
134
+        if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
135
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
135 136
             return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
136 137
         } else
137 138
             return virt2phys(addr);
@@ -141,8 +142,7 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
141 142
 
142 143
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
143 144
 
144
-    inline
145
-    uint32_t get_last_branch(){return reg.last_branch;}
145
+    inline uint32_t get_last_branch() { return reg.last_branch; }
146 146
 
147 147
 protected:
148 148
     struct ${coreDef.name}_regs {<%

+ 42
- 39
riscv/gen_input/templates/src-CORENAME.cpp.gtl View File

@@ -1,34 +1,34 @@
1
-////////////////////////////////////////////////////////////////////////////////
2
-// Copyright (C) 2017,2018 MINRES Technologies GmbH
3
-// All rights reserved.
4
-//
5
-// Redistribution and use in source and binary forms, with or without
6
-// modification, are permitted provided that the following conditions are met:
7
-//
8
-// 1. Redistributions of source code must retain the above copyright notice,
9
-//    this list of conditions and the following disclaimer.
10
-//
11
-// 2. Redistributions in binary form must reproduce the above copyright notice,
12
-//    this list of conditions and the following disclaimer in the documentation
13
-//    and/or other materials provided with the distribution.
14
-//
15
-// 3. Neither the name of the copyright holder nor the names of its contributors
16
-//    may be used to endorse or promote products derived from this software
17
-//    without specific prior written permission.
18
-//
19
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
-// POSSIBILITY OF SUCH DAMAGE.
30
-//
31
-////////////////////////////////////////////////////////////////////////////////
1
+/*******************************************************************************
2
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
3
+ * All rights reserved.
4
+ *
5
+ * Redistribution and use in source and binary forms, with or without
6
+ * modification, are permitted provided that the following conditions are met:
7
+ *
8
+ * 1. Redistributions of source code must retain the above copyright notice,
9
+ *    this list of conditions and the following disclaimer.
10
+ *
11
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
12
+ *    this list of conditions and the following disclaimer in the documentation
13
+ *    and/or other materials provided with the distribution.
14
+ *
15
+ * 3. Neither the name of the copyright holder nor the names of its contributors
16
+ *    may be used to endorse or promote products derived from this software
17
+ *    without specific prior written permission.
18
+ *
19
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+ * POSSIBILITY OF SUCH DAMAGE.
30
+ *
31
+ *******************************************************************************/
32 32
 
33 33
 #include "util/ities.h"
34 34
 #include <util/logging.h>
@@ -43,30 +43,33 @@ extern "C" {
43 43
 #ifdef __cplusplus
44 44
 }
45 45
 #endif
46
-#include <fstream>
47 46
 #include <cstdio>
48 47
 #include <cstring>
48
+#include <fstream>
49 49
 
50 50
 using namespace iss::arch;
51 51
 
52
+constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::${coreDef.name}_reg_size;
53
+constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::${coreDef.name}_reg_byte_offset;
54
+
52 55
 ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
53
-    reg.icount=0;
56
+    reg.icount = 0;
57
+    reg.machine_state = 0x3;
54 58
 }
55 59
 
56
-${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}(){
60
+${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
57 61
 }
58 62
 
59 63
 void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
60
-    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
64
+    for(size_t i=0; i<traits<${coreDef.name.toLowerCase()}>::NUM_REGS; ++i)
65
+    	set_reg(i, std::vector<uint8_t>(sizeof(traits<${coreDef.name.toLowerCase()}>::reg_t),0));
61 66
     reg.PC=address;
62 67
     reg.NEXT_PC=reg.PC;
63 68
     reg.trap_state=0;
64
-    reg.machine_state=0x0;
69
+    reg.machine_state=0x3;
65 70
 }
66 71
 
67
-uint8_t* ${coreDef.name.toLowerCase()}::get_regs_base_ptr(){
68
-    return reinterpret_cast<uint8_t*>(&reg);
69
-}
72
+uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() { return reinterpret_cast<uint8_t*>(&reg); }
70 73
 
71 74
 ${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
72 75
     return phys_addr_t(pc); // change logical address to physical address

+ 50
- 54
riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl View File

@@ -1,38 +1,34 @@
1
-////////////////////////////////////////////////////////////////////////////////
2
-// Copyright (C) 2017, MINRES Technologies GmbH
3
-// All rights reserved.
4
-//
5
-// Redistribution and use in source and binary forms, with or without
6
-// modification, are permitted provided that the following conditions are met:
7
-//
8
-// 1. Redistributions of source code must retain the above copyright notice,
9
-//    this list of conditions and the following disclaimer.
10
-//
11
-// 2. Redistributions in binary form must reproduce the above copyright notice,
12
-//    this list of conditions and the following disclaimer in the documentation
13
-//    and/or other materials provided with the distribution.
14
-//
15
-// 3. Neither the name of the copyright holder nor the names of its contributors
16
-//    may be used to endorse or promote products derived from this software
17
-//    without specific prior written permission.
18
-//
19
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
-// POSSIBILITY OF SUCH DAMAGE.
30
-//
31
-// Contributors:
32
-//       eyck@minres.com - initial API and implementation
33
-//
34
-//
35
-////////////////////////////////////////////////////////////////////////////////
1
+/*******************************************************************************
2
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
3
+ * All rights reserved.
4
+ *
5
+ * Redistribution and use in source and binary forms, with or without
6
+ * modification, are permitted provided that the following conditions are met:
7
+ *
8
+ * 1. Redistributions of source code must retain the above copyright notice,
9
+ *    this list of conditions and the following disclaimer.
10
+ *
11
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
12
+ *    this list of conditions and the following disclaimer in the documentation
13
+ *    and/or other materials provided with the distribution.
14
+ *
15
+ * 3. Neither the name of the copyright holder nor the names of its contributors
16
+ *    may be used to endorse or promote products derived from this software
17
+ *    without specific prior written permission.
18
+ *
19
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+ * POSSIBILITY OF SUCH DAMAGE.
30
+ *
31
+ *******************************************************************************/
36 32
 
37 33
 #include <iss/arch/${coreDef.name.toLowerCase()}.h>
38 34
 #include <iss/arch/riscv_hart_msu_vp.h>
@@ -44,12 +40,12 @@
44 40
 
45 41
 #include <boost/format.hpp>
46 42
 
47
-#include <iss/debugger/riscv_target_adapter.h>
48 43
 #include <array>
44
+#include <iss/debugger/riscv_target_adapter.h>
49 45
 
50 46
 namespace iss {
51 47
 namespace vm {
52
-namespace fp_impl{
48
+namespace fp_impl {
53 49
 void add_fp_functions_2_module(llvm::Module *, unsigned);
54 50
 }
55 51
 }
@@ -73,7 +69,7 @@ public:
73 69
 
74 70
     void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
75 71
 
76
-    target_adapter_if *accquire_target_adapter(server_if *srv) {
72
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
77 73
         debugger_if::dbg_enabled = true;
78 74
         if (vm::vm_base<ARCH>::tgt_adapter == nullptr)
79 75
             vm::vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
@@ -87,7 +83,7 @@ protected:
87 83
         return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
88 84
     }
89 85
 
90
-    void setup_module(llvm::Module* m) override {
86
+    void setup_module(llvm::Module *m) override {
91 87
         super::setup_module(m);
92 88
         vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE);
93 89
     }
@@ -117,7 +113,7 @@ protected:
117 113
 
118 114
     inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
119 115
         llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
120
-                                                                  this->get_type(traits<ARCH>::XLEN));
116
+                                                                 this->get_type(traits<ARCH>::XLEN));
121 117
         this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
122 118
     }
123 119
 
@@ -136,9 +132,9 @@ protected:
136 132
     std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
137 133
     std::array<compile_func, LUT_SIZE> lut_11;
138 134
 
139
-	std::array<compile_func*, 4> qlut;
135
+	std::array<compile_func *, 4> qlut;
140 136
 
141
-	std::array<const uint32_t, 4> lutmasks = { { EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32 } };
137
+	std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
142 138
 
143 139
     void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
144 140
                          compile_func f) {
@@ -248,7 +244,7 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
248 244
     const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
249 245
     phys_addr_t paddr(pc);
250 246
     try {
251
-        uint8_t *const data = (uint8_t *)&insn;
247
+        auto *const data = (uint8_t *)&insn;
252 248
         paddr = this->core.v2p(pc);
253 249
         if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
254 250
             auto res = this->core.read(paddr, 2, data);
@@ -282,7 +278,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock
282 278
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
283 279
     auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
284 280
     this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
285
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
281
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
282
+    						  get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
286 283
 }
287 284
 
288 285
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
@@ -292,7 +289,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
292 289
     this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
293 290
     auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
294 291
     this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
295
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
292
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
293
+                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
296 294
 }
297 295
 
298 296
 template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
@@ -305,11 +303,10 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
305 303
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(llvm::BasicBlock *trap_blk) {
306 304
     this->builder.SetInsertPoint(trap_blk);
307 305
     auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
308
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
309
-    std::vector<llvm::Value *> args{
310
-    	this->core_ptr,
311
-    	this->adj_to64(trap_state_val),
312
-        this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
306
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
307
+                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
308
+    std::vector<llvm::Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
309
+                                    this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
313 310
     this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
314 311
     auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
315 312
     this->builder.CreateRet(trap_addr_val);
@@ -327,10 +324,9 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBl
327 324
 
328 325
 template <>
329 326
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
330
-    std::unique_ptr<${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>> ret =
331
-        std::make_unique<${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>>(*core, dump);
332
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret.get(), port);
333
-    return ret;
327
+    auto ret = new ${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*core, dump);
328
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
329
+    return std::unique_ptr<vm_if>(ret);
334 330
 }
335 331
 
336 332
 } // namespace iss

+ 24
- 11
riscv/gen_input/templates/vm_riscv.in.cpp View File

@@ -44,6 +44,12 @@
44 44
 #include <iss/debugger/riscv_target_adapter.h>
45 45
 
46 46
 namespace iss {
47
+namespace vm {
48
+namespace fp_impl {
49
+void add_fp_functions_2_module(llvm::Module *, unsigned);
50
+}
51
+}
52
+
47 53
 namespace CORE_DEF_NAME {
48 54
 using namespace iss::arch;
49 55
 using namespace llvm;
@@ -63,7 +69,7 @@ public:
63 69
 
64 70
     void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
65 71
 
66
-    target_adapter_if *accquire_target_adapter(server_if *srv) {
72
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
67 73
         debugger_if::dbg_enabled = true;
68 74
         if (vm::vm_base<ARCH>::tgt_adapter == nullptr)
69 75
             vm::vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
@@ -77,8 +83,12 @@ protected:
77 83
         return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
78 84
     }
79 85
 
80
-    inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal,
81
-                                   unsigned size) const {
86
+    void setup_module(llvm::Module *m) override {
87
+        super::setup_module(m);
88
+        vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE);
89
+    }
90
+
91
+    inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal, unsigned size) {
82 92
         return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
83 93
     }
84 94
 
@@ -225,7 +235,7 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
225 235
     const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
226 236
     phys_addr_t paddr(pc);
227 237
     try {
228
-        uint8_t *const data = (uint8_t *)&insn;
238
+        auto *const data = (uint8_t *)&insn;
229 239
         paddr = this->core.v2p(pc);
230 240
         if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
231 241
             auto res = this->core.read(paddr, 2, data);
@@ -242,7 +252,6 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
242 252
     }
243 253
     if (insn == 0x0000006f || (insn & 0xffff) == 0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
244 254
     // curr pc on stack
245
-    typename vm_impl<ARCH>::processing_pc_entry addr(*this, pc, paddr);
246 255
     ++inst_cnt;
247 256
     auto lut_val = extract_fields(insn);
248 257
     auto f = qlut[insn & 0x3][lut_val];
@@ -260,6 +269,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock
260 269
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
261 270
     auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
262 271
     this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
272
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
273
+                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
263 274
 }
264 275
 
265 276
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
@@ -269,6 +280,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
269 280
     this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
270 281
     auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
271 282
     this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
283
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
284
+                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
272 285
 }
273 286
 
274 287
 template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
@@ -281,6 +294,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
281 294
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(llvm::BasicBlock *trap_blk) {
282 295
     this->builder.SetInsertPoint(trap_blk);
283 296
     auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
297
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
298
+                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
284 299
     std::vector<llvm::Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
285 300
                                     this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
286 301
     this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
@@ -298,12 +313,10 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBl
298 313
 
299 314
 } // namespace CORE_DEF_NAME
300 315
 
301
-template <>
302
-std::unique_ptr<vm_if> create<arch::CORE_DEF_NAME>(arch::CORE_DEF_NAME *core, unsigned short port, bool dump) {
303
-    std::unique_ptr<CORE_DEF_NAME::vm_impl<arch::CORE_DEF_NAME>> ret =
304
-        std::make_unique<CORE_DEF_NAME::vm_impl<arch::CORE_DEF_NAME>>(*core, dump);
305
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret.get(), port);
306
-    return ret;
316
+template <> std::unique_ptr<vm_if> create<arch::CORE_DEF_NAME>(arch::CORE_DEF_NAME *core, unsigned short port, bool dump) {
317
+    auto ret = new CORE_DEF_NAME::vm_impl<arch::CORE_DEF_NAME>(*core, dump);
318
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
319
+    return std::unique_ptr<vm_if>(ret);
307 320
 }
308 321
 
309 322
 } // namespace iss