Browse Source

Merge branch 'develop'

Conflicts:
	.cproject
	dbt-core
	sc-components
Eyck Jentzsch 1 year ago
parent
commit
9ad29ddb64
100 changed files with 21488 additions and 604 deletions
  1. 14
    2
      .cproject
  2. 2
    1
      .project
  3. 8
    0
      .settings/org.eclipse.cdt.core.prefs
  4. 2
    0
      CMakeLists.txt
  5. 1728
    0
      cycles.txt
  6. 1
    1
      dbt-core
  7. 3
    3
      etc/CoreDSL generator.launch
  8. 1
    1
      etc/dbt-riscv Debug hello gdb.launch
  9. 34
    0
      etc/dbt-riscv Debug hello w plugin.launch
  10. 1
    1
      etc/dbt-riscv SC Debug hello.launch
  11. 34
    0
      etc/dbt-riscv dhrystone.launch
  12. 1
    1
      riscv.sc/CMakeLists.txt
  13. 1
    0
      riscv.sc/src/CMakeLists.txt
  14. 9
    9
      riscv.sc/src/sysc/core_complex.cpp
  15. 1
    17
      riscv/CMakeLists.txt
  16. 91
    16
      riscv/gen_input/RV32C.core_desc
  17. 298
    0
      riscv/gen_input/RV32D.core_desc
  18. 210
    21
      riscv/gen_input/RV32F.core_desc
  19. 5
    5
      riscv/gen_input/RV32IBase.core_desc
  20. 27
    11
      riscv/gen_input/RV32M.core_desc
  21. 19
    14
      riscv/gen_input/minres_rv.core_desc
  22. 12
    8
      riscv/gen_input/templates/incl-CORENAME.h.gtl
  23. 3
    2
      riscv/gen_input/templates/src-CORENAME.cpp.gtl
  24. 11
    3
      riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl
  25. 0
    0
      riscv/gen_input/templates/vm_riscv.in.cpp
  26. 45
    1
      riscv/incl/iss/arch/riscv_hart_msu_vp.h
  27. 277
    0
      riscv/incl/iss/arch/rv32gc.h
  28. 7
    2
      riscv/incl/iss/arch/rv32imac.h
  29. 7
    2
      riscv/incl/iss/arch/rv64ia.h
  30. 5
    4
      riscv/src/CMakeLists.txt
  31. 458
    0
      riscv/src/internal/fp_functions.cpp
  32. 8415
    0
      riscv/src/internal/vm_rv32gc.cpp
  33. 379
    245
      riscv/src/internal/vm_rv32imac.cpp
  34. 229
    215
      riscv/src/internal/vm_rv64ia.cpp
  35. 74
    0
      riscv/src/iss/rv32gc.cpp
  36. 48
    12
      riscv/src/main.cpp
  37. 5
    5
      riscv/src/plugin/cycle_estimate.cpp
  38. 3
    1
      riscv/src/plugin/instruction_count.cpp
  39. 1
    1
      sc-components
  40. 381
    0
      softfloat/CMakeLists.txt
  41. 37
    0
      softfloat/COPYING.txt
  42. 49
    0
      softfloat/README.html
  43. 21
    0
      softfloat/README.txt
  44. 325
    0
      softfloat/build/Linux-386-GCC/Makefile
  45. 53
    0
      softfloat/build/Linux-386-GCC/platform.h
  46. 325
    0
      softfloat/build/Linux-386-SSE2-GCC/Makefile
  47. 53
    0
      softfloat/build/Linux-386-SSE2-GCC/platform.h
  48. 323
    0
      softfloat/build/Linux-ARM-VFPv2-GCC/Makefile
  49. 53
    0
      softfloat/build/Linux-ARM-VFPv2-GCC/platform.h
  50. 390
    0
      softfloat/build/Linux-x86_64-GCC/Makefile
  51. 55
    0
      softfloat/build/Linux-x86_64-GCC/platform.h
  52. 325
    0
      softfloat/build/Win32-MinGW/Makefile
  53. 53
    0
      softfloat/build/Win32-MinGW/platform.h
  54. 325
    0
      softfloat/build/Win32-SSE2-MinGW/Makefile
  55. 53
    0
      softfloat/build/Win32-SSE2-MinGW/platform.h
  56. 390
    0
      softfloat/build/Win64-MinGW-w64/Makefile
  57. 54
    0
      softfloat/build/Win64-MinGW-w64/platform.h
  58. 391
    0
      softfloat/build/template-FAST_INT64/Makefile
  59. 50
    0
      softfloat/build/template-FAST_INT64/platform.h
  60. 325
    0
      softfloat/build/template-not-FAST_INT64/Makefile
  61. 50
    0
      softfloat/build/template-not-FAST_INT64/platform.h
  62. 258
    0
      softfloat/doc/SoftFloat-history.html
  63. 686
    0
      softfloat/doc/SoftFloat-source.html
  64. 1527
    0
      softfloat/doc/SoftFloat.html
  65. 57
    0
      softfloat/source/8086-SSE/extF80M_isSignalingNaN.c
  66. 60
    0
      softfloat/source/8086-SSE/f128M_isSignalingNaN.c
  67. 56
    0
      softfloat/source/8086-SSE/s_commonNaNToExtF80M.c
  68. 56
    0
      softfloat/source/8086-SSE/s_commonNaNToExtF80UI.c
  69. 56
    0
      softfloat/source/8086-SSE/s_commonNaNToF128M.c
  70. 55
    0
      softfloat/source/8086-SSE/s_commonNaNToF128UI.c
  71. 51
    0
      softfloat/source/8086-SSE/s_commonNaNToF16UI.c
  72. 51
    0
      softfloat/source/8086-SSE/s_commonNaNToF32UI.c
  73. 53
    0
      softfloat/source/8086-SSE/s_commonNaNToF64UI.c
  74. 62
    0
      softfloat/source/8086-SSE/s_extF80MToCommonNaN.c
  75. 62
    0
      softfloat/source/8086-SSE/s_extF80UIToCommonNaN.c
  76. 62
    0
      softfloat/source/8086-SSE/s_f128MToCommonNaN.c
  77. 65
    0
      softfloat/source/8086-SSE/s_f128UIToCommonNaN.c
  78. 59
    0
      softfloat/source/8086-SSE/s_f16UIToCommonNaN.c
  79. 59
    0
      softfloat/source/8086-SSE/s_f32UIToCommonNaN.c
  80. 59
    0
      softfloat/source/8086-SSE/s_f64UIToCommonNaN.c
  81. 107
    0
      softfloat/source/8086-SSE/s_propagateNaNExtF80M.c
  82. 106
    0
      softfloat/source/8086-SSE/s_propagateNaNExtF80UI.c
  83. 76
    0
      softfloat/source/8086-SSE/s_propagateNaNF128M.c
  84. 81
    0
      softfloat/source/8086-SSE/s_propagateNaNF128UI.c
  85. 63
    0
      softfloat/source/8086-SSE/s_propagateNaNF16UI.c
  86. 63
    0
      softfloat/source/8086-SSE/s_propagateNaNF32UI.c
  87. 63
    0
      softfloat/source/8086-SSE/s_propagateNaNF64UI.c
  88. 52
    0
      softfloat/source/8086-SSE/softfloat_raiseFlags.c
  89. 376
    0
      softfloat/source/8086-SSE/specialize.h
  90. 57
    0
      softfloat/source/8086/extF80M_isSignalingNaN.c
  91. 60
    0
      softfloat/source/8086/f128M_isSignalingNaN.c
  92. 56
    0
      softfloat/source/8086/s_commonNaNToExtF80M.c
  93. 56
    0
      softfloat/source/8086/s_commonNaNToExtF80UI.c
  94. 56
    0
      softfloat/source/8086/s_commonNaNToF128M.c
  95. 55
    0
      softfloat/source/8086/s_commonNaNToF128UI.c
  96. 51
    0
      softfloat/source/8086/s_commonNaNToF16UI.c
  97. 51
    0
      softfloat/source/8086/s_commonNaNToF32UI.c
  98. 53
    0
      softfloat/source/8086/s_commonNaNToF64UI.c
  99. 62
    0
      softfloat/source/8086/s_extF80MToCommonNaN.c
  100. 0
    0
      softfloat/source/8086/s_extF80UIToCommonNaN.c

+ 14
- 2
.cproject View File

@@ -10,6 +10,7 @@
10 10
 					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
11 11
 					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
12 12
 					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
13
+					<extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
13 14
 				</extensions>
14 15
 			</storageModule>
15 16
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
@@ -17,7 +18,7 @@
17 18
 					<folderInfo id="cdt.managedbuild.config.gnu.exe.debug.1751741082." name="/" resourcePath="">
18 19
 						<toolChain id="cdt.managedbuild.toolchain.gnu.exe.debug.1289745146" name="Linux GCC" superClass="cdt.managedbuild.toolchain.gnu.exe.debug">
19 20
 							<targetPlatform binaryParser="org.eclipse.cdt.core.GNU_ELF;org.eclipse.cdt.core.ELF" id="cdt.managedbuild.target.gnu.platform.exe.debug.1460698591" name="Debug Platform" superClass="cdt.managedbuild.target.gnu.platform.exe.debug"/>
20
-							<builder buildPath="/DBT-RISE-RISCV/build/Debug" id="de.marw.cdt.cmake.core.genscriptbuilder.2126162017" keepEnvironmentInBuildfile="false" name="CMake Builder (portable)" parallelBuildOn="true" parallelizationNumber="optimal" superClass="de.marw.cdt.cmake.core.genscriptbuilder"/>
21
+							<builder buildPath="/DBT-RISE-RISCV/build/{ConfigName}" id="de.marw.cdt.cmake.core.genmakebuilder.2061143699" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CMake Builder (GNU Make)" parallelBuildOn="true" parallelizationNumber="optimal" superClass="de.marw.cdt.cmake.core.genmakebuilder"/>
21 22
 							<tool id="cdt.managedbuild.tool.gnu.archiver.base.366643800" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
22 23
 							<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.1510612390" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug">
23 24
 								<option id="gnu.cpp.compiler.exe.debug.option.optimization.level.1768317780" name="Optimization Level" superClass="gnu.cpp.compiler.exe.debug.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
@@ -45,7 +46,17 @@
45 46
 			</storageModule>
46 47
 			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
47 48
 			<storageModule buildDir="build/${ConfigName}" moduleId="de.marw.cdt.cmake.core.settings">
48
-				<options/>
49
+				<options clearCache="true"/>
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+				<linux command="cmake" generator="UnixMakefiles" use-default="true">
51
+					<defs>
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+						<def name="CMAKE_VERBOSE_MAKEFILE" type="BOOL" val="OFF"/>
53
+					</defs>
54
+					<undefs/>
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+				</linux>
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+				<win32 command="cmake" generator="MinGWMakefiles" use-default="true">
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+					<defs/>
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+					<undefs/>
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+				</win32>
49 60
 			</storageModule>
50 61
 		</cconfiguration>
51 62
 		<cconfiguration id="cdt.managedbuild.config.gnu.exe.release.1745230171">
@@ -177,4 +188,5 @@
177 188
 		</configuration>
178 189
 	</storageModule>
179 190
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
191
+	<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
180 192
 </cproject>

+ 2
- 1
.project View File

@@ -1,6 +1,6 @@
1 1
 <?xml version="1.0" encoding="UTF-8"?>
2 2
 <projectDescription>
3
-	<name>dbt-riscv</name>
3
+	<name>DBT-RISE-RISCV</name>
4 4
 	<comment></comment>
5 5
 	<projects>
6 6
 	</projects>
@@ -23,5 +23,6 @@
23 23
 		<nature>org.eclipse.cdt.core.ccnature</nature>
24 24
 		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
25 25
 		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
26
+		<nature>org.eclipse.linuxtools.tmf.project.nature</nature>
26 27
 	</natures>
27 28
 </projectDescription>

+ 8
- 0
.settings/org.eclipse.cdt.core.prefs View File

@@ -0,0 +1,8 @@
1
+eclipse.preferences.version=1
2
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
3
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
4
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/delimiter=\:
5
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/operation=append
6
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/value=/usr/lib/llvm-6.0
7
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
8
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true

+ 2
- 0
CMakeLists.txt View File

@@ -51,6 +51,8 @@ include(clang-format)
51 51
 add_subdirectory(external)
52 52
 add_subdirectory(dbt-core)
53 53
 add_subdirectory(sc-components)
54
+add_subdirectory(softfloat)
55
+GET_DIRECTORY_PROPERTY(SOFTFLOAT_INCLUDE_DIRS DIRECTORY softfloat DEFINITION SOFTFLOAT_INCLUDE_DIRS)
54 56
 add_subdirectory(riscv)
55 57
 add_subdirectory(riscv.sc)
56 58
 

+ 1728
- 0
cycles.txt
File diff suppressed because it is too large
View File


+ 1
- 1
dbt-core

@@ -1 +1 @@
1
-Subproject commit 23dbab0b768d122c492110d1db34408e9ae787f3
1
+Subproject commit 393c374cac4950e629036dda1615abedf866961f

+ 3
- 3
etc/CoreDSL generator.launch View File

@@ -2,7 +2,7 @@
2 2
 <launchConfiguration type="org.eclipse.ui.externaltools.ProgramLaunchConfigurationType">
3 3
 <stringAttribute key="org.eclipse.debug.core.ATTR_REFRESH_SCOPE" value="${working_set:&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;resources&gt;&#10;&lt;item path=&quot;/dbt-riscv/riscv&quot; type=&quot;2&quot;/&gt;&#10;&lt;/resources&gt;}"/>
4 4
 <stringAttribute key="org.eclipse.ui.externaltools.ATTR_LAUNCH_CONFIGURATION_BUILD_SCOPE" value="${none}"/>
5
-<stringAttribute key="org.eclipse.ui.externaltools.ATTR_LOCATION" value="/usr/lib/jvm/java-8-oracle/bin/java"/>
6
-<stringAttribute key="org.eclipse.ui.externaltools.ATTR_TOOL_ARGUMENTS" value="-jar ${env_var:HOME}/git/JIT-ISS-CoreDsl/com.minres.coredsl.standalone/target/com.minres.coredsl.standalone-1.0.0-SNAPSHOT.jar&#10;-i=${project_loc:dbt-riscv}/riscv/incl/iss/arch&#10;-s=${project_loc:dbt-riscv}/riscv/src/iss&#10;-v=${project_loc:dbt-riscv}/riscv/src/internal&#10;-t=${project_loc:dbt-riscv}/riscv/gen_input/templates&#10;${project_loc:dbt-riscv}/riscv/gen_input/minres_rv.core_desc"/>
7
-<stringAttribute key="org.eclipse.ui.externaltools.ATTR_WORKING_DIRECTORY" value="${workspace_loc:/dbt-riscv}/riscv/gen_input"/>
5
+<stringAttribute key="org.eclipse.ui.externaltools.ATTR_LOCATION" value="/usr/bin/java"/>
6
+<stringAttribute key="org.eclipse.ui.externaltools.ATTR_TOOL_ARGUMENTS" value="-Xmx1G -jar ${env_var:HOME}/git/JIT-ISS-CoreDsl/com.minres.coredsl.standalone/target/com.minres.coredsl.standalone-1.0.0-SNAPSHOT.jar&#10;-i=${project_loc:DBT-RISE-RISCV}/riscv/incl/iss/arch&#10;-s=${project_loc:DBT-RISE-RISCV}/riscv/src/iss&#10;-v=${project_loc:DBT-RISE-RISCV}/riscv/src/internal&#10;-t=${project_loc:DBT-RISE-RISCV}/riscv/gen_input/templates&#10;${project_loc:DBT-RISE-RISCV}/riscv/gen_input/minres_rv.core_desc"/>
7
+<stringAttribute key="org.eclipse.ui.externaltools.ATTR_WORKING_DIRECTORY" value="${workspace_loc:/DBT-RISE-RISCV}/riscv/gen_input"/>
8 8
 </launchConfiguration>

+ 1
- 1
etc/dbt-riscv Debug hello gdb.launch View File

@@ -19,7 +19,7 @@
19 19
 <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
20 20
 <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
21 21
 <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_ARGUMENTS" value="-v4&#10;-g10000&#10;${project_loc:hello}/hello"/>
22
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="/home/eyck/git/DBT-RISE-RISCV/build/Debug/bin/riscv"/>
22
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="build/Debug/riscv/bin/riscv"/>
23 23
 <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="DBT-RISE-RISCV"/>
24 24
 <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
25 25
 <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>

+ 34
- 0
etc/dbt-riscv Debug hello w plugin.launch View File

@@ -0,0 +1,34 @@
1
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
2
+<launchConfiguration type="org.eclipse.cdt.launch.applicationLaunchType">
3
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.AUTO_SOLIB" value="true"/>
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+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="gdb"/>
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+<stringAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE_MODE" value="UseSoftTrace"/>
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+<stringAttribute key="org.eclipse.cdt.dsf.gdb.TRACEPOINT_MODE" value="TP_NORMAL_ONLY"/>
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+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
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+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.internal.ui.launching.LocalApplicationCDebuggerTab.DEFAULTS_SET" value="true"/>
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+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
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+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
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+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
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+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
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+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
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+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_ARGUMENTS" value="-v4&#10;-p ic=${workspace_loc:DBT-RISE-RISCV}/cycles.txt&#10;${project_loc:hello}/hello"/>
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+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="build/Debug/riscv/bin/riscv"/>
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+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="DBT-RISE-RISCV"/>
24
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
25
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="cdt.managedbuild.config.gnu.exe.debug.1751741082"/>
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+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
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+<listEntry value="/DBT-RISE-RISCV"/>
28
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+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
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+<listEntry value="4"/>
31
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+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#10;"/>
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+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
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+</launchConfiguration>

+ 1
- 1
etc/dbt-riscv SC Debug hello.launch View File

@@ -19,7 +19,7 @@
19 19
 <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
20 20
 <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="sc_main"/>
21 21
 <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_ARGUMENTS" value="-v5&#10;-c simple-system.json&#10;-l ${project_loc:hello}/hello"/>
22
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="/home/eyck/git/DBT-RISE-RISCV/build/Debug/bin/riscv.sc"/>
22
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="build/Debug/bin/riscv.sc"/>
23 23
 <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="DBT-RISE-RISCV"/>
24 24
 <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
25 25
 <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>

+ 34
- 0
etc/dbt-riscv dhrystone.launch View File

@@ -0,0 +1,34 @@
1
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
2
+<launchConfiguration type="org.eclipse.cdt.launch.applicationLaunchType">
3
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.AUTO_SOLIB" value="true"/>
4
+<listAttribute key="org.eclipse.cdt.dsf.gdb.AUTO_SOLIB_LIST"/>
5
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="gdb"/>
6
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_ON_FORK" value="false"/>
7
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.GDB_INIT" value=".gdbinit"/>
8
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
9
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE" value="false"/>
10
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE_MODE" value="UseSoftTrace"/>
11
+<listAttribute key="org.eclipse.cdt.dsf.gdb.SOLIB_PATH"/>
12
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.TRACEPOINT_MODE" value="TP_NORMAL_ONLY"/>
13
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
14
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.internal.ui.launching.LocalApplicationCDebuggerTab.DEFAULTS_SET" value="true"/>
15
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="1"/>
16
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
17
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="gdb"/>
18
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
19
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
20
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
21
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_ARGUMENTS" value="-v4&#10;${project_loc:dhrystone}/dhrystone"/>
22
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="build/Release/riscv/bin/riscv"/>
23
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="DBT-RISE-RISCV"/>
24
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
25
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="cdt.managedbuild.config.gnu.exe.release.1745230171"/>
26
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
27
+<listEntry value="/DBT-RISE-RISCV"/>
28
+</listAttribute>
29
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
30
+<listEntry value="4"/>
31
+</listAttribute>
32
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#10;"/>
33
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
34
+</launchConfiguration>

+ 1
- 1
riscv.sc/CMakeLists.txt View File

@@ -68,7 +68,7 @@ include_directories(
68 68
 
69 69
 add_dependent_subproject(dbt-core)
70 70
 add_dependent_subproject(sc-components)
71
-add_dependent_header(util)
71
+add_dependent_subproject(riscv)
72 72
 
73 73
 include_directories(
74 74
     ${PROJECT_SOURCE_DIR}/incl

+ 1
- 0
riscv.sc/src/CMakeLists.txt View File

@@ -41,6 +41,7 @@ add_executable(${APPLICATION_NAME} ${APP_SOURCES})
41 41
 target_link_libraries(${APPLICATION_NAME} ${LIBRARY_NAME})
42 42
 target_link_libraries(${APPLICATION_NAME} risc-v)
43 43
 target_link_libraries(${APPLICATION_NAME} dbt-core)
44
+target_link_libraries(${APPLICATION_NAME} softfloat)
44 45
 target_link_libraries(${APPLICATION_NAME} sc-components)
45 46
 target_link_libraries(${APPLICATION_NAME} ${CONAN_LIBS_SEASOCKS})
46 47
 target_link_libraries(${APPLICATION_NAME} external)

+ 9
- 9
riscv.sc/src/sysc/core_complex.cpp View File

@@ -103,7 +103,9 @@ public:
103 103
 
104 104
     base_type::hart_state<base_type::reg_t>& get_state() { return this->state; }
105 105
 
106
-    void notify_phase(exec_phase) override;
106
+    void notify_phase(exec_phase p) override {
107
+        if(p == ISTART) owner->sync(this->reg.icount+cycle_offset);
108
+    }
107 109
 
108 110
     sync_type needed_sync() const override { return PRE_SYNC; }
109 111
 
@@ -131,9 +133,12 @@ public:
131 133
     		return owner->write_mem_dbg(addr.val, length, data) ? Ok : Err;
132 134
     	else{
133 135
     		auto res = owner->write_mem(addr.val, length, data) ? Ok : Err;
134
-    		// TODO: this is an ugly hack (clear MTIP on mtimecmp write), needs to be fixed
135
-    		if(addr.val==0x2004000)
136
-    			this->csr[arch::mip] &= ~(1ULL<<7);
136
+    		// clear MTIP on mtimecmp write
137
+    		if(addr.val==0x2004000){
138
+    		    reg_t val;
139
+    		    this->read_csr(arch::mip, val);
140
+    			this->write_csr(arch::mip, val & ~(1ULL<<7));
141
+    		}
137 142
     		return res;
138 143
     	}
139 144
     }
@@ -198,11 +203,6 @@ int cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func
198 203
 
199 204
 }
200 205
 
201
-void core_wrapper::notify_phase(exec_phase p) {
202
-    if(p == ISTART)
203
-        owner->sync(this->reg.icount+cycle_offset);
204
-}
205
-
206 206
 core_complex::core_complex(sc_core::sc_module_name name)
207 207
 : sc_core::sc_module(name)
208 208
 , NAMED(initiator)

+ 1
- 17
riscv/CMakeLists.txt View File

@@ -41,30 +41,14 @@ message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
41 41
 message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
42 42
 llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
43 43
 
44
-find_package(SystemC)
45
-if(SystemC_FOUND)
46
-    add_definitions(-DWITH_SYSTEMC)
47
-    include_directories(${SystemC_INCLUDE_DIRS})
48
-    link_directories(${SystemC_LIBRARY_DIRS})
49
-else(SystemC_FOUND)
50
-    message( FATAL_ERROR "SystemC library not found." )
51
-endif(SystemC_FOUND)
52
-
53
-if(SCV_FOUND)   
54
-    add_definitions(-DWITH_SCV)
55
-    link_directories(${SCV_LIBRARY_DIRS})
56
-endif(SCV_FOUND)
57
-
58 44
 # This sets the include directory for the reference project. This is the -I flag in gcc.
59 45
 include_directories(
60 46
     ${PROJECT_SOURCE_DIR}/incl
47
+	${SOFTFLOAT_INCLUDE_DIRS}
61 48
     ${LLVM_INCLUDE_DIRS}
62 49
 )
63
-
64 50
 add_dependent_subproject(dbt-core)
65 51
 add_dependent_subproject(sc-components)
66
-add_dependent_header(util)
67
-
68 52
 include_directories(
69 53
     ${PROJECT_SOURCE_DIR}/incl
70 54
     ${PROJECT_SOURCE_DIR}/../external/elfio

+ 91
- 16
riscv/gen_input/RV32C.core_desc View File

@@ -1,6 +1,6 @@
1 1
 import "RV32IBase.core_desc"
2 2
 
3
-InsructionSet RV32CI {
3
+InsructionSet RV32IC {
4 4
 	constants {
5 5
 		XLEN
6 6
 	}
@@ -197,7 +197,64 @@ InsructionSet RV32CI {
197 197
 	}
198 198
 }
199 199
 
200
-InsructionSet RV32CF extends RV32CI {
200
+InsructionSet RV32FC extends RV32IC{
201
+	constants {
202
+		XLEN, FLEN
203
+	}
204
+	address_spaces { 
205
+		MEM[8]
206
+	}
207
+	registers { 
208
+		[31:0]   X[XLEN],
209
+		[31:0]   F[FLEN]
210
+	}
211
+	instructions{
212
+		C.FLW {
213
+			encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
214
+			args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))";
215
+			val rs1_idx[5] <= rs1+8;
216
+			val rd_idx[5] <= rd+8;
217
+			val offs[XLEN] <= X[rs1_idx]+uimm;
218
+			val res[32] <= MEM[offs]{32};
219
+			if(FLEN==32)
220
+				F[rd_idx] <= res;
221
+			else { // NaN boxing
222
+				val upper[FLEN] <= -1;
223
+				F[rd] <= (upper<<32) | zext(res, FLEN);
224
+			}
225
+		} 
226
+		C.FSW {
227
+			encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
228
+			args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))";
229
+			val rs1_idx[5] <= rs1+8;
230
+			val rs2_idx[5] <= rs2+8;
231
+			val offs[XLEN] <= X[rs1_idx]+uimm;
232
+			MEM[offs]{32}<=F[rs2_idx]{32};
233
+		}
234
+		C.FLWSP {
235
+			encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
236
+			args_disass:"f%rd$d, %uimm%(x2)";
237
+			val x2_idx[5] <= 2;
238
+			val offs[XLEN] <= X[x2_idx]+uimm;
239
+			val res[32] <= MEM[offs]{32};
240
+			if(FLEN==32)
241
+				F[rd] <= res;
242
+			else { // NaN boxing
243
+				val upper[FLEN] <= -1;
244
+				F[rd] <= (upper<<32) | zext(res, FLEN);
245
+			}
246
+		}
247
+		C.FSWSP {
248
+			encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
249
+			args_disass:"f%rs2$d, %uimm%(x2), ";
250
+			val x2_idx[5] <= 2;
251
+			val offs[XLEN] <= X[x2_idx]+uimm;
252
+			MEM[offs]{32}<=F[rs2]{32};
253
+		}		
254
+	}
255
+}
256
+
257
+InsructionSet RV32DC extends RV32IC{
201 258
 	constants {
202 259
 		XLEN, FLEN
203 260
 	}
@@ -211,32 +268,50 @@ InsructionSet RV32CF extends RV32CI {
211 268
 	instructions{
212 269
 		C.FLD { //(RV32/64)
213 270
 			encoding: b001 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
271
+			args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))";
272
+			val rs1_idx[5] <= rs1+8;
273
+			val rd_idx[5] <= rd+8;
274
+			val offs[XLEN] <= X[rs1_idx]+uimm;
275
+			val res[64] <= MEM[offs]{64};
276
+			if(FLEN==64)
277
+				F[rd_idx] <= res;
278
+			else { // NaN boxing
279
+				val upper[FLEN] <= -1;
280
+				F[rd_idx] <= (upper<<64) | res;
281
+			}
214 282
 	 	}
215
-		C.FLW {//(RV32)
216
-			encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
217
-		} 
218 283
 		C.FSD { //(RV32/64)
219 284
 			encoding: b101 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
285
+			args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))";
286
+			val rs1_idx[5] <= rs1+8;
287
+			val rs2_idx[5] <= rs2+8;
288
+			val offs[XLEN] <= X[rs1_idx]+uimm;
289
+			MEM[offs]{64}<=F[rs2_idx]{64};
220 290
 		} 
221
-		C.FSW {//(RV32)
222
-			encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
223
-		}
224 291
 		C.FLDSP {//(RV32/64)
225 292
 			encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
226
-		}
227
-		C.FLWSP {//RV32
228
-			encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
293
+			args_disass:"f%rd$d, %uimm%(x2)";
294
+			val x2_idx[5] <= 2;
295
+			val offs[XLEN] <= X[x2_idx]+uimm;
296
+			val res[64] <= MEM[offs]{64};
297
+			if(FLEN==64)
298
+				F[rd] <= res;
299
+			else { // NaN boxing
300
+				val upper[FLEN] <= -1;
301
+				F[rd] <= (upper<<64) | zext(res, FLEN);
302
+			}
229 303
 		}
230 304
 		C.FSDSP {//(RV32/64)
231 305
 			encoding:b101 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
306
+			args_disass:"f%rs2$d, %uimm%(x2), ";
307
+			val x2_idx[5] <= 2;
308
+			val offs[XLEN] <= X[x2_idx]+uimm;
309
+			MEM[offs]{64}<=F[rs2]{64};
232 310
 		}
233
-		C.FSWSP {//(RV32)
234
-			encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
235
-		}		
236 311
 	}
237 312
 }
238 313
 
239
-InsructionSet RV64CI extends RV32CI {
314
+InsructionSet RV64IC extends RV32IC {
240 315
 	constants {
241 316
 		XLEN
242 317
 	}
@@ -284,7 +359,7 @@ InsructionSet RV64CI extends RV32CI {
284 359
 	}
285 360
 }
286 361
 
287
-InsructionSet RV128CI extends RV64CI {
362
+InsructionSet RV128IC extends RV64IC {
288 363
 	constants {
289 364
 		XLEN
290 365
 	}

+ 298
- 0
riscv/gen_input/RV32D.core_desc View File

@@ -0,0 +1,298 @@
1
+import "RV32IBase.core_desc"
2
+
3
+InsructionSet RV32D extends RV32IBase{
4
+	constants {
5
+		FLEN, FFLAG_MASK := 0x1f
6
+	} 
7
+	registers {
8
+		[31:0]    F[FLEN],  FCSR[32]
9
+    }	
10
+	instructions{
11
+		FLD {
12
+			encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000111;
13
+			args_disass:"f%rd$d, %imm%(x%rs1$d)";
14
+			val offs[XLEN] <= X[rs1]+imm;
15
+			val res[64] <= MEM[offs]{64};
16
+			if(FLEN==64)
17
+				F[rd] <= res;
18
+			else { // NaN boxing
19
+				val upper[FLEN] <= -1;
20
+				F[rd] <= (upper<<64) | res;
21
+			}
22
+		}
23
+		FSD {
24
+			encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100111;
25
+			args_disass:"f%rs2$d, %imm%(x%rs1$d)";
26
+			val offs[XLEN] <= X[rs1]+imm;
27
+			MEM[offs]{64}<=F[rs2]{64};
28
+		}
29
+		FMADD.D {
30
+			encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
31
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
32
+			//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
33
+			val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(0, 64), choose(rm<7, rm{8}, FCSR{8}));
34
+			if(FLEN==64)
35
+				F[rd] <= res;
36
+			else { // NaN boxing
37
+				val upper[FLEN] <= -1;
38
+				F[rd] <= (upper<<64) | res;
39
+			}
40
+			val flags[32] <= fdispatch_fget_flags();
41
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
42
+		}
43
+		FMSUB.D {
44
+			encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
45
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
46
+			//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
47
+			val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
48
+			if(FLEN==64)
49
+				F[rd] <= res;
50
+			else { // NaN boxing
51
+				val upper[FLEN] <= -1;
52
+				F[rd] <= (upper<<64) | res;
53
+			}
54
+			val flags[32] <= fdispatch_fget_flags();
55
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};	
56
+		}
57
+		FNMADD.D {
58
+			encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
59
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
60
+			//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
61
+			val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
62
+			if(FLEN==64)
63
+				F[rd] <= res;
64
+			else { // NaN boxing
65
+				val upper[FLEN] <= -1;
66
+				F[rd] <= (upper<<64) | res;
67
+			}
68
+			val flags[32] <= fdispatch_fget_flags();
69
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
70
+		}
71
+		FNMSUB.D {
72
+			encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
73
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
74
+			//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
75
+			val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
76
+			if(FLEN==64)
77
+				F[rd] <= res;
78
+			else { // NaN boxing
79
+				val upper[FLEN] <= -1;
80
+				F[rd] <= (upper<<64) | res;
81
+			}
82
+			val flags[32] <= fdispatch_fget_flags();
83
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
84
+		}
85
+		FADD.D {
86
+			encoding: b0000001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
87
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
88
+			// F[rd]f <= F[rs1]f + F[rs2]f;
89
+			val res[64] <= fdispatch_fadd_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
90
+			if(FLEN==64)
91
+				F[rd] <= res;
92
+			else { // NaN boxing
93
+				val upper[FLEN] <= -1;
94
+				F[rd] <= (upper<<64) | res;
95
+			}
96
+			val flags[32] <= fdispatch_fget_flags();
97
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
98
+		}
99
+		FSUB.D {
100
+			encoding: b0000101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
101
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
102
+			// F[rd]f <= F[rs1]f - F[rs2]f;
103
+			val res[64] <= fdispatch_fsub_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
104
+			if(FLEN==64)
105
+				F[rd] <= res;
106
+			else { // NaN boxing
107
+				val upper[FLEN] <= -1;
108
+				F[rd] <= (upper<<64) | res;
109
+			}
110
+			val flags[32] <= fdispatch_fget_flags();
111
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
112
+		}
113
+		FMUL.D {
114
+			encoding: b0001001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
115
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
116
+			// F[rd]f <= F[rs1]f * F[rs2]f;
117
+			val res[64] <= fdispatch_fmul_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
118
+			if(FLEN==64)
119
+				F[rd] <= res;
120
+			else { // NaN boxing
121
+				val upper[FLEN] <= -1;
122
+				F[rd] <= (upper<<64) | res;
123
+			}
124
+			val flags[32] <= fdispatch_fget_flags();
125
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
126
+		}
127
+		FDIV.D {
128
+			encoding: b0001101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
129
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
130
+			// F[rd]f <= F[rs1]f / F[rs2]f;
131
+			val res[64] <= fdispatch_fdiv_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
132
+			if(FLEN==64)
133
+				F[rd] <= res;
134
+			else { // NaN boxing
135
+				val upper[FLEN] <= -1;
136
+				F[rd] <= (upper<<64) | res;
137
+			}
138
+			val flags[32] <= fdispatch_fget_flags();
139
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
140
+		}
141
+		FSQRT.D {
142
+			encoding: b0101101 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
143
+			args_disass:"x%rd$d, f%rs1$d";
144
+			//F[rd]f<=sqrt(F[rs1]f);
145
+			val res[64] <= fdispatch_fsqrt_d(F[rs1]{64}, choose(rm<7, rm{8}, FCSR{8}));
146
+			if(FLEN==64)
147
+				F[rd] <= res;
148
+			else { // NaN boxing
149
+				val upper[FLEN] <= -1;
150
+				F[rd] <= (upper<<64) | res;
151
+			}
152
+			val flags[32] <= fdispatch_fget_flags();
153
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
154
+		}
155
+		FSGNJ.D {
156
+			encoding: b0010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
157
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
158
+			val res[64] <= (F[rs1]{64} & 0x7fffffff) | (F[rs2]{64} & 0x80000000);
159
+			if(FLEN==64)
160
+				F[rd] <= res;
161
+			else { // NaN boxing
162
+				val upper[FLEN] <= -1;
163
+				F[rd] <= (upper<<64) | res;
164
+			}
165
+		}
166
+		FSGNJN.D {
167
+			encoding: b0010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
168
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
169
+			val res[64] <= (F[rs1]{64} & 0x7fffffff) | (~F[rs2]{64} & 0x80000000);
170
+			if(FLEN==64)
171
+				F[rd] <= res;
172
+			else { // NaN boxing
173
+				val upper[FLEN] <= -1;
174
+				F[rd] <= (upper<<64) | res;
175
+			}
176
+		}
177
+		FSGNJX.D {
178
+			encoding: b0010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
179
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
180
+			val res[64] <= F[rs1]{64} ^ (F[rs2]{64} & 0x80000000);
181
+			if(FLEN==64)
182
+				F[rd] <= res;
183
+			else { // NaN boxing
184
+				val upper[FLEN] <= -1;
185
+				F[rd] <= (upper<<64) | res;
186
+			}
187
+		}
188
+		FMIN.D  {
189
+			encoding: b0010101 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
190
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
191
+			//F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
192
+			val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32));
193
+			if(FLEN==64)
194
+				F[rd] <= res;
195
+			else { // NaN boxing
196
+				val upper[FLEN] <= -1;
197
+				F[rd] <= (upper<<64) | res;
198
+			}
199
+			val flags[32] <= fdispatch_fget_flags();
200
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
201
+		}
202
+		FMAX.D {
203
+			encoding: b0010101 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
204
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
205
+			//F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
206
+			val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32));
207
+			if(FLEN==64)
208
+				F[rd] <= res;
209
+			else { // NaN boxing
210
+				val upper[FLEN] <= -1;
211
+				F[rd] <= (upper<<64) | res;
212
+			}
213
+			val flags[32] <= fdispatch_fget_flags();
214
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
215
+		}
216
+		FCVT.S.D {
217
+			encoding: b0100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
218
+			args_disass:"f%rd$d, f%rs1$d";
219
+			val res[32] <= fdispatch_fconv_d2f(F[rs1], rm{8});
220
+			// NaN boxing
221
+			val upper[FLEN] <= -1;
222
+			F[rd] <= upper<<32 | zext(res, FLEN);
223
+		}
224
+		FCVT.D.S {
225
+			encoding: b0100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
226
+			args_disass:"f%rd$d, f%rs1$d";
227
+			val res[64] <= fdispatch_fconv_f2d(F[rs1]{32}, rm{8});
228
+			if(FLEN==64){
229
+				F[rd] <= res;
230
+			} else {
231
+				val upper[FLEN] <= -1;
232
+				F[rd] <= (upper<<64) | res;
233
+			}
234
+		}
235
+		FEQ.D {
236
+			encoding: b1010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
237
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
238
+			X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32));
239
+			val flags[32] <= fdispatch_fget_flags();
240
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
241
+		}
242
+		FLT.D {
243
+			encoding: b1010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
244
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
245
+			X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(2, 32));
246
+			val flags[32] <= fdispatch_fget_flags();
247
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
248
+		}
249
+		FLE.D {
250
+			encoding: b1010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
251
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
252
+			X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32));
253
+			val flags[32] <= fdispatch_fget_flags();
254
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
255
+		}
256
+		FCLASS.D {
257
+			encoding: b1110001 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
258
+			args_disass:"x%rd$d, f%rs1$d";
259
+			X[rd]<=fdispatch_fclass_d(F[rs1]{64});
260
+		}
261
+		FCVT.W.D {
262
+			encoding: b1100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
263
+			args_disass:"x%rd$d, f%rs1$d";
264
+			X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(0, 32), rm{8}), XLEN);
265
+			val flags[32] <= fdispatch_fget_flags();
266
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
267
+		}
268
+		FCVT.WU.D {
269
+			encoding: b1100001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
270
+			args_disass:"x%rd$d, f%rs1$d";
271
+			X[rd]<= zext(fdispatch_fcvt_d(F[rs1]{64}, zext(1, 32), rm{8}), XLEN);
272
+			val flags[32] <= fdispatch_fget_flags();
273
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
274
+		}
275
+		FCVT.D.W {
276
+			encoding: b1101001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
277
+			args_disass:"f%rd$d, x%rs1$d";
278
+			val res[64] <= fdispatch_fcvt_d(sext(X[rs1],64), zext(2, 32), rm{8});
279
+			if(FLEN==64)
280
+				F[rd] <= res;
281
+			else { // NaN boxing
282
+				val upper[FLEN] <= -1;
283
+				F[rd] <= (upper<<64) | res;
284
+			}
285
+		}
286
+		FCVT.D.WU {
287
+			encoding: b1101001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
288
+			args_disass:"f%rd$d, x%rs1$d";
289
+			val res[64] <=fdispatch_fcvt_d(zext(X[rs1],64), zext(3,32), rm{8});
290
+			if(FLEN==64)
291
+				F[rd] <= res;
292
+			else { // NaN boxing
293
+				val upper[FLEN] <= -1;
294
+				F[rd] <= (upper<<64) | res;
295
+			}
296
+		}
297
+	}
298
+}

+ 210
- 21
riscv/gen_input/RV32F.core_desc View File

@@ -2,104 +2,293 @@ import "RV32IBase.core_desc"
2 2
 
3 3
 InsructionSet RV32F extends RV32IBase{
4 4
 	constants {
5
-		FLEN, fcsr
5
+		FLEN, FFLAG_MASK := 0x1f
6 6
 	} 
7 7
 	registers {
8
-		[31:0]    F[FLEN]
8
+		[31:0]    F[FLEN],  FCSR[32]
9 9
     }	
10 10
 	instructions{
11 11
 		FLW {
12 12
 			encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
13
+			args_disass:"f%rd$d, %imm%(x%rs1$d)";
13 14
 			val offs[XLEN] <= X[rs1]+imm;
14
-			F[rd]<=MEM[offs];
15
+			val res[32] <= MEM[offs]{32};
16
+			if(FLEN==32)
17
+				F[rd] <= res;
18
+			else { // NaN boxing
19
+				val upper[FLEN] <= -1;
20
+				F[rd] <= (upper<<32) | zext(res, FLEN);
21
+			}
15 22
 		}
16 23
 		FSW {
17 24
 			encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
25
+			args_disass:"f%rs2$d, %imm%(x%rs1$d)";
18 26
 			val offs[XLEN] <= X[rs1]+imm;
19
-			MEM[offs]<=F[rs2];
27
+			MEM[offs]{32}<=F[rs2]{32};
20 28
 		}
21 29
 		FMADD.S {
22 30
 			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
23
-			F[rd]f<= F[rs1]f * F[rs2]f * F[rs3]f;
31
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
32
+			//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
33
+			val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
34
+			if(FLEN==32)
35
+				F[rd] <= res;
36
+			else { // NaN boxing
37
+				val upper[FLEN] <= -1;
38
+				F[rd] <= (upper<<32) | zext(res, FLEN);
39
+			}
40
+			val flags[32] <= fdispatch_fget_flags();
41
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
24 42
 		}
25 43
 		FMSUB.S {
26 44
 			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
27
-			F[rd]f<=F[rs1]f * F[rs2]f -F[rs3]f;
28
-		}
29
-		FNMSUB.S {
30
-			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
31
-			F[rd]f<=-F[rs1]f * F[rs2]f- F[rs3]f;
45
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
46
+			//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
47
+			val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
48
+			if(FLEN==32)
49
+				F[rd] <= res;
50
+			else { // NaN boxing
51
+				val upper[FLEN] <= -1;
52
+				F[rd] <= (upper<<32) | zext(res, FLEN);
53
+			}
54
+			val flags[32] <= fdispatch_fget_flags();
55
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};	
32 56
 		}
33 57
 		FNMADD.S {
34 58
 			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
35
-			F[rd]f<=-F[rs1]f*F[rs2]f+F[rs3]f;
59
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
60
+			//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
61
+			val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
62
+			if(FLEN==32)
63
+				F[rd] <= res;
64
+			else { // NaN boxing
65
+				val upper[FLEN] <= -1;
66
+				F[rd] <= (upper<<32) | zext(res, FLEN);
67
+			}
68
+			val flags[32] <= fdispatch_fget_flags();
69
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
70
+		}
71
+		FNMSUB.S {
72
+			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
73
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
74
+			//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
75
+			val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
76
+			if(FLEN==32)
77
+				F[rd] <= res;
78
+			else { // NaN boxing
79
+				val upper[FLEN] <= -1;
80
+				F[rd] <= (upper<<32) | zext(res, FLEN);
81
+			}
82
+			val flags[32] <= fdispatch_fget_flags();
83
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
36 84
 		}
37 85
 		FADD.S {
38 86
 			encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
39
-			F[rd]f <= F[rs1]f + F[rs2]f;
87
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
88
+			// F[rd]f <= F[rs1]f + F[rs2]f;
89
+			val res[32] <= fdispatch_fadd_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
90
+			if(FLEN==32)
91
+				F[rd] <= res;
92
+			else { // NaN boxing
93
+				val upper[FLEN] <= -1;
94
+				F[rd] <= (upper<<32) | zext(res, FLEN);
95
+			}
96
+			val flags[32] <= fdispatch_fget_flags();
97
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
40 98
 		}
41 99
 		FSUB.S {
42 100
 			encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
43
-			F[rd]f <= F[rs1]f - F[rs2]f;
101
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
102
+			// F[rd]f <= F[rs1]f - F[rs2]f;
103
+			val res[32] <= fdispatch_fsub_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
104
+			if(FLEN==32)
105
+				F[rd] <= res;
106
+			else { // NaN boxing
107
+				val upper[FLEN] <= -1;
108
+				F[rd] <= (upper<<32) | zext(res, FLEN);
109
+			}
110
+			val flags[32] <= fdispatch_fget_flags();
111
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
44 112
 		}
45 113
 		FMUL.S {
46 114
 			encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
47
-			F[rd]f <= F[rs1]f * F[rs2];
115
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
116
+			// F[rd]f <= F[rs1]f * F[rs2]f;
117
+			val res[32] <= fdispatch_fmul_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
118
+			if(FLEN==32)
119
+				F[rd] <= res;
120
+			else { // NaN boxing
121
+				val upper[FLEN] <= -1;
122
+				F[rd] <= (upper<<32) | zext(res, FLEN);
123
+			}
124
+			val flags[32] <= fdispatch_fget_flags();
125
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
48 126
 		}
49 127
 		FDIV.S {
50 128
 			encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
51
-			F[rd]f <= F[rs1]f / F[rs2]f;
129
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
130
+			// F[rd]f <= F[rs1]f / F[rs2]f;
131
+			val res[32] <= fdispatch_fdiv_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
132
+			if(FLEN==32)
133
+				F[rd] <= res;
134
+			else { // NaN boxing
135
+				val upper[FLEN] <= -1;
136
+				F[rd] <= (upper<<32) | zext(res, FLEN);
137
+			}
138
+			val flags[32] <= fdispatch_fget_flags();
139
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
52 140
 		}
53 141
 		FSQRT.S {
54 142
 			encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
55
-			F[rd]f<=sqrt(F[rs1]f);
143
+			args_disass:"f%rd$d, f%rs1$d";
144
+			//F[rd]f<=sqrt(F[rs1]f);
145
+			val res[32] <= fdispatch_fsqrt_s(F[rs1]{32}, choose(rm<7, rm{8}, FCSR{8}));
146
+			if(FLEN==32)
147
+				F[rd] <= res;
148
+			else { // NaN boxing
149
+				val upper[FLEN] <= -1;
150
+				F[rd] <= (upper<<32) | zext(res, FLEN);
151
+			}
152
+			val flags[32] <= fdispatch_fget_flags();
153
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
56 154
 		}
57 155
 		FSGNJ.S {
58 156
 			encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
157
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
158
+			val res[32] <= (F[rs1]{32} & 0x7fffffff) | (F[rs2]{32} & 0x80000000);
159
+			if(FLEN==32)
160
+				F[rd] <= res;
161
+			else { // NaN boxing
162
+				val upper[FLEN] <= -1;
163
+				F[rd] <= (upper<<32) | zext(res, FLEN);
164
+			}
59 165
 		}
60 166
 		FSGNJN.S {
61 167
 			encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
168
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
169
+			val res[32] <= (F[rs1]{32} & 0x7fffffff) | (~F[rs2]{32} & 0x80000000);
170
+			if(FLEN==32)
171
+				F[rd] <= res;
172
+			else { // NaN boxing
173
+				val upper[FLEN] <= -1;
174
+				F[rd] <= (upper<<32) | zext(res, FLEN);
175
+			}
62 176
 		}
63 177
 		FSGNJX.S {
64 178
 			encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
179
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
180
+			val res[32] <= F[rs1]{32} ^ (F[rs2]{32} & 0x80000000);
181
+			if(FLEN==32)
182
+				F[rd] <= res;
183
+			else { // NaN boxing
184
+				val upper[FLEN] <= -1;
185
+				F[rd] <= (upper<<32) | zext(res, FLEN);
186
+			}
65 187
 		}
66 188
 		FMIN.S  {
67 189
 			encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
68
-			F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
190
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
191
+			//F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
192
+			val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
193
+			if(FLEN==32)
194
+				F[rd] <= res;
195
+			else { // NaN boxing
196
+				val upper[FLEN] <= -1;
197
+				F[rd] <= (upper<<32) | zext(res, FLEN);
198
+			}
199
+			val flags[32] <= fdispatch_fget_flags();
200
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
69 201
 		}
70 202
 		FMAX.S {
71 203
 			encoding: b0010100 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
72
-			F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
204
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
205
+			//F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
206
+			val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
207
+			if(FLEN==32)
208
+				F[rd] <= res;
209
+			else { // NaN boxing
210
+				val upper[FLEN] <= -1;
211
+				F[rd] <= (upper<<32) | zext(res, FLEN);
212
+			}
213
+			val flags[32] <= fdispatch_fget_flags();
214
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
73 215
 		}
74 216
 		FCVT.W.S {
75 217
 			encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
218
+			args_disass:"x%rd$d, f%rs1$d";
219
+			X[rd]<= sext(fdispatch_fcvt_s(F[rs1]{32}, zext(0, 32), rm{8}), XLEN);
220
+			val flags[32] <= fdispatch_fget_flags();
221
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
76 222
 		}
77 223
 		FCVT.WU.S {
78 224
 			encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
79
-		}
80
-		FMV.X.W {
81
-			encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
225
+			args_disass:"x%rd$d, f%rs1$d";
226
+			X[rd]<= zext(fdispatch_fcvt_s(F[rs1]{32}, zext(1, 32), rm{8}), XLEN);
227
+			val flags[32] <= fdispatch_fget_flags();
228
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
82 229
 		}
83 230
 		FEQ.S {
84 231
 			encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
232
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
233
+			X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
234
+			val flags[32] <= fdispatch_fget_flags();
235
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
85 236
 		}
86 237
 		FLT.S {
87 238
 			encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
239
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
240
+			X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32));
241
+			val flags[32] <= fdispatch_fget_flags();
242
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
88 243
 		}
89 244
 		FLE.S {
90 245
 			encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
246
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
247
+			X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
248
+			val flags[32] <= fdispatch_fget_flags();
249
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
91 250
 		}
92 251
 		FCLASS.S {
93 252
 			encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
253
+			args_disass:"x%rd$d, f%rs1$d";
254
+			X[rd]<=fdispatch_fclass_s(F[rs1]{32});
94 255
 		}
95 256
 		FCVT.S.W {
96 257
 			encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
258
+			args_disass:"f%rd$d, x%rs1$d";
259
+			val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
260
+			if(FLEN==32)
261
+				F[rd] <= res;
262
+			else { // NaN boxing
263
+				val upper[FLEN] <= -1;
264
+				F[rd] <= (upper<<32) | zext(res, FLEN);
265
+			}
97 266
 		}
98 267
 		FCVT.S.WU {
99 268
 			encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
269
+			args_disass:"f%rd$d, x%rs1$d";
270
+			val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
271
+			if(FLEN==32)
272
+				F[rd] <= res;
273
+			else { // NaN boxing
274
+				val upper[FLEN] <= -1;
275
+				F[rd] <= (upper<<32) | zext(res, FLEN);
276
+			}
277
+		}
278
+		FMV.X.W {
279
+			encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
280
+			args_disass:"x%rd$d, f%rs1$d";
281
+			X[rd]<=sext(F[rs1]{32});
100 282
 		}
101 283
 		FMV.W.X {
102 284
 			encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
285
+			args_disass:"f%rd$d, x%rs1$d";
286
+			if(FLEN==32)
287
+				F[rd] <= X[rs1];
288
+			else { // NaN boxing
289
+				val upper[FLEN] <= -1;
290
+				F[rd] <= (upper<<32) | zext(X[rs1], FLEN);
291
+			}
103 292
 		}
104 293
 	}
105 294
 }

+ 5
- 5
riscv/gen_input/RV32IBase.core_desc View File

@@ -1,12 +1,12 @@
1 1
 InsructionSet RV32IBase {
2 2
 	constants {
3 3
 		XLEN,
4
-		XLEN_BIT_MASK,
5 4
 		PCLEN,
6
-		fence,
7
-		fencei,
8
-		fencevmal,
9
-		fencevmau
5
+		XLEN_BIT_MASK:=0x1f,
6
+        fence:=0,
7
+        fencei:=1,
8
+        fencevmal:=2,
9
+        fencevmau:=3
10 10
 	}
11 11
 	
12 12
 	address_spaces { 

+ 27
- 11
riscv/gen_input/RV32M.core_desc View File

@@ -2,14 +2,14 @@ import "RV32IBase.core_desc"
2 2
 
3 3
 InsructionSet RV32M extends RV32IBase {
4 4
 	constants {
5
-		XLEN2
5
+		MAXLEN:=128
6 6
 	}
7 7
 	instructions{       
8 8
 		MUL{
9 9
 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
10 10
 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
11 11
 		    if(rd != 0){
12
-		        val res[XLEN2] <= zext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
12
+		        val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
13 13
 		    	X[rd]<= zext(res , XLEN);
14 14
 		    }
15 15
 		}
@@ -17,7 +17,7 @@ InsructionSet RV32M extends RV32IBase {
17 17
 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
18 18
 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
19 19
 		    if(rd != 0){
20
-		        val res[XLEN2] <= sext(X[rs1], XLEN2) * sext(X[rs2], XLEN2);
20
+		        val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN);
21 21
                 X[rd]<= zext(res >> XLEN, XLEN);
22 22
 		    }
23 23
 		}
@@ -25,7 +25,7 @@ InsructionSet RV32M extends RV32IBase {
25 25
 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
26 26
 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
27 27
 		    if(rd != 0){
28
-                val res[XLEN2] <= sext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
28
+                val res[MAXLEN] <= sext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
29 29
                 X[rd]<= zext(res >> XLEN, XLEN);
30 30
 		    }
31 31
 		}
@@ -33,7 +33,7 @@ InsructionSet RV32M extends RV32IBase {
33 33
 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
34 34
 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
35 35
 		    if(rd != 0){
36
-                val res[XLEN2] <= zext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
36
+                val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
37 37
                 X[rd]<= zext(res >> XLEN, XLEN);
38 38
 		    }
39 39
 		}
@@ -41,9 +41,17 @@ InsructionSet RV32M extends RV32IBase {
41 41
 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011;
42 42
 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
43 43
 		    if(rd != 0){
44
-		    	if(X[rs2]!=0)
45
-		    		X[rd] <= sext(X[rs1], 32) / sext(X[rs2], 32);
46
-		    	else 
44
+		    	if(X[rs2]!=0){
45
+		    		val M1[XLEN] <= -1;
46
+		    		val MMIN[XLEN] <= -1<<(XLEN-1);
47
+		    		if(X[rs1]s==MMIN's)
48
+			    		if(X[rs2]s==M1's)
49
+			    			X[rd]<=MMIN;
50
+		    			else
51
+			    			X[rd] <= X[rs1]s / X[rs2]s;
52
+	    			else
53
+		    			X[rd] <= X[rs1]s / X[rs2]s;
54
+		    	}else 
47 55
 		    		X[rd] <= -1;
48 56
 		    }
49 57
 		}
@@ -61,9 +69,17 @@ InsructionSet RV32M extends RV32IBase {
61 69
 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
62 70
 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
63 71
 		    if(rd != 0){
64
-		    	if(X[rs2]!=0)
65
-		    		X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
66
-		    	else 
72
+		    	if(X[rs2]!=0) {
73
+		    		val M1[XLEN] <= -1;
74
+		    		val MMIN[XLEN] <= -1<<(XLEN-1);
75
+		    		if(X[rs1]s==MMIN's)
76
+			    		if(X[rs2]s==M1's)
77
+			    			X[rd] <= 0;
78
+			    		else
79
+			    			X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
80
+	    			else
81
+		    			X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
82
+		    	} else 
67 83
 		    		X[rd] <= X[rs1];
68 84
 		    }
69 85
 		}

+ 19
- 14
riscv/gen_input/minres_rv.core_desc View File

@@ -2,24 +2,34 @@ import "RV32IBase.core_desc"
2 2
 import "RV32M.core_desc"
3 3
 import "RV32A.core_desc"
4 4
 import "RV32C.core_desc"
5
+import "RV32F.core_desc"
6
+import "RV32D.core_desc"
5 7
 import "RV64IBase.core_desc"
6 8
 //import "RV64M.core_desc"
7 9
 import "RV64A.core_desc"
8 10
 
9 11
 
10
-Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32CI {
12
+Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
11 13
     template:"vm_riscv.in.cpp";
12 14
     constants {
13 15
         XLEN:=32;
14
-        XLEN2:=64;
15
-        XLEN_BIT_MASK:=0x1f;
16 16
         PCLEN:=32;
17
-        fence:=0;
18
-        fencei:=1;
19
-        fencevmal:=2;
20
-        fencevmau:=3;
17
+        // definitions for the architecture wrapper
21 18
         //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
22
-        MISA_VAL:=0b01000000000101000001000100000001;
19
+        MISA_VAL:=0b01000000000101000001000100000101;
20
+        PGSIZE := 4096; //1 << 12;
21
+        PGMASK := 4095; //PGSIZE-1
22
+    }
23
+}
24
+
25
+Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32DC {
26
+    constants {
27
+        XLEN:=32;
28
+        FLEN:=64;
29
+        PCLEN:=32;
30
+        // definitions for the architecture wrapper
31
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
32
+        MISA_VAL:=0b01000000000101000001000100101101;
23 33
         PGSIZE := 4096; //1 << 12;
24 34
         PGMASK := 4095; //PGSIZE-1
25 35
     }
@@ -30,13 +40,8 @@ Core RV64IA provides RV64IBase, RV64A, RV32A {
30 40
     template:"vm_riscv.in.cpp";
31 41
     constants {
32 42
         XLEN:=64;
33
-        XLEN2:=128;
34
-        XLEN_BIT_MASK:=0x3f;
35 43
         PCLEN:=64;
36
-        fence:=0;
37
-        fencei:=1;
38
-        fencevmal:=2;
39
-        fencevmau:=3;
44
+        // definitions for the architecture wrapper
40 45
         //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
41 46
         MISA_VAL:=0b10000000000001000000000100000001;
42 47
         PGSIZE := 4096; //1 << 12;

+ 12
- 8
riscv/gen_input/templates/incl-CORENAME.h.gtl View File

@@ -56,6 +56,8 @@ struct traits<${coreDef.name.toLowerCase()}> {
56 56
     
57 57
     enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
58 58
 
59
+    constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
60
+
59 61
     enum reg_e {<%
60 62
      	allRegs.each { reg -> 
61 63
     		if( reg instanceof RegisterFile) {
@@ -78,8 +80,6 @@ struct traits<${coreDef.name.toLowerCase()}> {
78 80
 
79 81
     using addr_t = uint${addrDataWidth}_t;
80 82
 
81
-    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
82
-
83 83
     using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
84 84
 
85 85
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
@@ -99,7 +99,6 @@ struct traits<${coreDef.name.toLowerCase()}> {
99 99
     enum sreg_flag_e {FLAGS};
100 100
 
101 101
     enum mem_type_e {${allSpaces.collect{s -> s.name}.join(', ')}};
102
-
103 102
 };
104 103
 
105 104
 struct ${coreDef.name.toLowerCase()}: public arch_if {
@@ -112,8 +111,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
112 111
     ${coreDef.name.toLowerCase()}();
113 112
     ~${coreDef.name.toLowerCase()}();
114 113
 
115
-	const std::string core_type_name() const override {return traits<${coreDef.name.toLowerCase()}>::core_type;}
116
-	
117 114
     void reset(uint64_t address=0) override;
118 115
 
119 116
     uint8_t* get_regs_base_ptr() override;
@@ -158,9 +155,16 @@ protected:
158 155
     } reg;
159 156
 
160 157
     std::array<address_type, 4> addr_mode;
161
-
162
-    uint64_t cycles = 0;
163
-
158
+    
159
+<%
160
+def fcsr = allRegs.find {it.name=='FCSR'}
161
+if(fcsr != null) {%>
162
+	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
163
+	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
164
+<%} else { %>
165
+	uint32_t get_fcsr(){return 0;}
166
+	void set_fcsr(uint32_t val){}
167
+<%}%>
164 168
 };
165 169
 
166 170
 }

+ 3
- 2
riscv/gen_input/templates/src-CORENAME.cpp.gtl View File

@@ -68,6 +68,7 @@ uint8_t* ${coreDef.name.toLowerCase()}::get_regs_base_ptr(){
68 68
     return reinterpret_cast<uint8_t*>(&reg);
69 69
 }
70 70
 
71
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::v2p(const iss::addr_t& pc) {
72
-    return phys_addr_t(pc); //change logical address to physical address
71
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
72
+    return phys_addr_t(pc); // change logical address to physical address
73 73
 }
74
+

+ 11
- 3
riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl View File

@@ -48,6 +48,12 @@
48 48
 #include <array>
49 49
 
50 50
 namespace iss {
51
+namespace vm {
52
+namespace fp_impl{
53
+void add_fp_functions_2_module(llvm::Module *, unsigned);
54
+}
55
+}
56
+
51 57
 namespace ${coreDef.name.toLowerCase()} {
52 58
 using namespace iss::arch;
53 59
 using namespace llvm;
@@ -81,6 +87,11 @@ protected:
81 87
         return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
82 88
     }
83 89
 
90
+    void setup_module(llvm::Module* m) override {
91
+        super::setup_module(m);
92
+        vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE);
93
+    }
94
+
84 95
     inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal,
85 96
                                    unsigned size) const {
86 97
         return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
@@ -101,7 +112,6 @@ protected:
101 112
 
102 113
     void gen_trap_check(llvm::BasicBlock *bb);
103 114
 
104
-
105 115
     inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) {
106 116
         return this->builder.CreateLoad(get_reg_ptr(i), false);
107 117
     }
@@ -310,8 +320,6 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBl
310 320
                           bb, this->trap_blk, 1);
311 321
 }
312 322
 
313
-} // namespace ${coreDef.name.toLowerCase()}
314
-
315 323
 template <>
316 324
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
317 325
     std::unique_ptr<${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>> ret =

riscv/src/internal/vm_riscv.in.cpp → riscv/gen_input/templates/vm_riscv.in.cpp View File


+ 45
- 1
riscv/incl/iss/arch/riscv_hart_msu_vp.h View File

@@ -48,13 +48,14 @@
48 48
 #include <util/sparse_array.h>
49 49
 #include <util/bit_field.h>
50 50
 #include <array>
51
+#include <type_traits>
51 52
 
52 53
 namespace iss {
53 54
 namespace arch {
54 55
 
55 56
 enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 };
56 57
 
57
-enum csr_name {
58
+enum riscv_csr {
58 59
     /* user-level CSR */
59 60
     // User Trap Setup
60 61
     ustatus = 0x000,
@@ -537,6 +538,8 @@ private:
537 538
     iss::status write_ip(unsigned addr, reg_t val);
538 539
     iss::status read_satp(unsigned addr, reg_t &val);
539 540
     iss::status write_satp(unsigned addr, reg_t val);
541
+    iss::status read_fcsr(unsigned addr, reg_t& val);
542
+    iss::status write_fcsr(unsigned addr, reg_t val);
540 543
 protected:
541 544
     void check_interrupt();
542 545
 };
@@ -579,6 +582,13 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
579 582
     csr_wr_cb[uie] = &riscv_hart_msu_vp<BASE>::write_ie;
580 583
     csr_rd_cb[satp] = &riscv_hart_msu_vp<BASE>::read_satp;
581 584
     csr_wr_cb[satp] = &riscv_hart_msu_vp<BASE>::write_satp;
585
+    csr_rd_cb[fcsr] = &riscv_hart_msu_vp<BASE>::read_fcsr;
586
+    csr_wr_cb[fcsr] = &riscv_hart_msu_vp<BASE>::write_fcsr;
587
+    csr_rd_cb[fflags] = &riscv_hart_msu_vp<BASE>::read_fcsr;
588
+    csr_wr_cb[fflags] = &riscv_hart_msu_vp<BASE>::write_fcsr;
589
+    csr_rd_cb[frm] = &riscv_hart_msu_vp<BASE>::read_fcsr;
590
+    csr_wr_cb[frm] = &riscv_hart_msu_vp<BASE>::write_fcsr;
591
+
582 592
 }
583 593
 
584 594
 template <typename BASE> std::pair<uint64_t,bool> riscv_hart_msu_vp<BASE>::load_file(std::string name, int type) {
@@ -940,6 +950,39 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_satp(unsigne
940 950
     update_vm_info();
941 951
     return iss::Ok;
942 952
 }
953
+template<typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_fcsr(unsigned addr, reg_t& val) {
954
+    switch(addr){
955
+    case 1: //fflags, 4:0
956
+        val = bit_sub<0, 5>(this->get_fcsr());
957
+        break;
958
+    case 2: // frm, 7:5
959
+        val = bit_sub<5, 3>(this->get_fcsr());
960
+       break;
961
+    case 3: // fcsr
962
+        val=this->get_fcsr();
963
+        break;
964
+    default:
965
+        return iss::Err;
966
+    }
967
+    return iss::Ok;
968
+}
969
+
970
+template<typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_fcsr(unsigned addr, reg_t val) {
971
+    switch(addr){
972
+    case 1: //fflags, 4:0
973
+        this->set_fcsr( (this->get_fcsr() & 0xffffffe0) | (val&0x1f));
974
+        break;
975
+    case 2: // frm, 7:5
976
+        this->set_fcsr( (this->get_fcsr() & 0xffffff1f) | ((val&0x7)<<5));
977
+       break;
978
+    case 3: // fcsr
979
+        this->set_fcsr(val&0xff);
980
+        break;
981
+    default:
982
+        return iss::Err;
983
+    }
984
+    return iss::Ok;
985
+}
943 986
 
944 987
 template <typename BASE>
945 988
 iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
@@ -1299,4 +1342,5 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::wait_until(uint64_t flags
1299 1342
 }
1300 1343
 }
1301 1344
 
1345
+
1302 1346
 #endif /* _RISCV_CORE_H_ */

+ 277
- 0
riscv/incl/iss/arch/rv32gc.h View File

@@ -0,0 +1,277 @@
1
+////////////////////////////////////////////////////////////////////////////////
2
+// Copyright (C) 2017, MINRES Technologies GmbH
3
+// All rights reserved.
4
+// 
5
+// Redistribution and use in source and binary forms, with or without
6
+// modification, are permitted provided that the following conditions are met:
7
+// 
8
+// 1. Redistributions of source code must retain the above copyright notice,
9
+//    this list of conditions and the following disclaimer.
10
+// 
11
+// 2. Redistributions in binary form must reproduce the above copyright notice,
12
+//    this list of conditions and the following disclaimer in the documentation
13
+//    and/or other materials provided with the distribution.
14
+// 
15
+// 3. Neither the name of the copyright holder nor the names of its contributors
16
+//    may be used to endorse or promote products derived from this software
17
+//    without specific prior written permission.
18
+// 
19
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+// POSSIBILITY OF SUCH DAMAGE.
30
+// 
31
+////////////////////////////////////////////////////////////////////////////////
32
+
33
+#ifndef _RV32GC_H_
34
+#define _RV32GC_H_
35
+
36
+#include <iss/arch_if.h>
37
+#include <iss/vm_if.h>
38
+#include <iss/arch/traits.h>
39
+#include <array>
40
+
41
+namespace iss {
42
+namespace arch {
43
+
44
+struct rv32gc;
45
+
46
+template<>
47
+struct traits<rv32gc> {
48
+
49
+	constexpr static char const* const core_type = "RV32GC";
50
+    
51
+    enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=1075056941, PGSIZE=4096, PGMASK=4095};
52
+
53
+    constexpr static unsigned FP_REGS_SIZE = 64;
54
+
55
+    enum reg_e {
56
+        X0,
57
+        X1,
58
+        X2,
59
+        X3,
60
+        X4,
61
+        X5,
62
+        X6,
63
+        X7,
64
+        X8,
65
+        X9,
66
+        X10,
67
+        X11,
68
+        X12,
69
+        X13,
70
+        X14,
71
+        X15,
72
+        X16,
73
+        X17,
74
+        X18,
75
+        X19,
76
+        X20,
77
+        X21,
78
+        X22,
79
+        X23,
80
+        X24,
81
+        X25,
82
+        X26,
83
+        X27,
84
+        X28,
85
+        X29,
86
+        X30,
87
+        X31,
88
+        PC,
89
+        F0,
90
+        F1,
91
+        F2,
92
+        F3,
93
+        F4,
94
+        F5,
95
+        F6,
96
+        F7,
97
+        F8,
98
+        F9,
99
+        F10,
100
+        F11,
101
+        F12,
102
+        F13,
103
+        F14,
104
+        F15,
105
+        F16,
106
+        F17,
107
+        F18,
108
+        F19,
109
+        F20,
110
+        F21,
111
+        F22,
112
+        F23,
113
+        F24,
114
+        F25,
115
+        F26,
116
+        F27,
117
+        F28,
118
+        F29,
119
+        F30,
120
+        F31,
121
+        FCSR,
122
+        NUM_REGS,
123
+        NEXT_PC=NUM_REGS,
124
+        TRAP_STATE,
125
+        PENDING_TRAP,
126
+        MACHINE_STATE,
127
+        ICOUNT
128
+    };
129
+
130
+    using reg_t = uint32_t;
131
+
132
+    using addr_t = uint32_t;
133
+
134
+    using code_word_t = uint32_t; //TODO: check removal
135
+
136
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
137
+
138
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
139
+
140
+    constexpr static unsigned reg_bit_width(unsigned r) {
141
+        constexpr std::array<const uint32_t, 71> RV32GC_reg_size{{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,32,32,64}};
142
+        return RV32GC_reg_size[r];
143
+    }
144
+
145
+    constexpr static unsigned reg_byte_offset(unsigned r) {
146
+    	constexpr std::array<const uint32_t, 72> RV32GC_reg_byte_offset{{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,280,288,296,304,312,320,328,336,344,352,360,368,376,384,392,396,400,404,408,416,424}};
147
+        return RV32GC_reg_byte_offset[r];
148
+    }
149
+
150
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
151
+
152
+    enum sreg_flag_e {FLAGS};
153
+
154
+    enum mem_type_e {MEM, CSR, FENCE, RES};
155
+};
156
+
157
+struct rv32gc: public arch_if {
158
+
159
+    using virt_addr_t = typename traits<rv32gc>::virt_addr_t;
160
+    using phys_addr_t = typename traits<rv32gc>::phys_addr_t;
161
+    using reg_t =  typename traits<rv32gc>::reg_t;
162
+    using addr_t = typename traits<rv32gc>::addr_t;
163
+
164
+    rv32gc();
165
+    ~rv32gc();
166
+
167
+    void reset(uint64_t address=0) override;
168
+
169
+    uint8_t* get_regs_base_ptr() override;
170
+    /// deprecated
171
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
172
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
173
+    /// deprecated
174
+    bool get_flag(int flag) override {return false;}
175
+    void set_flag(int, bool value) override {};
176
+    /// deprecated
177
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
178
+
179
+    uint64_t get_icount() { return reg.icount;}
180
+
181
+    inline phys_addr_t v2p(const iss::addr_t& addr){
182
+        if(addr.space != traits<rv32gc>::MEM ||
183
+                addr.type == iss::address_type::PHYSICAL ||
184
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL){
185
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<rv32gc>::addr_mask);
186
+        } else
187
+            return virt2phys(addr);
188
+    }
189
+
190
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
191
+
192
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
193
+
194
+protected:
195
+    struct RV32GC_regs {
196
+        uint32_t X0 = 0;
197
+        uint32_t X1 = 0;
198
+        uint32_t X2 = 0;
199
+        uint32_t X3 = 0;
200
+        uint32_t X4 = 0;
201
+        uint32_t X5 = 0;
202
+        uint32_t X6 = 0;
203
+        uint32_t X7 = 0;
204
+        uint32_t X8 = 0;
205
+        uint32_t X9 = 0;
206
+        uint32_t X10 = 0;
207
+        uint32_t X11 = 0;
208
+        uint32_t X12 = 0;
209
+        uint32_t X13 = 0;
210
+        uint32_t X14 = 0;
211
+        uint32_t X15 = 0;
212
+        uint32_t X16 = 0;
213
+        uint32_t X17 = 0;
214
+        uint32_t X18 = 0;
215
+        uint32_t X19 = 0;
216
+        uint32_t X20 = 0;
217
+        uint32_t X21 = 0;
218
+        uint32_t X22 = 0;
219
+        uint32_t X23 = 0;
220
+        uint32_t X24 = 0;
221
+        uint32_t X25 = 0;
222
+        uint32_t X26 = 0;
223
+        uint32_t X27 = 0;
224
+        uint32_t X28 = 0;
225
+        uint32_t X29 = 0;
226
+        uint32_t X30 = 0;
227
+        uint32_t X31 = 0;
228
+        uint32_t PC = 0;
229
+        uint64_t F0 = 0;
230
+        uint64_t F1 = 0;
231
+        uint64_t F2 = 0;
232
+        uint64_t F3 = 0;
233
+        uint64_t F4 = 0;
234
+        uint64_t F5 = 0;
235
+        uint64_t F6 = 0;
236
+        uint64_t F7 = 0;
237
+        uint64_t F8 = 0;
238
+        uint64_t F9 = 0;
239
+        uint64_t F10 = 0;
240
+        uint64_t F11 = 0;
241
+        uint64_t F12 = 0;
242
+        uint64_t F13 = 0;
243
+        uint64_t F14 = 0;
244
+        uint64_t F15 = 0;
245
+        uint64_t F16 = 0;
246
+        uint64_t F17 = 0;
247
+        uint64_t F18 = 0;
248
+        uint64_t F19 = 0;
249
+        uint64_t F20 = 0;
250
+        uint64_t F21 = 0;
251
+        uint64_t F22 = 0;
252
+        uint64_t F23 = 0;
253
+        uint64_t F24 = 0;
254
+        uint64_t F25 = 0;
255
+        uint64_t F26 = 0;
256
+        uint64_t F27 = 0;
257
+        uint64_t F28 = 0;
258
+        uint64_t F29 = 0;
259
+        uint64_t F30 = 0;
260
+        uint64_t F31 = 0;
261
+        uint32_t FCSR = 0;
262
+        uint32_t NEXT_PC = 0;
263
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0;
264
+        uint64_t icount = 0;
265
+    } reg;
266
+
267
+    std::array<address_type, 4> addr_mode;
268
+    
269
+
270
+	uint32_t get_fcsr(){return reg.FCSR;}
271
+	void set_fcsr(uint32_t val){reg.FCSR = val;}		
272
+
273
+};
274
+
275
+}
276
+}            
277
+#endif /* _RV32GC_H_ */

+ 7
- 2
riscv/incl/iss/arch/rv32imac.h View File

@@ -48,7 +48,9 @@ struct traits<rv32imac> {
48 48
 
49 49
 	constexpr static char const* const core_type = "RV32IMAC";
50 50
     
51
-    enum constants {XLEN=32, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095};
51
+    enum constants {XLEN=32, PCLEN=32, MISA_VAL=1075056901, PGSIZE=4096, PGMASK=4095};
52
+
53
+    constexpr static unsigned FP_REGS_SIZE = 0;
52 54
 
53 55
     enum reg_e {
54 56
         X0,
@@ -117,7 +119,6 @@ struct traits<rv32imac> {
117 119
     enum sreg_flag_e {FLAGS};
118 120
 
119 121
     enum mem_type_e {MEM, CSR, FENCE, RES};
120
-
121 122
 };
122 123
 
123 124
 struct rv32imac: public arch_if {
@@ -198,6 +199,10 @@ protected:
198 199
     } reg;
199 200
 
200 201
     std::array<address_type, 4> addr_mode;
202
+    
203
+
204
+	uint32_t get_fcsr(){return 0;}
205
+	void set_fcsr(uint32_t val){}
201 206
 
202 207
 };
203 208
 

+ 7
- 2
riscv/incl/iss/arch/rv64ia.h View File

@@ -48,7 +48,9 @@ struct traits<rv64ia> {
48 48
 
49 49
 	constexpr static char const* const core_type = "RV64IA";
50 50
     
51
-    enum constants {XLEN=64, XLEN2=128, XLEN_BIT_MASK=63, PCLEN=64, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095};
51
+    enum constants {XLEN=64, PCLEN=64, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095};
52
+
53
+    constexpr static unsigned FP_REGS_SIZE = 0;
52 54
 
53 55
     enum reg_e {
54 56
         X0,
@@ -117,7 +119,6 @@ struct traits<rv64ia> {
117 119
     enum sreg_flag_e {FLAGS};
118 120
 
119 121
     enum mem_type_e {MEM, CSR, FENCE, RES};
120
-
121 122
 };
122 123
 
123 124
 struct rv64ia: public arch_if {
@@ -198,6 +199,10 @@ protected:
198 199
     } reg;
199 200
 
200 201
     std::array<address_type, 4> addr_mode;
202
+    
203
+
204
+	uint32_t get_fcsr(){return 0;}
205
+	void set_fcsr(uint32_t val){}
201 206
 
202 207
 };
203 208
 

+ 5
- 4
riscv/src/CMakeLists.txt View File

@@ -1,11 +1,11 @@
1 1
 # library files
2 2
 FILE(GLOB RiscVHeaders *.h)
3
+FILE(GLOB IssSources iss/*.cpp internal/*.cpp) 
4
+
5
+
3 6
 set(LIB_HEADERS ${RiscVHeaders} )
4 7
 set(LIB_SOURCES
5
-    iss/rv32imac.cpp
6
-    iss/rv64ia.cpp
7
-    internal/vm_rv32imac.cpp
8
-    internal/vm_rv64ia.cpp
8
+    ${IssSources}
9 9
     plugin/instruction_count.cpp
10 10
     plugin/cycle_estimate.cpp
11 11
 )
@@ -35,6 +35,7 @@ add_executable(${APPLICATION_NAME} ${APP_SOURCES})
35 35
 # Links the target exe against the libraries
36 36
 target_link_libraries(${APPLICATION_NAME} ${LIBRARY_NAME})
37 37
 target_link_libraries(${APPLICATION_NAME} dbt-core)
38
+target_link_libraries(${APPLICATION_NAME} softfloat)
38 39
 target_link_libraries(${APPLICATION_NAME} sc-components)
39 40
 target_link_libraries(${APPLICATION_NAME} external)
40 41
 target_link_libraries(${APPLICATION_NAME} ${llvm_libs})

+ 458
- 0
riscv/src/internal/fp_functions.cpp View File

@@ -0,0 +1,458 @@
1
+////////////////////////////////////////////////////////////////////////////////
2
+// Copyright (C) 2017, MINRES Technologies GmbH
3
+// All rights reserved.
4
+//
5
+// Redistribution and use in source and binary forms, with or without
6
+// modification, are permitted provided that the following conditions are met:
7
+//
8
+// 1. Redistributions of source code must retain the above copyright notice,
9
+//    this list of conditions and the following disclaimer.
10
+//
11
+// 2. Redistributions in binary form must reproduce the above copyright notice,
12
+//    this list of conditions and the following disclaimer in the documentation
13
+//    and/or other materials provided with the distribution.
14
+//
15
+// 3. Neither the name of the copyright holder nor the names of its contributors
16
+//    may be used to endorse or promote products derived from this software
17
+//    without specific prior written permission.
18
+//
19
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+// POSSIBILITY OF SUCH DAMAGE.
30
+//
31
+// Contributors:
32
+//       eyck@minres.com - initial API and implementation
33
+////////////////////////////////////////////////////////////////////////////////
34
+
35
+#include <iss/iss.h>
36
+#include <iss/vm_base.h>
37
+
38
+extern "C" {
39
+#include <softfloat.h>
40
+#include "internals.h"
41
+#include "specialize.h"
42
+}
43
+
44
+#include <limits>
45
+
46
+namespace iss {
47
+namespace vm {
48
+namespace fp_impl {
49
+
50
+using namespace std;
51
+
52
+#define INT_TYPE(L)   Type::getIntNTy(mod->getContext(), L)
53
+#define FLOAT_TYPE    Type::getFloatTy(mod->getContext())
54
+#define DOUBLE_TYPE   Type::getDoubleTy(mod->getContext())
55
+#define VOID_TYPE     Type::getVoidTy(mod->getContext())
56
+#define THIS_PTR_TYPE Type::getIntNPtrTy(mod->getContext(), 8)
57
+#define FDECLL(NAME, RET, ...)                                                                                         \
58
+    Function *NAME##_func = CurrentModule->getFunction(#NAME);                                                         \
59
+    if (!NAME##_func) {                                                                                                \
60
+        std::vector<Type *> NAME##_args{__VA_ARGS__};                                                                  \
61
+        FunctionType *NAME##_type = FunctionType::get(RET, NAME##_args, false);                                        \
62
+        NAME##_func = Function::Create(NAME##_type, GlobalValue::ExternalLinkage, #NAME, CurrentModule);               \
63
+        NAME##_func->setCallingConv(CallingConv::C);                                                                   \
64
+    }
65
+
66
+#define FDECL(NAME, RET, ...)                                                                                          \
67
+    std::vector<Type *> NAME##_args{__VA_ARGS__};                                                                      \
68
+    FunctionType *NAME##_type = llvm::FunctionType::get(RET, NAME##_args, false);                                      \
69
+    mod->getOrInsertFunction(#NAME, NAME##_type);
70
+
71
+using namespace llvm;
72
+
73
+void add_fp_functions_2_module(Module *mod, uint32_t flen) {
74
+    if(flen){
75
+        FDECL(fget_flags, INT_TYPE(32));
76
+        FDECL(fadd_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
77
+        FDECL(fsub_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
78
+        FDECL(fmul_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
79
+        FDECL(fdiv_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
80
+        FDECL(fsqrt_s,    INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
81
+        FDECL(fcmp_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
82
+        FDECL(fcvt_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
83
+        FDECL(fmadd_s,    INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
84
+        FDECL(fsel_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
85
+        FDECL(fclass_s,   INT_TYPE(32), INT_TYPE(32));
86
+        if(flen>32){
87
+            FDECL(fconv_d2f,  INT_TYPE(32), INT_TYPE(64), INT_TYPE(8));
88
+            FDECL(fconv_f2d,  INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
89
+            FDECL(fadd_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
90
+            FDECL(fsub_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
91
+            FDECL(fmul_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
92
+            FDECL(fdiv_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
93
+            FDECL(fsqrt_d,    INT_TYPE(64), INT_TYPE(64), INT_TYPE(8));
94
+            FDECL(fcmp_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
95
+            FDECL(fcvt_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
96
+            FDECL(fmadd_d,    INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32), INT_TYPE(8));
97
+            FDECL(fsel_d,     INT_TYPE(64), INT_TYPE(64), INT_TYPE(64), INT_TYPE(32));
98
+            FDECL(fclass_d,   INT_TYPE(64), INT_TYPE(64));
99
+        }
100
+    }
101
+}
102
+
103
+}
104
+}
105
+}
106
+
107
+using this_t = uint8_t *;
108
+const uint8_t rmm_map[] = {
109
+        softfloat_round_near_even /*RNE*/,
110
+        softfloat_round_minMag/*RTZ*/,
111
+        softfloat_round_min/*RDN*/,
112
+        softfloat_round_max/*RUP?*/,
113
+        softfloat_round_near_maxMag /*RMM*/,
114
+        softfloat_round_max/*RTZ*/,
115
+        softfloat_round_max/*RTZ*/,
116
+        softfloat_round_max/*RTZ*/,
117
+};
118
+
119
+const uint32_t quiet_nan32=0x7fC00000;
120
+
121
+extern "C" {
122
+
123
+uint32_t fget_flags(){
124
+    return softfloat_exceptionFlags&0x1f;
125
+}
126
+
127
+uint32_t fadd_s(uint32_t v1, uint32_t v2, uint8_t mode) {
128
+    float32_t v1f{v1},v2f{v2};
129
+    softfloat_roundingMode=rmm_map[mode&0x7];
130
+    softfloat_exceptionFlags=0;
131
+    float32_t r =f32_add(v1f, v2f);
132
+    return r.v;
133
+}
134
+
135
+uint32_t fsub_s(uint32_t v1, uint32_t v2, uint8_t mode) {
136
+    float32_t v1f{v1},v2f{v2};
137
+    softfloat_roundingMode=rmm_map[mode&0x7];
138
+    softfloat_exceptionFlags=0;
139
+    float32_t r=f32_sub(v1f, v2f);
140
+    return r.v;
141
+}
142
+
143
+uint32_t fmul_s(uint32_t v1, uint32_t v2, uint8_t mode) {
144
+    float32_t v1f{v1},v2f{v2};
145
+    softfloat_roundingMode=rmm_map[mode&0x7];
146
+    softfloat_exceptionFlags=0;
147
+    float32_t r=f32_mul(v1f, v2f);
148
+    return r.v;
149
+}
150
+
151
+uint32_t fdiv_s(uint32_t v1, uint32_t v2, uint8_t mode) {
152
+    float32_t v1f{v1},v2f{v2};
153
+    softfloat_roundingMode=rmm_map[mode&0x7];
154
+    softfloat_exceptionFlags=0;
155
+    float32_t r=f32_div(v1f, v2f);
156
+    return r.v;
157
+}
158
+
159
+uint32_t fsqrt_s(uint32_t v1, uint8_t mode) {
160
+    float32_t v1f{v1};
161
+    softfloat_roundingMode=rmm_map[mode&0x7];
162
+    softfloat_exceptionFlags=0;
163
+    float32_t r=f32_sqrt(v1f);
164
+    return r.v;
165
+}
166
+
167
+uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) {
168
+    float32_t v1f{v1},v2f{v2};
169
+    softfloat_exceptionFlags=0;
170
+    bool nan = (v1&defaultNaNF32UI)==quiet_nan32 || (v2&defaultNaNF32UI)==quiet_nan32;
171
+    bool snan = softfloat_isSigNaNF32UI(v1) || softfloat_isSigNaNF32UI(v2);
172
+    switch(op){
173
+    case 0:
174
+        if(nan | snan){
175
+            if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
176
+            return 0;
177
+        } else
178
+            return f32_eq(v1f,v2f )?1:0;
179
+    case 1:
180
+        if(nan | snan){
181
+            softfloat_raiseFlags(softfloat_flag_invalid);
182
+            return 0;
183
+        } else
184
+            return f32_le(v1f,v2f )?1:0;
185
+    case 2:
186
+        if(nan | snan){
187
+            softfloat_raiseFlags(softfloat_flag_invalid);
188
+            return 0;
189
+        } else
190
+            return f32_lt(v1f,v2f )?1:0;
191
+    default:
192
+        break;
193
+    }
194
+    return -1;
195
+}
196
+
197
+uint32_t fcvt_s(uint32_t v1, uint32_t op, uint8_t mode) {
198
+    float32_t v1f{v1};
199
+    softfloat_exceptionFlags=0;
200
+    float32_t r;
201
+    int32_t res;
202
+    switch(op){
203
+    case 0: //w->s, fp to int32
204
+        res = f32_to_i32(v1f,rmm_map[mode&0x7],true);
205
+        return (uint32_t)res;
206
+    case 1: //wu->s
207
+        return f32_to_ui32(v1f,rmm_map[mode&0x7],true);
208
+    case 2: //s->w
209
+        r=i32_to_f32(v1);
210
+        return r.v;
211
+    case 3: //s->wu
212
+        r=ui32_to_f32(v1);
213
+        return r.v;
214
+    }
215
+    return 0;
216
+}
217
+
218
+uint32_t fmadd_s(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode) {
219
+    // op should be {softfloat_mulAdd_subProd(2), softfloat_mulAdd_subC(1)}
220
+    softfloat_roundingMode=rmm_map[mode&0x7];
221
+    softfloat_exceptionFlags=0;
222
+    float32_t res = softfloat_mulAddF32(v1, v2, v3, op&0x1);
223
+    if(op>1) res.v ^= 1ULL<<31;
224
+    return res.v;
225
+}
226
+
227
+uint32_t fsel_s(uint32_t v1, uint32_t v2, uint32_t op) {
228
+    softfloat_exceptionFlags = 0;
229
+    bool v1_nan = (v1 & defaultNaNF32UI) == defaultNaNF32UI;
230
+    bool v2_nan = (v2 & defaultNaNF32UI) == defaultNaNF32UI;
231
+    bool v1_snan = softfloat_isSigNaNF32UI(v1);
232
+    bool v2_snan = softfloat_isSigNaNF32UI(v2);
233
+    if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
234
+    if (v1_nan || v1_snan)
235
+        return (v2_nan || v2_snan) ? defaultNaNF32UI : v2;
236
+    else
237
+        if (v2_nan || v2_snan)
238
+            return v1;
239
+        else {
240
+            if ((v1 & 0x7fffffff) == 0 && (v2 & 0x7fffffff) == 0) {
241
+                return op == 0 ? ((v1 & 0x80000000) ? v1 : v2) : ((v1 & 0x80000000) ? v2 : v1);
242
+            } else {
243
+                float32_t v1f{ v1 }, v2f{ v2 };
244
+                return op == 0 ? (f32_lt(v1f, v2f) ? v1 : v2) : (f32_lt(v1f, v2f) ? v2 : v1);
245
+            }
246
+        }
247
+}
248
+
249
+uint32_t fclass_s( uint32_t v1 ){
250
+
251
+    float32_t a{v1};
252
+    union ui32_f32 uA;
253
+    uint_fast32_t uiA;
254
+
255
+    uA.f = a;
256
+    uiA = uA.ui;
257
+
258
+    uint_fast16_t infOrNaN = expF32UI( uiA ) == 0xFF;
259
+    uint_fast16_t subnormalOrZero = expF32UI( uiA ) == 0;
260
+    bool sign = signF32UI( uiA );
261
+    bool fracZero = fracF32UI( uiA ) == 0;
262
+    bool isNaN = isNaNF32UI( uiA );
263
+    bool isSNaN = softfloat_isSigNaNF32UI( uiA );
264
+
265
+    return
266
+        (  sign && infOrNaN && fracZero )          << 0 |
267
+        (  sign && !infOrNaN && !subnormalOrZero ) << 1 |
268
+        (  sign && subnormalOrZero && !fracZero )  << 2 |
269
+        (  sign && subnormalOrZero && fracZero )   << 3 |
270
+        ( !sign && infOrNaN && fracZero )          << 7 |
271
+        ( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
272
+        ( !sign && subnormalOrZero && !fracZero )  << 5 |
273
+        ( !sign && subnormalOrZero && fracZero )   << 4 |
274
+        ( isNaN &&  isSNaN )                       << 8 |
275
+        ( isNaN && !isSNaN )                       << 9;
276
+}
277
+
278
+uint32_t fconv_d2f(uint64_t v1, uint8_t mode){
279
+    softfloat_roundingMode=rmm_map[mode&0x7];
280
+    bool nan = (v1 & defaultNaNF64UI)==defaultNaNF64UI;
281
+    if(nan){
282
+        return defaultNaNF32UI;
283
+    } else {
284
+        float32_t res = f64_to_f32(float64_t{v1});
285
+        return res.v;
286
+    }
287
+}
288
+
289
+uint64_t fconv_f2d(uint32_t v1, uint8_t mode){
290
+    bool nan = (v1 & defaultNaNF32UI)==defaultNaNF32UI;
291
+    if(nan){
292
+        return defaultNaNF64UI;
293
+    } else {
294
+        softfloat_roundingMode=rmm_map[mode&0x7];
295
+        float64_t res = f32_to_f64(float32_t{v1});
296
+        return res.v;
297
+    }
298
+}
299
+
300
+uint64_t fadd_d(uint64_t v1, uint64_t v2, uint8_t mode) {
301
+    bool nan = (v1&defaultNaNF32UI)==quiet_nan32;
302
+    bool snan = softfloat_isSigNaNF32UI(v1);
303
+   float64_t v1f{v1},v2f{v2};
304
+    softfloat_roundingMode=rmm_map[mode&0x7];
305
+    softfloat_exceptionFlags=0;
306
+    float64_t r =f64_add(v1f, v2f);
307
+    return r.v;
308
+}
309
+
310
+uint64_t fsub_d(uint64_t v1, uint64_t v2, uint8_t mode) {
311
+    float64_t v1f{v1},v2f{v2};
312
+    softfloat_roundingMode=rmm_map[mode&0x7];
313
+    softfloat_exceptionFlags=0;
314
+    float64_t r=f64_sub(v1f, v2f);
315
+    return r.v;
316
+}
317
+
318
+uint64_t fmul_d(uint64_t v1, uint64_t v2, uint8_t mode) {
319
+    float64_t v1f{v1},v2f{v2};
320
+    softfloat_roundingMode=rmm_map[mode&0x7];
321
+    softfloat_exceptionFlags=0;
322
+    float64_t r=f64_mul(v1f, v2f);
323
+    return r.v;
324
+}
325
+
326
+uint64_t fdiv_d(uint64_t v1, uint64_t v2, uint8_t mode) {
327
+    float64_t v1f{v1},v2f{v2};
328
+    softfloat_roundingMode=rmm_map[mode&0x7];
329
+    softfloat_exceptionFlags=0;
330
+    float64_t r=f64_div(v1f, v2f);
331
+    return r.v;
332
+}
333
+
334
+uint64_t fsqrt_d(uint64_t v1, uint8_t mode) {
335
+    float64_t v1f{v1};
336
+    softfloat_roundingMode=rmm_map[mode&0x7];
337
+    softfloat_exceptionFlags=0;
338
+    float64_t r=f64_sqrt(v1f);
339
+    return r.v;
340
+}
341
+
342
+uint64_t fcmp_d(uint64_t v1, uint64_t v2, uint32_t op) {
343
+    float64_t v1f{v1},v2f{v2};
344
+    softfloat_exceptionFlags=0;
345
+    bool nan = (v1&defaultNaNF64UI)==quiet_nan32 || (v2&defaultNaNF64UI)==quiet_nan32;
346
+    bool snan = softfloat_isSigNaNF64UI(v1) || softfloat_isSigNaNF64UI(v2);
347
+    switch(op){
348
+    case 0:
349
+        if(nan | snan){
350
+            if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
351
+            return 0;
352
+        } else
353
+            return f64_eq(v1f,v2f )?1:0;
354
+    case 1:
355
+        if(nan | snan){
356
+            softfloat_raiseFlags(softfloat_flag_invalid);
357
+            return 0;
358
+        } else
359
+            return f64_le(v1f,v2f )?1:0;
360
+    case 2:
361
+        if(nan | snan){
362
+            softfloat_raiseFlags(softfloat_flag_invalid);
363
+            return 0;
364
+        } else
365
+            return f64_lt(v1f,v2f )?1:0;
366
+    default:
367
+        break;
368
+    }
369
+    return -1;
370
+}
371
+
372
+uint64_t fcvt_d(uint64_t v1, uint32_t op, uint8_t mode) {
373
+    float64_t v1f{v1};
374
+    softfloat_exceptionFlags=0;
375
+    float64_t r;
376
+    int32_t res;
377
+    switch(op){
378
+    case 0: //w->s, fp to int32
379
+        res = f64_to_i64(v1f,rmm_map[mode&0x7],true);
380
+        return (uint64_t)res;
381
+    case 1: //wu->s
382
+        return f64_to_ui64(v1f,rmm_map[mode&0x7],true);
383
+    case 2: //s->w
384
+        r=i64_to_f64(v1);
385
+        return r.v;
386
+    case 3: //s->wu
387
+        r=ui64_to_f64(v1);
388
+        return r.v;
389
+    }
390
+    return 0;
391
+}
392
+
393
+uint64_t fmadd_d(uint64_t v1, uint64_t v2, uint64_t v3, uint32_t op, uint8_t mode) {
394
+    // op should be {softfloat_mulAdd_subProd(2), softfloat_mulAdd_subC(1)}
395
+    softfloat_roundingMode=rmm_map[mode&0x7];
396
+    softfloat_exceptionFlags=0;
397
+    float64_t res = softfloat_mulAddF64(v1, v2, v3, op&0x1);
398
+    if(op>1) res.v ^= 1ULL<<63;
399
+    return res.v;
400
+}
401
+
402
+uint64_t fsel_d(uint64_t v1, uint64_t v2, uint32_t op) {
403
+    softfloat_exceptionFlags = 0;
404
+    bool v1_nan = (v1 & defaultNaNF64UI) == defaultNaNF64UI;
405
+    bool v2_nan = (v2 & defaultNaNF64UI) == defaultNaNF64UI;
406
+    bool v1_snan = softfloat_isSigNaNF64UI(v1);
407
+    bool v2_snan = softfloat_isSigNaNF64UI(v2);
408
+    if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
409
+    if (v1_nan || v1_snan)
410
+        return (v2_nan || v2_snan) ? defaultNaNF64UI : v2;
411
+    else
412
+        if (v2_nan || v2_snan)
413
+            return v1;
414
+        else {
415
+            if ((v1 & std::numeric_limits<int64_t>::max()) == 0 && (v2 & std::numeric_limits<int64_t>::max()) == 0) {
416
+                return op == 0 ?
417
+                        ((v1 & std::numeric_limits<int64_t>::min()) ? v1 : v2) :
418
+                        ((v1 & std::numeric_limits<int64_t>::min()) ? v2 : v1);
419
+            } else {
420
+                float64_t v1f{ v1 }, v2f{ v2 };
421
+                return op == 0 ?
422
+                        (f64_lt(v1f, v2f) ? v1 : v2) :
423
+                        (f64_lt(v1f, v2f) ? v2 : v1);
424
+            }
425
+        }
426
+}
427
+
428
+uint64_t fclass_d(uint64_t v1  ){
429
+
430
+    float64_t a{v1};
431
+    union ui64_f64 uA;
432
+    uint_fast64_t uiA;
433
+
434
+    uA.f = a;
435
+    uiA = uA.ui;
436
+
437
+    uint_fast16_t infOrNaN = expF64UI( uiA ) == 0x7FF;
438
+    uint_fast16_t subnormalOrZero = expF64UI( uiA ) == 0;
439
+    bool sign = signF64UI( uiA );
440
+    bool fracZero = fracF64UI( uiA ) == 0;
441
+    bool isNaN = isNaNF64UI( uiA );
442
+    bool isSNaN = softfloat_isSigNaNF64UI( uiA );
443
+
444
+    return
445
+        (  sign && infOrNaN && fracZero )          << 0 |
446
+        (  sign && !infOrNaN && !subnormalOrZero ) << 1 |
447
+        (  sign && subnormalOrZero && !fracZero )  << 2 |
448
+        (  sign && subnormalOrZero && fracZero )   << 3 |
449
+        ( !sign && infOrNaN && fracZero )          << 7 |
450
+        ( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
451
+        ( !sign && subnormalOrZero && !fracZero )  << 5 |
452
+        ( !sign && subnormalOrZero && fracZero )   << 4 |
453
+        ( isNaN &&  isSNaN )                       << 8 |
454
+        ( isNaN && !isSNaN )                       << 9;
455
+}
456
+
457
+}
458
+

+ 8415
- 0
riscv/src/internal/vm_rv32gc.cpp
File diff suppressed because it is too large
View File


+ 379
- 245
riscv/src/internal/vm_rv32imac.cpp
File diff suppressed because it is too large
View File


+ 229
- 215
riscv/src/internal/vm_rv64ia.cpp
File diff suppressed because it is too large
View File


+ 74
- 0
riscv/src/iss/rv32gc.cpp View File

@@ -0,0 +1,74 @@
1
+////////////////////////////////////////////////////////////////////////////////
2
+// Copyright (C) 2017, MINRES Technologies GmbH
3
+// All rights reserved.
4
+// 
5
+// Redistribution and use in source and binary forms, with or without
6
+// modification, are permitted provided that the following conditions are met:
7
+// 
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+// 1. Redistributions of source code must retain the above copyright notice,
9
+//    this list of conditions and the following disclaimer.
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+// 
11
+// 2. Redistributions in binary form must reproduce the above copyright notice,
12
+//    this list of conditions and the following disclaimer in the documentation
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+//    and/or other materials provided with the distribution.
14
+// 
15
+// 3. Neither the name of the copyright holder nor the names of its contributors
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+//    may be used to endorse or promote products derived from this software
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+//    without specific prior written permission.
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+// 
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+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+// POSSIBILITY OF SUCH DAMAGE.
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+//
31
+////////////////////////////////////////////////////////////////////////////////
32
+
33
+#include "util/ities.h"
34
+#include <util/logging.h>
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+
36
+#include <elfio/elfio.hpp>
37
+#include <iss/arch/rv32gc.h>
38
+
39
+#ifdef __cplusplus
40
+extern "C" {
41
+#endif
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+#include <ihex.h>
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+#ifdef __cplusplus
44
+}
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+#endif
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+#include <fstream>
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+#include <cstdio>
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+#include <cstring>
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+
50
+using namespace iss::arch;
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+
52
+rv32gc::rv32gc() {
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+    reg.icount=0;
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+}
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+
56
+rv32gc::~rv32gc(){
57
+}
58
+
59
+void rv32gc::reset(uint64_t address) {
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+    for(size_t i=0; i<traits<rv32gc>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32gc>::reg_t),0));
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+    reg.PC=address;
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+    reg.NEXT_PC=reg.PC;
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+    reg.trap_state=0;
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+    reg.machine_state=0x0;
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+}
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+
67
+uint8_t* rv32gc::get_regs_base_ptr(){
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+    return reinterpret_cast<uint8_t*>(&reg);
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+}
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+
71
+rv32gc::phys_addr_t rv32gc::virt2phys(const iss::addr_t &pc) {
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+    return phys_addr_t(pc); // change logical address to physical address
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+}
74
+

+ 48
- 12
riscv/src/main.cpp View File

@@ -39,6 +39,7 @@
39 39
 #include <boost/program_options.hpp>
40 40
 #include <iss/arch/riscv_hart_msu_vp.h>
41 41
 #include <iss/arch/rv32imac.h>
42
+#include <iss/arch/rv32gc.h>
42 43
 #include <iss/arch/rv64ia.h>
43 44
 #include <iss/jit/MCJIThelper.h>
44 45
 #include <iss/log_categories.h>
@@ -65,7 +66,8 @@ int main(int argc, char *argv[]) {
65 66
         ("dump-ir", "dump the intermediate representation")
66 67
         ("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
67 68
         ("mem,m", po::value<std::string>(), "the memory input file")
68
-        ("isa", po::value<std::string>()->default_value("rv32imac"), "isa to use for simulation");
69
+        ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
70
+        ("isa", po::value<std::string>()->default_value("rv32gc"), "isa to use for simulation");
69 71
     // clang-format on
70 72
     auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
71 73
     try {
@@ -96,26 +98,55 @@ int main(int argc, char *argv[]) {
96 98
         LOG_OUTPUT(connection)::stream() = f;
97 99
     }
98 100
 
101
+    std::vector<iss::vm_plugin*> plugin_list;
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+    auto res=0;
99 103
     try {
100 104
         // application code comes here //
101 105
         iss::init_jit(argc, argv);
102 106
         bool dump = clim.count("dump-ir");
103 107
         // instantiate the simulator
104 108
         std::unique_ptr<iss::vm_if> vm{nullptr};
109
+        std::unique_ptr<iss::arch_if> cpu{nullptr};
105 110
         std::string isa_opt(clim["isa"].as<std::string>());
106
-        iss::plugin::instruction_count ic_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
107
-        iss::plugin::cycle_estimate ce_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
108
-        if (isa_opt.substr(0, 4)=="rv64") {
109
-            iss::arch::rv64ia* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64ia>();
110
-            vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
111
-        } else if (isa_opt.substr(0, 4)=="rv32") {
112
-            iss::arch::rv32imac* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>();
113
-            vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
114
-            //vm->register_plugin(ce_plugin);
111
+        if (isa_opt=="rv64ia") {
112
+            iss::arch::rv64ia* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64ia>();
113
+            vm = iss::create(lcpu, clim["gdb-port"].as<unsigned>());
114
+            cpu.reset(lcpu);
115
+        } else if (isa_opt=="rv32imac") {
116
+            iss::arch::rv32imac* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>();
117
+            vm = iss::create(lcpu, clim["gdb-port"].as<unsigned>());
118
+            cpu.reset(lcpu);
119
+        } else if (isa_opt=="rv32gc") {
120
+            iss::arch::rv32gc* lcpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32gc>();
121
+            vm = iss::create(lcpu, clim["gdb-port"].as<unsigned>());
122
+            cpu.reset(lcpu);
115 123
         } else {
116 124
             LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
117 125
             return 127;
118 126
         }
127
+        if (clim.count("plugin")) {
128
+           for (std::string opt_val : clim["plugin"].as<std::vector<std::string>>()){
129
+               auto plugin_name{opt_val};
130
+               std::string filename{"cycles.txt"};
131
+               std::size_t found = opt_val.find('=');
132
+               if (found!=std::string::npos){
133
+                   plugin_name=opt_val.substr(0, found);
134
+                   filename=opt_val.substr(found+1, opt_val.size());
135
+               }
136
+                if(plugin_name=="ic"){
137
+                    auto* ic_plugin= new iss::plugin::instruction_count(filename);
138
+                    vm->register_plugin(*ic_plugin);
139
+                    plugin_list.push_back(ic_plugin);
140
+                } else if(plugin_name=="ce"){
141
+                    auto* ce_plugin= new iss::plugin::cycle_estimate(filename);
142
+                    vm->register_plugin(*ce_plugin);
143
+                    plugin_list.push_back(ce_plugin);
144
+                } else {
145
+                    LOG(ERROR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'"<<std::endl;
146
+                    return 127;
147
+                }
148
+            }
149
+        }
119 150
         if (clim.count("disass")) {
120 151
             vm->setDisassEnabled(true);
121 152
             LOGGER(disass)::reporting_level() = logging::INFO;
@@ -146,9 +177,14 @@ int main(int argc, char *argv[]) {
146 177
         }
147 178
 		vm->reset(start_address);
148 179
         auto cycles = clim["instructions"].as<int64_t>();
149
-        return vm->start(cycles, dump);
180
+        res = vm->start(cycles, dump);
150 181
     } catch (std::exception &e) {
151 182
         LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl;
152
-        return 2;
183
+        res=2;
184
+    }
185
+    // cleanup to let plugins report of needed
186
+    for(auto* p:plugin_list){
187
+        delete p;
153 188
     }
189
+    return res;
154 190
 }

+ 5
- 5
riscv/src/plugin/cycle_estimate.cpp View File

@@ -63,7 +63,7 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
63 63
 	if(!arch_instr) return false;
64 64
 	const std::string  core_name = arch_instr->core_type_name();
65 65
     Json::Value &val = root[core_name];
66
-    if(val.isArray()){
66
+    if(!val.isNull() && val.isArray()){
67 67
     	delays.reserve(val.size());
68 68
     	for(auto it:val){
69 69
     		auto name = it["name"];
@@ -76,6 +76,8 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
76 76
 				delays.push_back(instr_desc{size.asUInt(), delay[0].asUInt(), delay[1].asUInt()});
77 77
     		}
78 78
     	}
79
+    } else {
80
+        LOG(ERROR)<<"plugin cycle_estimate: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
79 81
     }
80 82
 	return true;
81 83
 
@@ -85,8 +87,6 @@ void iss::plugin::cycle_estimate::callback(instr_info_t instr_info) {
85 87
     assert(arch_instr && "No instrumentation interface available but callback executed");
86 88
 	auto entry = delays[instr_info.instr_id];
87 89
 	bool taken = (arch_instr->get_next_pc()-arch_instr->get_pc()) != (entry.size/8);
88
-	if(taken && entry.taken > 1 ) // 1 is the default increment per instruction
89
-		arch_instr->set_curr_instr_cycles(entry.taken);
90
-	if(!taken && entry.not_taken > 1) // 1 is the default increment per instruction
91
-		arch_instr->set_curr_instr_cycles(entry.not_taken);
90
+    uint32_t delay = taken ? entry.taken : entry.not_taken;
91
+    if(delay>1) arch_instr->set_curr_instr_cycles(delay);
92 92
 }

+ 3
- 1
riscv/src/plugin/instruction_count.cpp View File

@@ -68,7 +68,7 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
68 68
     if(!instr_if) return false;
69 69
 	const std::string  core_name = instr_if->core_type_name();
70 70
     Json::Value &val = root[core_name];
71
-    if(val.isArray()){
71
+    if(!val.isNull() && val.isArray()){
72 72
     	delays.reserve(val.size());
73 73
     	for(auto it:val){
74 74
     		auto name = it["name"];
@@ -84,6 +84,8 @@ bool iss::plugin::instruction_count::registration(const char* const version, vm_
84 84
     		}
85 85
     	}
86 86
     	rep_counts.resize(delays.size());
87
+    } else {
88
+        LOG(ERROR)<<"plugin instruction_count: could not find an entry for "<<core_name<<" in JSON file"<<std::endl;
87 89
     }
88 90
 	return true;
89 91
 }

+ 1
- 1
sc-components

@@ -1 +1 @@
1
-Subproject commit b50df83ebfbf06299613a