Browse Source

Restructured project

pull/1/head
Eyck Jentzsch 3 years ago
parent
commit
9a617dab57
55 changed files with 16144 additions and 165 deletions
  1. +1
    -4
      .cproject
  2. +1
    -0
      CMakeLists.txt
  3. +1
    -1
      dbt-core
  4. +2
    -4
      external/CMakeLists.txt
  5. +95
    -0
      riscv.sc/CMakeLists.txt
  6. +0
    -0
      riscv.sc/gen_input/fe310.rdl
  7. +0
    -0
      riscv.sc/gen_input/gpio.rdl
  8. +2
    -2
      riscv.sc/gen_input/plic.rdl
  9. +174
    -0
      riscv.sc/gen_input/spi.rdl
  10. +81
    -0
      riscv.sc/gen_input/uart.rdl
  11. +171
    -0
      riscv.sc/incl/cli_options.h
  12. +1249
    -0
      riscv.sc/incl/iss/arch/riscv_hart_msu_vp.h
  13. +200
    -0
      riscv.sc/incl/iss/arch/rv32imac.h
  14. +200
    -0
      riscv.sc/incl/iss/arch/rv64ia.h
  15. +0
    -0
      riscv.sc/incl/sysc/SiFive/core_complex.h
  16. +0
    -0
      riscv.sc/incl/sysc/SiFive/gen/e300_plat_t.h
  17. +0
    -0
      riscv.sc/incl/sysc/SiFive/gen/gpio_regs.h
  18. +0
    -0
      riscv.sc/incl/sysc/SiFive/gen/plic_regs.h
  19. +0
    -0
      riscv.sc/incl/sysc/SiFive/gen/spi_regs.h
  20. +0
    -0
      riscv.sc/incl/sysc/SiFive/gen/uart_regs.h
  21. +0
    -0
      riscv.sc/incl/sysc/SiFive/gpio.h
  22. +0
    -0
      riscv.sc/incl/sysc/SiFive/platform.h
  23. +0
    -0
      riscv.sc/incl/sysc/SiFive/plic.h
  24. +0
    -0
      riscv.sc/incl/sysc/SiFive/spi.h
  25. +0
    -0
      riscv.sc/incl/sysc/SiFive/uart.h
  26. +62
    -0
      riscv.sc/src/CMakeLists.txt
  27. +695
    -0
      riscv.sc/src/internal/vm_riscv.in.cpp
  28. +4882
    -0
      riscv.sc/src/internal/vm_rv32imac.cpp
  29. +3884
    -0
      riscv.sc/src/internal/vm_rv64ia.cpp
  30. +76
    -0
      riscv.sc/src/iss/rv32imac.cpp
  31. +76
    -0
      riscv.sc/src/iss/rv64ia.cpp
  32. +0
    -0
      riscv.sc/src/sc_main.cpp
  33. +0
    -0
      riscv.sc/src/sysc/core_complex.cpp
  34. +0
    -0
      riscv.sc/src/sysc/gpio.cpp
  35. +0
    -0
      riscv.sc/src/sysc/platform.cpp
  36. +0
    -0
      riscv.sc/src/sysc/plic.cpp
  37. +0
    -0
      riscv.sc/src/sysc/spi.cpp
  38. +0
    -0
      riscv.sc/src/sysc/uart.cpp
  39. +0
    -0
      riscv/gen_input/RV32A.core_desc
  40. +0
    -0
      riscv/gen_input/RV32C.core_desc
  41. +0
    -0
      riscv/gen_input/RV32F.core_desc
  42. +0
    -0
      riscv/gen_input/RV32IBase.core_desc
  43. +0
    -0
      riscv/gen_input/RV32M.core_desc
  44. +0
    -0
      riscv/gen_input/RV64A.core_desc
  45. +0
    -0
      riscv/gen_input/RV64IBase.core_desc
  46. +0
    -0
      riscv/gen_input/RV64M.core_desc
  47. +0
    -0
      riscv/gen_input/minres_rv.core_desc
  48. +2
    -1
      riscv/incl/iss/arch/riscv_hart_msu_vp.h
  49. +1
    -1
      riscv/incl/iss/arch/rv32imac.h
  50. +200
    -0
      riscv/incl/iss/arch/rv64ia.h
  51. +3
    -14
      riscv/src/CMakeLists.txt
  52. +95
    -95
      riscv/src/internal/vm_rv32imac.cpp
  53. +3884
    -0
      riscv/src/internal/vm_rv64ia.cpp
  54. +76
    -0
      riscv/src/iss/rv64ia.cpp
  55. +31
    -43
      riscv/src/main.cpp

+ 1
- 4
.cproject View File

@ -151,11 +151,8 @@
</tool>
</toolChain>
</folderInfo>
<fileInfo id="cdt.managedbuild.config.gnu.exe.release.446935686.748801612" name="vm_riscv.in.cpp" rcbsApplicability="disable" resourcePath="riscv/src/internal/vm_riscv.in.cpp" toolsToInvoke="cdt.managedbuild.tool.gnu.cpp.compiler.exe.release.1265053613.1256835897">
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.exe.release.1265053613.1256835897" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.exe.release.1265053613"/>
</fileInfo>
<sourceEntries>
<entry excluding="riscv/src/internal/vm_riscv.in.cpp|riscv/src-gen|blink.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry excluding="riscv/src-gen|blink.S|riscv/src/internal/vm_riscv.in.cpp" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>

+ 1
- 0
CMakeLists.txt View File

@ -31,3 +31,4 @@ add_subdirectory(external)
add_subdirectory(dbt-core)
add_subdirectory(sc-components)
add_subdirectory(riscv)
add_subdirectory(riscv.sc)

+ 1
- 1
dbt-core

@ -1 +1 @@
Subproject commit df6f6eb713c3c0a2dc10ba29e80d586a9f66a25f
Subproject commit 1091afcc3045c1bea5508a6be785eed757632452

+ 2
- 4
external/CMakeLists.txt View File

@ -8,18 +8,16 @@ project("external")
include(Common)
include_directories( ${PROJECT_SOURCE_DIR}/external/libGIS ${PROJECT_SOURCE_DIR}/external/easyloggingpp/src )
include_directories( ${PROJECT_SOURCE_DIR}/external/libGIS )
FILE(GLOB ElfioHeaders elfio *.hpp)
FILE(GLOB GISHeaders libGis *.h)
FILE(GLOB LogHeaders easyloggingpp/src *.h)
set(LIB_HEADERS ${ElfioHeaders} ${GISHeaders} ${LogHeaders})
set(LIB_HEADERS ${ElfioHeaders} ${GISHeaders})
set(LIB_SOURCES
libGIS/atmel_generic.c
libGIS/ihex.c
libGIS/srecord.c
easyloggingpp/src/easylogging++.cc
)
# Define two variables in order not to repeat ourselves.

+ 95
- 0
riscv.sc/CMakeLists.txt View File

@ -0,0 +1,95 @@
cmake_minimum_required(VERSION 2.8)
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/../cmake) # main (top) cmake dir
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake) # project specific cmake dir
set(CMAKE_CXX_STANDARD 14) # tODO move up to a general cmake config for all sub projects ?
# CMake useful variables
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/bin")
set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib")
set(CMAKE_LIBRARY_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib")
# Set the name of your project here
project("riscv.sc")
# Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
set(VERSION_MAJOR "0")
set(VERSION_MINOR "0")
set(VERSION_PATCH "1")
set(VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH})
include(Common)
## Git (and its revision)
find_package(Git QUIET) # if we don't find git or FindGit.cmake is not on the system we ignore it.
## The Git module will trigger a reconfiguration for each pull that will bring a new revision on the local repository
set (VCS_REVISION "-1")
if(GIT_FOUND)
include(GetGitRevisionDescription)
get_git_head_revision(GIT_REFSPEC GIT_SHA1)
message(STATUS "GIT branch ${GIT_REFSPEC}")
message(STATUS "GIT revision ${GIT_SHA1}")
set (VCS_REVISION ${GIT_SHA1})
endif()
# This line finds the boost lib and headers.
set(Boost_NO_BOOST_CMAKE ON) # Don't do a find_package in config mode before searching for a regular boost install.
find_package(Boost COMPONENTS program_options system thread REQUIRED)
find_package(LLVM REQUIRED CONFIG)
message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
find_package(SystemC)
if(SystemC_FOUND)
add_definitions(-DWITH_SYSTEMC)
include_directories(${SystemC_INCLUDE_DIRS})
link_directories(${SystemC_LIBRARY_DIRS})
else(SystemC_FOUND)
message( FATAL_ERROR "SystemC library not found." )
endif(SystemC_FOUND)
if(SCV_FOUND)
add_definitions(-DWITH_SCV)
link_directories(${SCV_LIBRARY_DIRS})
endif(SCV_FOUND)
# This sets the include directory for the reference project. This is the -I flag in gcc.
include_directories(
${PROJECT_SOURCE_DIR}/incl
${LLVM_INCLUDE_DIRS}
)
add_dependent_subproject(dbt-core)
add_dependent_subproject(sc-components)
add_dependent_header(util)
include_directories(
${PROJECT_SOURCE_DIR}/incl
${PROJECT_SOURCE_DIR}/../external/elfio
${PROJECT_SOURCE_DIR}/../external/libGIS
${PROJECT_SOURCE_DIR}/../riscv
${Boost_INCLUDE_DIRS}
)
# Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
set(CMAKE_MACOSX_RPATH ON)
set(CMAKE_SKIP_BUILD_RPATH FALSE)
set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE)
set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib")
set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE)
add_subdirectory(src)
#
# SYSTEM PACKAGING (RPM, TGZ, ...)
# _____________________________________________________________________________
#include(CPackConfig)
#
# CMAKE PACKAGING (for other CMake projects to use this one easily)
# _____________________________________________________________________________
#include(PackageConfigurator)

riscv/fe310.rdl → riscv.sc/gen_input/fe310.rdl View File


riscv/gpio.rdl → riscv.sc/gen_input/gpio.rdl View File


riscv/plic.rdl → riscv.sc/gen_input/plic.rdl View File

@ -26,12 +26,12 @@ regfile plic_regs {
field {
name = "threshold";
} \threshold[2:0];
} \threshold @0x0C200000;
} \threshold @0x200000;
reg {
name="claim/complete";
desc="interrupt handling completed";
field {
name = "interrupt_claimed";
} interrupt_claimed[31:0];
} claim_complete @0x0C200004;
} claim_complete @0x200004;
};

+ 174
- 0
riscv.sc/gen_input/spi.rdl View File

@ -0,0 +1,174 @@
regfile spi_regs {
lsb0;
reg {
name="sckdiv";
desc="Serial clock divisor";
field {
name ="div";
} div[12];
} sckdiv @0x000;
reg {
name="sckmode";
desc="Serial clock mode";
field {
name="pha";
} pha[1];
field {
name="pol";
} pol[1];
} sckmode @0x004;
reg {
name="csid";
desc="Chip select ID";
field {
name="csid";
} csid[32];
} csid @0x010;
reg {
name="csdef";
desc="Chip select default";
field {
name="csdef";
} csdef[32];
} csdef @0x014;
reg {
name="csmode";
desc="Chip select mode";
field {
name="mode";
} mode[2];
} csmode @0x018;
reg {
name="delay0";
desc="Delay control 0";
field {
name="cssck";
} cssck[7:0];
field {
name ="sckcs";
} sckcs[23:16];
} delay0 @0x028;
reg {
name="delay1";
desc="Delay control 1";
field {
name="intercs";
}intercs[15:0];
field {
name="interxfr";
} interxfr[23:16];
} delay1 @0x02C;
reg {
name="fmt";
desc="Frame format";
field{
name ="proto";
}proto[2];
field {
name="endian";
} endian[1];
field {
name="dir";
} dir[1];
field {
name="len";
} len[19:16];
} fmt @0x040;
reg {
name="txdata";
desc="Tx FIFO data";
field {
name="data";
} data[8];
field {
name="full";
} full[31:31];
} txdata @0x048;
reg {
name="rxdata";
desc="Rx FIFO data";
field{
name="data";
} data[8];
field{
name="empty";
} empty[31:31];
} rxdata @0x04C;
reg {
name="txmark";
desc="Tx FIFO watermark";
field {
name="txmark";
} txmark[3];
} txmark @0x050;
reg {
name="rxmark";
desc="Rx FIFO watermark";
field {
name="rxmark";
} rxmark[3];
} rxmark @0x054;
reg {
name="fctrl";
desc="SPI flash interface control";
field {
name="en";
} en[1];
} fctrl @0x060;
reg {
name="ffmt";
desc="SPI flash instruction format";
field {
name="cmd_en";
reset=0x1;
} cmd_en[1];
field {
name="addr_len";
reset=0x3;
} addr_len[2];
field {
name="pad_cnt";
reset=0x0;
} pad_cnt[4];
field {
name="cmd_proto";
reset=0x0;
} cmd_proto[2];
field {
name="addr_proto";
reset=0x0;
} addr_proto[2];
field {
name="data_proto";
reset=0x0;
} data_proto[2];
field {
name="cmd_code";
reset=0x3;
} cmd_code[23:16];
field {
name="pad_code";
reset=0x0;
} pad_code[8];
} ffmt @0x064;
reg {
name="ie";
desc="SPI interrupt enable";
field{
name="txwm";
} txwm[1];
field{
name="rxwm";
} rxwm[1];
} ie @0x070;
reg {
name="ip";
desc="SPI interrupt pending";
field{
name="txwm";
} txwm[1];
field{
name="rxwm";
} rxwm[1];
} ip @0x074;
};

+ 81
- 0
riscv.sc/gen_input/uart.rdl View File

@ -0,0 +1,81 @@
regfile uart_regs {
lsb0;
reg {
name="txdata";
desc="Transmit data register";
field {
name ="data";
} data[7:0];
field {
name ="full";
} full[31:31];
} txdata @0x00;
reg {
name="rxdata";
desc="Receive data register";
field {
name ="data";
} data[7:0];
field {
name ="empty";
} empty[31:31];
}rxdata @0x04;
reg {
name="txctrl";
desc="Transmit control register";
field {
name ="txen";
} txen[1];
field {
name ="nstop";
} nstop[1];
field {
name ="reserved";
} reserved[14];
field {
name ="txcnt";
} txcnt[3];
}txctrl @0x08;
reg {
name="rxctrl";
desc="Receive control register";
field {
name ="rxen";
} rxen[1];
field {
name ="reserved";
} reserved[15];
field {
name ="rxcnt";
} rxcnt[3];
}rxctrl @0x0C;
reg {
name="ie";
desc="UART interrupt enable";
field{
name ="txwm";
} txwm[1];
field{
name ="rxwm";
} rxwm[1];
}ie @0x10;
reg {
name="ip";
desc="UART Interrupt pending";
field{
name ="txwm";
} txwm[1];
field{
name ="rxwm";
} rxwm[1];
} ip @0x14;
reg {
name="div";
desc="Baud rate divisor";
field{
name ="div";
} div[16];
} div @0x18;
};

+ 171
- 0
riscv.sc/incl/cli_options.h View File

@ -0,0 +1,171 @@
/*******************************************************************************
* Copyright (C) 2017, MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Contributors:
* eyck@minres.com - initial API and implementation
******************************************************************************/
#ifndef _CLI_OPTIONS_H_
#define _CLI_OPTIONS_H_
#include <boost/program_options.hpp>
#include <util/logging.h>
#include <iostream>
#include <cstdio>
namespace {
const size_t ERROR_IN_COMMAND_LINE = 1;
const size_t SUCCESS = 0;
const size_t ERROR_UNHANDLED_EXCEPTION = 2;
inline void enable_log_level(int level){
switch(level){
case 0:
logging::Logger::reporting_level()= logging::FATAL;
/* no break */
case 1:
logging::Logger::reporting_level()= logging::ERROR;
/* no break */
case 2:
logging::Logger::reporting_level()= logging::WARNING;
/* no break */
case 3:
logging::Logger::reporting_level()= logging::INFO;
/* no break */
case 4:
logging::Logger::reporting_level()= logging::DEBUG;
/* no break */
case 5:
logging::Logger::reporting_level()= logging::TRACE;
/* no break */
}
}
inline void configure_default_logger(boost::program_options::variables_map& vm){
// el::Configurations defaultConf;
// defaultConf.setToDefault();
// defaultConf.set(el::Level::Error, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
// defaultConf.set(el::Level::Warning, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
// defaultConf.set(el::Level::Info, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
// defaultConf.set(el::Level::Debug, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
// defaultConf.set(el::Level::Trace, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
if(vm.count("verbose"))
enable_log_level(vm["verbose"].as<int>());
if(vm.count("log-file"))
logging::Output2FILE::stream() = fopen(vm["log-file"].as<std::string>().c_str(), "w");
// default logger uses default configurations
// el::Loggers::reconfigureLogger("default", defaultConf);
}
inline void configure_debugger_logger() {
// configure the connection logger
// el::Logger* gdbServerLogger = el::Loggers::getLogger("connection");
// el::Configurations gdbServerConf;
// gdbServerConf.setToDefault();
// gdbServerConf.set(el::Level::Error, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Warning, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Info, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Debug, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Trace, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// enable_log_level(gdbServerConf, 5);
// gdbServerLogger->configure(gdbServerConf);
}
inline void configure_disass_logger(boost::program_options::variables_map& vm) {
// el::Logger* disassLogger = el::Loggers::getLogger("disass");
// el::Configurations disassConf;
// if(vm.count("disass")){
// auto file_name=vm["disass"].as<std::string>();
// disassConf.setToDefault();
// if (file_name.length() > 0) {
// disassConf.set(el::Level::Global, el::ConfigurationType::ToFile,
// std::string("true"));
// disassConf.set(el::Level::Global,
// el::ConfigurationType::ToStandardOutput, std::string("false"));
// disassConf.set(el::Level::Global, el::ConfigurationType::Format,
// std::string("%msg"));
// disassConf.set(el::Level::Global, el::ConfigurationType::Filename,
// file_name);
// std::ofstream str(file_name); // just to clear the file
// } else {
// disassConf.set(el::Level::Global, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} [%logger] %msg");
// }
// } else {
// enable_log_level(disassConf, 0);
// }
// disassLogger->configure(disassConf);
}
} // namespace
inline int parse_cli_options(boost::program_options::variables_map& vm, int argc, char *argv[]){
namespace po = boost::program_options;
po::options_description desc("Options");
desc.add_options()
("help,h", "Print help message")
("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
("vmodule", po::value<std::string>(),"Defines the module(s) to be logged")
("logging-flags", po::value<int>(),"Sets logging flag(s).")
("log-file", po::value<std::string>(),"Sets default log file.")
("disass,d", po::value<std::string>()->implicit_value(""),"Enables disassembly")
("elf,l", po::value< std::vector<std::string> >(), "ELF file(s) to load")
("gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use")
("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")
("dump-ir", "dump the intermediate representation")
("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run")
("systemc,s", "Run as SystemC simulation")
("time", po::value<int>(), "SystemC siimulation time in ms")
("reset,r", po::value<std::string>(), "reset address")
("trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")\
("mem,m", po::value<std::string>(), "the memory input file")
("rv64", "run RV64");
try {
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
// --help option
if ( vm.count("help") ){
std::cout << "DBT-RISE-RiscV" << std::endl << desc << std::endl;
return SUCCESS;
}
po::notify(vm); // throws on error, so do after help in case
} catch(po::error& e){
// there are problems
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl;
return ERROR_IN_COMMAND_LINE;
}
return SUCCESS;
}
#endif /* _CLI_OPTIONS_H_ */

+ 1249
- 0
riscv.sc/incl/iss/arch/riscv_hart_msu_vp.h
File diff suppressed because it is too large
View File


+ 200
- 0
riscv.sc/incl/iss/arch/rv32imac.h View File

@ -0,0 +1,200 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Thu Sep 21 17:01:54 CEST 2017
// * rv32imac.h Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _RV32IMAC_H_
#define _RV32IMAC_H_
#include <iss/arch_if.h>
#include <iss/vm_if.h>
#include <iss/arch/traits.h>
namespace iss {
namespace arch {
struct rv32imac;
template<>
struct traits<rv32imac> {
enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095};
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
ICOUNT
};
typedef uint32_t reg_t;
typedef uint32_t addr_t;
typedef uint32_t code_word_t; //TODO: check removal
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV32IMAC_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64};
return RV32IMAC_reg_size[r];
}
constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV32IMAC_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160};
return RV32IMAC_reg_byte_offset[r];
}
enum sreg_flag_e {FLAGS};
enum mem_type_e {MEM,CSR,FENCE,RES};
};
struct rv32imac: public arch_if {
using virt_addr_t = typename traits<rv32imac>::virt_addr_t;
using phys_addr_t = typename traits<rv32imac>::phys_addr_t;
using reg_t = typename traits<rv32imac>::reg_t;
using addr_t = typename traits<rv32imac>::addr_t;
rv32imac();
~rv32imac();
virtual void reset(uint64_t address=0) override;
virtual uint8_t* get_regs_base_ptr() override;
/// deprecated
virtual void get_reg(short idx, std::vector<uint8_t>& value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
virtual bool get_flag(int flag) override {return false;}
virtual void set_flag(int, bool value) override {};
/// deprecated
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
virtual void notify_phase(exec_phase phase){
if(phase==ISTART){
++reg.icount;
reg.PC=reg.NEXT_PC;
reg.trap_state=reg.pending_trap;
}
}
uint64_t get_icount() { return reg.icount;}
virtual phys_addr_t v2p(const iss::addr_t& pc);
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
protected:
struct RV32IMAC_regs {
uint32_t X0;
uint32_t X1;
uint32_t X2;
uint32_t X3;
uint32_t X4;
uint32_t X5;
uint32_t X6;
uint32_t X7;
uint32_t X8;
uint32_t X9;
uint32_t X10;
uint32_t X11;
uint32_t X12;
uint32_t X13;
uint32_t X14;
uint32_t X15;
uint32_t X16;
uint32_t X17;
uint32_t X18;
uint32_t X19;
uint32_t X20;
uint32_t X21;
uint32_t X22;
uint32_t X23;
uint32_t X24;
uint32_t X25;
uint32_t X26;
uint32_t X27;
uint32_t X28;
uint32_t X29;
uint32_t X30;
uint32_t X31;
uint32_t PC;
uint32_t NEXT_PC;
uint32_t trap_state, pending_trap, machine_state;
uint64_t icount;
} reg;
};
}
}
#endif /* _RV32IMAC_H_ */

+ 200
- 0
riscv.sc/incl/iss/arch/rv64ia.h View File

@ -0,0 +1,200 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Thu Sep 21 17:01:54 CEST 2017
// * rv64ia.h Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _RV64IA_H_
#define _RV64IA_H_
#include <iss/arch_if.h>
#include <iss/vm_if.h>
#include <iss/arch/traits.h>
namespace iss {
namespace arch {
struct rv64ia;
template<>
struct traits<rv64ia> {
enum constants {XLEN=64,XLEN2=128,XLEN_BIT_MASK=63,PCLEN=64,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=2147750144,PGSIZE=4096,PGMASK=4095};
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
ICOUNT
};
typedef uint64_t reg_t;
typedef uint64_t addr_t;
typedef uint64_t code_word_t; //TODO: check removal
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV64IA_reg_size[] = {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64};
return RV64IA_reg_size[r];
}
constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV64IA_reg_byte_offset[] = {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296};
return RV64IA_reg_byte_offset[r];
}
enum sreg_flag_e {FLAGS};
enum mem_type_e {MEM,CSR,FENCE,RES};
};
struct rv64ia: public arch_if {
using virt_addr_t = typename traits<rv64ia>::virt_addr_t;
using phys_addr_t = typename traits<rv64ia>::phys_addr_t;
using reg_t = typename traits<rv64ia>::reg_t;
using addr_t = typename traits<rv64ia>::addr_t;
rv64ia();
~rv64ia();
virtual void reset(uint64_t address=0) override;
virtual uint8_t* get_regs_base_ptr() override;
/// deprecated
virtual void get_reg(short idx, std::vector<uint8_t>& value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
virtual bool get_flag(int flag) override {return false;}
virtual void set_flag(int, bool value) override {};
/// deprecated
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
virtual void notify_phase(exec_phase phase){
if(phase==ISTART){
++reg.icount;
reg.PC=reg.NEXT_PC;
reg.trap_state=reg.pending_trap;
}
}
uint64_t get_icount() { return reg.icount;}
virtual phys_addr_t v2p(const iss::addr_t& pc);
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
protected:
struct RV64IA_regs {
uint64_t X0;
uint64_t X1;
uint64_t X2;
uint64_t X3;
uint64_t X4;
uint64_t X5;
uint64_t X6;
uint64_t X7;
uint64_t X8;
uint64_t X9;
uint64_t X10;
uint64_t X11;
uint64_t X12;
uint64_t X13;
uint64_t X14;
uint64_t X15;
uint64_t X16;
uint64_t X17;
uint64_t X18;
uint64_t X19;
uint64_t X20;
uint64_t X21;
uint64_t X22;
uint64_t X23;
uint64_t X24;
uint64_t X25;
uint64_t X26;
uint64_t X27;
uint64_t X28;
uint64_t X29;
uint64_t X30;
uint64_t X31;
uint64_t PC;
uint64_t NEXT_PC;
uint32_t trap_state, pending_trap, machine_state;
uint64_t icount;
} reg;
};
}
}
#endif /* _RV64IA_H_ */

riscv/incl/sysc/SiFive/core_complex.h → riscv.sc/incl/sysc/SiFive/core_complex.h View File


riscv/incl/sysc/SiFive/gen/e300_plat_t.h → riscv.sc/incl/sysc/SiFive/gen/e300_plat_t.h View File


riscv/incl/sysc/SiFive/gen/gpio_regs.h → riscv.sc/incl/sysc/SiFive/gen/gpio_regs.h View File


riscv/incl/sysc/SiFive/gen/plic_regs.h → riscv.sc/incl/sysc/SiFive/gen/plic_regs.h View File


riscv/incl/sysc/SiFive/gen/spi_regs.h → riscv.sc/incl/sysc/SiFive/gen/spi_regs.h View File


riscv/incl/sysc/SiFive/gen/uart_regs.h → riscv.sc/incl/sysc/SiFive/gen/uart_regs.h View File


riscv/incl/sysc/SiFive/gpio.h → riscv.sc/incl/sysc/SiFive/gpio.h View File


riscv/incl/sysc/SiFive/platform.h → riscv.sc/incl/sysc/SiFive/platform.h View File


riscv/incl/sysc/SiFive/plic.h → riscv.sc/incl/sysc/SiFive/plic.h View File


riscv/incl/sysc/SiFive/spi.h → riscv.sc/incl/sysc/SiFive/spi.h View File


riscv/incl/sysc/SiFive/uart.h → riscv.sc/incl/sysc/SiFive/uart.h View File


+ 62
- 0
riscv.sc/src/CMakeLists.txt View File

@ -0,0 +1,62 @@
# library files
FILE(GLOB RiscVSCHeaders *.h)
set(LIB_HEADERS ${RiscVSCHeaders} )
set(LIB_SOURCES
sysc/core_complex.cpp
sysc/gpio.cpp
sysc/plic.cpp
sysc/platform.cpp
sysc/spi.cpp
sysc/uart.cpp
)
set(APP_HEADERS )
set(APP_SOURCES sc_main.cpp
)
# Define two variables in order not to repeat ourselves.
set(LIBRARY_NAME risc-v.sc)
# Define the library
add_library(${LIBRARY_NAME} ${LIB_SOURCES})
set_target_properties(${LIBRARY_NAME} PROPERTIES
VERSION ${VERSION} # ${VERSION} was defined in the main CMakeLists.
FRAMEWORK FALSE
PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
)
# This is a make target, so you can do a "make riscv-sc"
set(APPLICATION_NAME riscv.sc)
add_executable(${APPLICATION_NAME} ${APP_SOURCES})
# Links the target exe against the libraries
target_link_libraries(${APPLICATION_NAME} ${LIBRARY_NAME})
target_link_libraries(${APPLICATION_NAME} dbt-core)
target_link_libraries(${APPLICATION_NAME} sc-components)
target_link_libraries(${APPLICATION_NAME} external)
target_link_libraries(${APPLICATION_NAME} risc-v)
target_link_libraries(${APPLICATION_NAME} ${llvm_libs})
target_link_libraries(${APPLICATION_NAME} ${SystemC_LIBRARIES} )
if(SCV_FOUND)
target_link_libraries (${APPLICATION_NAME} ${SCV_LIBRARIES})
endif()
target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} )
# Says how and where to install software
# Targets:
# * <prefix>/lib/<libraries>
# * header location after install: <prefix>/include/<project>/*.h
# * headers can be included by C++ code `#<project>/Bar.hpp>`
install(TARGETS ${LIBRARY_NAME} ${APPLICATION_NAME}
EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
ARCHIVE DESTINATION lib COMPONENT libs # static lib
RUNTIME DESTINATION bin COMPONENT libs # binaries
LIBRARY DESTINATION lib COMPONENT libs # shared lib
FRAMEWORK DESTINATION bin COMPONENT libs # for mac
PUBLIC_HEADER DESTINATION incl/${PROJECT_NAME} COMPONENT devel # headers for mac (note the different component -> different package)
INCLUDES DESTINATION incl # headers
)

+ 695
- 0
riscv.sc/src/internal/vm_riscv.in.cpp View File

@ -0,0 +1,695 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial API and implementation
//
//
////////////////////////////////////////////////////////////////////////////////
#include <iss/iss.h>
#include <iss/debugger/gdb_session.h>
#include <util/logging.h>
#include <memory>
#include <cstring>
#include "iss/vm_base.h"
#include "iss/arch/CORE_DEF_NAME.h"
#include "iss/debugger/server.h"
#include <boost/format.hpp>
#include "iss/arch/riscv_hart_msu_vp.h"
namespace iss {
namespace CORE_DEF_NAME {
using namespace iss::arch;
using namespace llvm;
using namespace iss::debugger;
template<typename ARCH>
struct vm_impl;
template<typename ARCH>
struct target_adapter: public target_adapter_base {
target_adapter(server_if* srv, vm_impl<ARCH>* vm)
: target_adapter_base(srv)
, vm(vm)
{
}
/*============== Thread Control ===============================*/
/* Set generic thread */
status set_gen_thread(rp_thread_ref& thread) override;
/* Set control thread */
status set_ctrl_thread(rp_thread_ref& thread) override;
/* Get thread status */
status is_thread_alive(rp_thread_ref& thread, bool& alive) override;
/*============= Register Access ================================*/
/* Read all registers. buf is 4-byte aligned and it is in
target byte order. If register is not available
corresponding bytes in avail_buf are 0, otherwise
avail buf is 1 */
status read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) override;
/* Write all registers. buf is 4-byte aligned and it is in target
byte order */
status write_registers(const std::vector<uint8_t>& data) override;
/* Read one register. buf is 4-byte aligned and it is in
target byte order. If register is not available
corresponding bytes in avail_buf are 0, otherwise
avail buf is 1 */
status read_single_register(unsigned int reg_no, std::vector<uint8_t>& buf, std::vector<uint8_t>& avail_buf) override;
/* Write one register. buf is 4-byte aligned and it is in target byte
order */
status write_single_register(unsigned int reg_no, const std::vector<uint8_t>& buf) override;
/*=================== Memory Access =====================*/
/* Read memory, buf is 4-bytes aligned and it is in target
byte order */
status read_mem(uint64_t addr, std::vector<uint8_t>& buf) override;
/* Write memory, buf is 4-bytes aligned and it is in target
byte order */
status write_mem(uint64_t addr, const std::vector<uint8_t>& buf) override;
status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override;
status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num, bool& done) override;
status current_thread_query(rp_thread_ref& thread) override;
status offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) override;
status crc_query(uint64_t addr, size_t len, uint32_t& val) override;
status raw_query(std::string in_buf, std::string& out_buf) override;
status threadinfo_query(int first, std::string& out_buf) override;
status threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) override;
status packetsize_query(std::string& out_buf) override;
status add_break(int type, uint64_t addr, unsigned int length) override;
status remove_break(int type, uint64_t addr, unsigned int length) override;
status resume_from_addr(bool step, int sig, uint64_t addr) override;
protected:
static inline constexpr addr_t map_addr(const addr_t& i){
return i;
}
vm_impl<ARCH>* vm;
rp_thread_ref thread_idx;
};
template<typename ARCH>
struct vm_impl: public vm::vm_base<ARCH> {
using super = typename vm::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
using addr_t = typename super::addr_t ;
vm_impl();
vm_impl(ARCH& core, bool dump=false);
void enableDebug(bool enable) {
super::sync_exec=super::ALL_SYNC;
}
target_adapter_if* accquire_target_adapter(server_if* srv){
debugger_if::dbg_enabled=true;
if(vm::vm_base<ARCH>::tgt_adapter==nullptr)
vm::vm_base<ARCH>::tgt_adapter=new target_adapter<ARCH>(srv, this);
return vm::vm_base<ARCH>::tgt_adapter;
}
protected:
template<typename T> inline
llvm::ConstantInt* size(T type){
return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
}
inline llvm::Value * gen_choose(llvm::Value * cond, llvm::Value * trueVal, llvm::Value * falseVal, unsigned size) const {
return this->gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
}
std::tuple<vm::continuation_e, llvm::BasicBlock*> gen_single_inst_behavior(virt_addr_t&, unsigned int&, llvm::BasicBlock*) override;
void gen_leave_behavior(llvm::BasicBlock* leave_blk) override;
void gen_raise_trap(uint16_t trap_id, uint16_t cause);
void gen_leave_trap(unsigned lvl);
void gen_wait(unsigned type);
void gen_trap_behavior(llvm::BasicBlock*) override;
void gen_trap_check(llvm::BasicBlock* bb);
inline
void gen_set_pc(virt_addr_t pc, unsigned reg_num){
llvm::Value* next_pc_v = this->builder->CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val), this->get_type(traits<ARCH>::XLEN));
this->builder->CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
}
inline
llvm::Value* get_reg_ptr(unsigned i){
void* ptr = this->core.get_regs_base_ptr()+traits<ARCH>::reg_byte_offset(i);
llvm::PointerType* ptrType=nullptr;
switch (traits<ARCH>::reg_bit_width(i)>>3) {
case 8:
ptrType=llvm::Type::getInt64PtrTy(this->mod->getContext());
break;
case 4:
ptrType=llvm::Type::getInt32PtrTy(this->mod->getContext());
break;
case 2:
ptrType=llvm::Type::getInt16PtrTy(this->mod->getContext());
break;
case 1:
ptrType=llvm::Type::getInt8PtrTy(this->mod->getContext());
break;
default:
throw std::runtime_error("unsupported access with");
break;
}
return llvm::ConstantExpr::getIntToPtr(
llvm::ConstantInt::get(this->mod->getContext(), llvm::APInt(
8/*bits*/ * sizeof(uint8_t*),
reinterpret_cast<uint64_t>(ptr)
)),
ptrType);
}
inline
llvm::Value* gen_reg_load(unsigned i, unsigned level=0){
// if(level){
return this->builder->CreateLoad(get_reg_ptr(i), false);
// } else {
// if(!this->loaded_regs[i])
// this->loaded_regs[i]=this->builder->CreateLoad(get_reg_ptr(i), false);
// return this->loaded_regs[i];
// }
}
inline
void gen_set_pc(virt_addr_t pc){
llvm::Value* pc_l = this->builder->CreateSExt(this->gen_const(traits<ARCH>::caddr_bit_width, (unsigned)pc), this->get_type(traits<ARCH>::caddr_bit_width));
super::gen_set_reg(traits<ARCH>::PC, pc_l);
}
// some compile time constants
enum {MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111};
enum {EXTR_MASK16 = MASK16>>2, EXTR_MASK32 = MASK32>>2};
enum {LUT_SIZE = 1<< bit_count(EXTR_MASK32), LUT_SIZE_C = 1<<bit_count(EXTR_MASK16)};
using this_class = vm_impl<ARCH>;
using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock*> (this_class::*)(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb);
compile_func lut[LUT_SIZE];
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
std::array<compile_func, LUT_SIZE> lut_11;
compile_func* qlut[4];// = {lut_00, lut_01, lut_10, lut_11};
const uint32_t lutmasks[4]={EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32};
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[], compile_func f){
if(pos<0){
lut[idx]=f;
} else {
auto bitmask = 1UL<<pos;
if((mask & bitmask)==0){
expand_bit_mask(pos-1, mask, value, valid, idx, lut, f);
} else {
if((valid & bitmask) == 0) {
expand_bit_mask(pos-1, mask, value, valid, (idx<<1), lut, f);
expand_bit_mask(pos-1, mask, value, valid, (idx<<1)+1, lut, f);
} else {
auto new_val = idx<<1;
if((value&bitmask)!=0)
new_val++;
expand_bit_mask(pos-1, mask, value, valid, new_val, lut, f);
}
}
}
}
inline uint32_t extract_fields(uint32_t val){
return extract_fields(29, val>>2, lutmasks[val&0x3], 0);
}
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val){
if(pos>=0) {
auto bitmask = 1UL<<pos;
if((mask & bitmask)==0){
lut_val = extract_fields(pos-1, val, mask, lut_val);
} else {
auto new_val = lut_val<<1;
if((val&bitmask)!=0)
new_val++;
lut_val = extract_fields(pos-1, val, mask, new_val);
}
}
return lut_val;
}
private:
/****************************************************************************
* start opcode definitions
****************************************************************************/
struct InstructionDesriptor {
size_t length;
uint32_t value;
uint32_t mask;
compile_func op;
};
/* «start generated code» */
InstructionDesriptor instr_descr[0] = {};
/* «end generated code» */
/****************************************************************************
* end opcode definitions
****************************************************************************/
std::tuple<vm::continuation_e, llvm::BasicBlock*> illegal_intruction(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
//this->gen_sync(iss::PRE_SYNC);
this->builder->CreateStore(
this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
get_reg_ptr(traits<ARCH>::PC), true);
this->builder->CreateStore(
this->builder->CreateAdd(
this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
this->gen_const(64U, 1)),
get_reg_ptr(traits<ARCH>::ICOUNT), true);
if(this->debugging_enabled()) this->gen_sync(iss::PRE_SYNC);
pc=pc+((instr&3) == 3?4:2);
this->gen_raise_trap(0, 2); // illegal instruction trap
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
}
};
template<typename CODE_WORD>
void debug_fn(CODE_WORD insn){
volatile CODE_WORD x=insn;
insn=2*x;
}
template<typename ARCH>
vm_impl<ARCH>::vm_impl(){
this(new ARCH());
}
template<typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH& core, bool dump) : vm::vm_base<ARCH>(core, dump) {
qlut[0] = lut_00.data();
qlut[1] = lut_01.data();
qlut[2] = lut_10.data();
qlut[3] = lut_11.data();
for(auto instr: instr_descr){
auto quantrant = instr.value&0x3;
expand_bit_mask(29, lutmasks[quantrant], instr.value>>2, instr.mask>>2, 0, qlut[quantrant], instr.op);
}
this->sync_exec=static_cast<sync_type>(this->sync_exec|core.needed_sync());
}
template<typename ARCH>
std::tuple<vm::continuation_e, llvm::BasicBlock*> vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt, llvm::BasicBlock* this_block){
// we fetch at max 4 byte, alignment is 2
code_word_t insn = 0;
iss::addr_t paddr;
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
try {
uint8_t* const data = (uint8_t*)&insn;
paddr=this->core.v2p(pc);
if((pc.val&upper_bits) != ((pc.val+2)&upper_bits)){ // we may cross a page boundary
auto res = this->core.read(paddr, 2, data);
if(res!=iss::Ok)
throw trap_access(1, pc.val);
if((insn & 0x3) == 0x3){ // this is a 32bit instruction
res = this->core.read(this->core.v2p(pc+2), 2, data+2);
}
} else {
auto res = this->core.read(paddr, 4, data);
if(res!=iss::Ok)
throw trap_access(1, pc.val);
}
} catch(trap_access& ta){
throw trap_access(ta.id, pc.val);
}
if(insn==0x0000006f)
throw simulation_stopped(0);
// curr pc on stack
typename vm_impl<ARCH>::processing_pc_entry addr(*this, pc, paddr);
++inst_cnt;
auto lut_val = extract_fields(insn);
auto f = qlut[insn&0x3][lut_val];
if (f==nullptr){
f=&this_class::illegal_intruction;
}
return (this->*f)(pc, insn, this_block);
}
template<typename ARCH>
void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock* leave_blk){
this->builder->SetInsertPoint(leave_blk);
this->builder->CreateRet(this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
}
template<typename ARCH>
void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause){
auto* TRAP_val = this->gen_const(32, 0x80<<24| (cause<<16) | trap_id );
this->builder->CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
}
template<typename ARCH>
void vm_impl<ARCH>::gen_leave_trap(unsigned lvl){
std::vector<llvm::Value*> args {
this->core_ptr,
llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)),
};
this->builder->CreateCall(this->mod->getFunction("leave_trap"), args);
auto* PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl<<8)+0x41, traits<ARCH>::XLEN/8);