Browse Source

C++11 refactoring

pull/1/head
Eyck Jentzsch 3 years ago
parent
commit
7c2539bff0
14 changed files with 622 additions and 215 deletions
  1. +61
    -48
      .cproject
  2. +6
    -0
      build.sh
  3. +1
    -1
      dbt-core
  4. +61
    -52
      riscv.sc/src/sysc/core_complex.cpp
  5. +4
    -4
      riscv/gen_input/RV32IBase.core_desc
  6. +1
    -0
      riscv/gen_input/minres_rv.core_desc
  7. +38
    -36
      riscv/incl/iss/arch/riscv_hart_msu_vp.h
  8. +5
    -4
      riscv/incl/iss/arch/rv32imac.h
  9. +6
    -5
      riscv/incl/iss/arch/rv64ia.h
  10. +5
    -4
      riscv/incl/iss/debugger/riscv_target_adapter.h
  11. +7
    -6
      riscv/src/internal/vm_riscv.in.cpp
  12. +230
    -31
      riscv/src/internal/vm_rv32imac.cpp
  13. +196
    -23
      riscv/src/internal/vm_rv64ia.cpp
  14. +1
    -1
      sc-components

+ 61
- 48
.cproject View File

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@ -78,7 +81,7 @@
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@ -277,6 +324,7 @@
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<buildTarget>clangformat</buildTarget>
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@ -284,6 +332,7 @@
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<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>riscv</buildTarget>
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<useDefaultCommand>true</useDefaultCommand>
@ -291,56 +340,20 @@
</target>
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<buildCommand>make</buildCommand>
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<buildTarget>riscv.sc</buildTarget>
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+ 6
- 0
build.sh View File

@ -0,0 +1,6 @@
mkdir -f build_rel
cd build_rel/
cmake .. -DCMAKE_BUILD_TYPE=RelWithDebInfo && \
cmake --build . && \
bin/riscv --reset=0x20400000 --verbose=4 $HOME/eclipse-workspace/RiscV-dhrystone/dhrystone

+ 1
- 1
dbt-core

@ -1 +1 @@
Subproject commit 4eb39e8583e591b50c97051db7ac667c209459ab
Subproject commit e70839fbf599302c976919afc590492b80bb2995

+ 61
- 52
riscv.sc/src/sysc/core_complex.cpp View File

@ -47,45 +47,54 @@
#ifdef WITH_SCV
#include <scv.h>
#include <array>
#endif
namespace sysc {
namespace SiFive {
using namespace std;
using namespace iss;
namespace {
iss::debugger::encoder_decoder encdec;
}
namespace {
const char lvl[] = {'U', 'S', 'H', 'M'};
const char *trap_str[] = {"Instruction address misaligned",
"Instruction access fault",
"Illegal instruction",
"Breakpoint",
"Load address misaligned",
"Load access fault",
"Store/AMO address misaligned",
"Store/AMO access fault",
"Environment call from U-mode",
"Environment call from S-mode",
"Reserved",
"Environment call from M-mode",
"Instruction page fault",
"Load page fault",
"Reserved",
"Store/AMO page fault"};
const char *irq_str[] = {
"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"};
std::array<const char, 4> lvl = { { 'U', 'S', 'H', 'M' } };
std::array<const char*, 16> trap_str = { {
"Instruction address misaligned",
"Instruction access fault",
"Illegal instruction",
"Breakpoint",
"Load address misaligned",
"Load access fault",
"Store/AMO address misaligned",
"Store/AMO access fault",
"Environment call from U-mode",
"Environment call from S-mode",
"Reserved",
"Environment call from M-mode",
"Instruction page fault",
"Load page fault",
"Reserved",
"Store/AMO page fault"
} };
std::array<const char*, 12> irq_str = { {
"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt" } };
}
class core_wrapper : public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac> {
public:
using core_type = iss::arch::rv32imac;
using base_type = iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>;
using phys_addr_t = typename iss::arch::traits<iss::arch::rv32imac>::phys_addr_t;
using core_type = arch::rv32imac;
using base_type = arch::riscv_hart_msu_vp<arch::rv32imac>;
using phys_addr_t = typename arch::traits<arch::rv32imac>::phys_addr_t;
core_wrapper(core_complex *owner)
: owner(owner)
{}
@ -96,7 +105,7 @@ public:
void notify_phase(exec_phase) override;
iss::sync_type needed_sync() const override { return iss::PRE_SYNC; }
sync_type needed_sync() const override { return PRE_SYNC; }
void disass_output(uint64_t pc, const std::string instr) override {
if (logging::INFO <= logging::Log<logging::Output2FILE<logging::disass>>::reporting_level() && logging::Output2FILE<logging::disass>::stream()){
@ -109,22 +118,22 @@ public:
owner->disass_output(pc,instr);
};
iss::status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) {
if (addr.access && iss::access_type::DEBUG)
return owner->read_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
status read_mem(phys_addr_t addr, unsigned length, uint8_t *const data) {
if (addr.access && access_type::DEBUG)
return owner->read_mem_dbg(addr.val, length, data) ? Ok : Err;
else {
return owner->read_mem(addr.val, length, data,addr.access && iss::access_type::FETCH) ? iss::Ok : iss::Err;
return owner->read_mem(addr.val, length, data,addr.access && access_type::FETCH) ? Ok : Err;
}
}
iss::status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) {
if (addr.access && iss::access_type::DEBUG)
return owner->write_mem_dbg(addr.val, length, data) ? iss::Ok : iss::Err;
status write_mem(phys_addr_t addr, unsigned length, const uint8_t *const data) {
if (addr.access && access_type::DEBUG)
return owner->write_mem_dbg(addr.val, length, data) ? Ok : Err;
else{
auto res = owner->write_mem(addr.val, length, data) ? iss::Ok : iss::Err;
auto res = owner->write_mem(addr.val, length, data) ? Ok : Err;
// TODO: this is an ugly hack (clear MTIP on mtimecmp write), needs to be fixed
if(addr.val==0x2004000)
this->csr[iss::arch::mip] &= ~(1ULL<<7);
this->csr[arch::mip] &= ~(1ULL<<7);
return res;
}
}
@ -140,13 +149,13 @@ public:
void local_irq(short id){
switch(id){
case 16: // SW
this->csr[iss::arch::mip] |= 1<<3;
this->csr[arch::mip] |= 1<<3;
break;
case 17: // timer
this->csr[iss::arch::mip] |= 1<<7;
this->csr[arch::mip] |= 1<<7;
break;
case 18: //external
this->csr[iss::arch::mip] |= 1<<11;
this->csr[arch::mip] |= 1<<11;
break;
default:
/* do nothing*/
@ -159,15 +168,15 @@ private:
sc_event wfi_evt;
};
int cmd_sysc(int argc, char* argv[], iss::debugger::out_func of, iss::debugger::data_func df, iss::debugger::target_adapter_if* tgt_adapter){
int cmd_sysc(int argc, char* argv[], debugger::out_func of, debugger::data_func df, debugger::target_adapter_if* tgt_adapter){
if(argc>1) {
if(strcasecmp(argv[1], "print_time")==0){
std::string t = sc_core::sc_time_stamp().to_string();
of(t.c_str());
char buf[64];
encdec.enc_string(t.c_str(), buf, 63);
df(buf);
return iss::Ok;
std::array<char, 64> buf;
encdec.enc_string(t.c_str(), buf.data(), 63);
df(buf.data());
return Ok;
} else if(strcasecmp(argv[1], "break")==0){
sc_core::sc_time t;
if(argc==4){
@ -175,17 +184,17 @@ int cmd_sysc(int argc, char* argv[], iss::debugger::out_func of, iss::debugger::
} else if(argc==3){
t= scc::parse_from_string(argv[2]);
} else
return iss::Err;
return Err;
// no check needed as it is only called if debug server is active
tgt_adapter->add_break_condition([t]()->unsigned{
LOG(TRACE)<<"Checking condition at "<<sc_core::sc_time_stamp();
return sc_core::sc_time_stamp()>=t?std::numeric_limits<unsigned>::max():0;
});
return iss::Ok;
return Ok;
}
return iss::Err;
return Err;
}
return iss::Err;
return Err;
}
@ -245,15 +254,15 @@ core_complex::~core_complex() = default;
void core_complex::trace(sc_core::sc_trace_file *trf) {}
void core_complex::before_end_of_elaboration() {
cpu = std::make_unique<core_wrapper>(this);
vm = iss::create<iss::arch::rv32imac>(cpu.get(), gdb_server_port.value, dump_ir.value);
cpu = make_unique<core_wrapper>(this);
vm = create<arch::rv32imac>(cpu.get(), gdb_server_port.value, dump_ir.value);
vm->setDisassEnabled(enable_disass.value);
auto* srv = iss::debugger::server<iss::debugger::gdb_session>::get();
auto* srv = debugger::server<debugger::gdb_session>::get();
if(srv) tgt_adapter = srv->get_target();
if(tgt_adapter)
tgt_adapter->add_custom_command({
"sysc",
[this](int argc, char* argv[], iss::debugger::out_func of, iss::debugger::data_func df)-> int {
[this](int argc, char* argv[], debugger::out_func of, debugger::data_func df)-> int {
return cmd_sysc(argc, argv, of, df, tgt_adapter);
},
"SystemC sub-commands: break <time>, print_time"});
@ -306,7 +315,7 @@ void core_complex::run() {
cpu->reset(reset_address.value);
try {
vm->start(-1);
} catch (iss::simulation_stopped &e) {
} catch (simulation_stopped &e) {
}
sc_core::sc_stop();
}

+ 4
- 4
riscv/gen_input/RV32IBase.core_desc View File

@ -41,7 +41,7 @@ InsructionSet RV32IBase {
val new_pc[XLEN] <= X[rs1]+ imm;
val align[XLEN] <= new_pc & 0x2;
if(align != 0){
raise(0, 0)
raise(0, 0);
} else {
if(rd!=0) X[rd] <= PC+4;
PC<=new_pc & ~0x1;
@ -160,7 +160,7 @@ InsructionSet RV32IBase {
encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
args_disass:"x%rd$d, x%rs1$d, %shamt%";
if(shamt > 31){
raise(0,0)
raise(0,0);
} else {
if(rd != 0) X[rd] <= shll(X[rs1], shamt);
}
@ -169,7 +169,7 @@ InsructionSet RV32IBase {
encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
args_disass:"x%rd$d, x%rs1$d, %shamt%";
if(shamt > 31){
raise(0,0)
raise(0,0);
} else {
if(rd != 0) X[rd] <= shrl(X[rs1], shamt);
}
@ -178,7 +178,7 @@ InsructionSet RV32IBase {
encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
args_disass:"x%rd$d, x%rs1$d, %shamt%";
if(shamt > 31){
raise(0,0)
raise(0,0);
} else {
if(rd != 0) X[rd] <= shra(X[rs1], shamt);
}

+ 1
- 0
riscv/gen_input/minres_rv.core_desc View File

@ -6,6 +6,7 @@ import "RV64IBase.core_desc"
//import "RV64M.core_desc"
import "RV64A.core_desc"
Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32CI {
template:"vm_riscv.in.cpp";
constants {

+ 38
- 36
riscv/incl/iss/arch/riscv_hart_msu_vp.h View File

@ -46,6 +46,7 @@
#include <util/ities.h>
#include <util/sparse_array.h>
#include <util/bit_field.h>
#include <array>
namespace iss {
namespace arch {
@ -159,28 +160,29 @@ enum csr_name {
namespace {
const char lvl[] = {'U', 'S', 'H', 'M'};
const char *trap_str[] = {"Instruction address misaligned", //0
"Instruction access fault", //1
"Illegal instruction", //2
"Breakpoint", //3
"Load address misaligned", //4
"Load access fault", //5
"Store/AMO address misaligned", //6
"Store/AMO access fault", //7
"Environment call from U-mode", //8
"Environment call from S-mode", //9
"Reserved", //a
"Environment call from M-mode", //b
"Instruction page fault", //c
"Load page fault", //d
"Reserved", //e
"Store/AMO page fault"}; //f
const char *irq_str[] = {
"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"};
std::array<const char, 4> lvl = { { 'U', 'S', 'H', 'M' } };
std::array<const char*, 16> trap_str = { { ""
"Instruction address misaligned", //0
"Instruction access fault", //1
"Illegal instruction", //2
"Breakpoint", //3
"Load address misaligned", //4
"Load access fault", //5
"Store/AMO address misaligned", //6
"Store/AMO access fault", //7
"Environment call from U-mode", //8
"Environment call from S-mode", //9
"Reserved", //a
"Environment call from M-mode", //b
"Instruction page fault", //c
"Load page fault", //d
"Reserved", //e
"Store/AMO page fault" } };
std::array<const char*, 12> irq_str = { {
"User software interrupt", "Supervisor software interrupt", "Reserved", "Machine software interrupt",
"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt", "User external interrupt",
"Supervisor external interrupt", "Reserved", "Machine external interrupt" } };
enum {
PGSHIFT = 12,
@ -313,7 +315,7 @@ public:
void write_mstatus(T val, unsigned priv_lvl){
auto mask = get_mask(priv_lvl);
auto new_val = (mstatus & ~mask) | (val & mask);
auto new_val = (mstatus.st.value & ~mask) | (val & mask);
mstatus=new_val;
}
@ -435,12 +437,12 @@ public:
const typename super::reg_t PGMASK = PGSIZE - 1;
constexpr reg_t get_irq_mask(size_t mode) {
const reg_t m[4] = {
0b000100010001, // U mode
0b001100110011, // S class="o">-mode
0,
0b101110111011 // M class="o">-mode
};
std::array<const reg_t,4> m = { {
0b000100010001,// U mode
0b001100110011,// S mode
0,
0b101110111011 // M mode
}};
return m[mode];
}
@ -485,7 +487,7 @@ protected:
mem_type mem;
csr_type csr;
hart_state<reg_t> state;
vm_info vm[2];
std::array<vm_info,2> vm;
void update_vm_info();
unsigned to_host_wr_cnt = 0;
std::stringstream uart_buf;
@ -552,11 +554,11 @@ riscv_hart_msu_vp::riscv_hart_msu_vp()
template <typename BASE> void riscv_hart_msu_vp<BASE>::load_file(std::string name, int type) {
FILE *fp = fopen(name.c_str(), "r");
if (fp) {
char buf[5];
auto n = fread(buf, 1, 4, fp);
std::array<char, 5> buf;
auto n = fread(buf.data(), 1, 4, fp);
if (n != 4) throw std::runtime_error("input file has insufficient size");
buf[4] = 0;
if (strcmp(buf + 1, "ELF") == 0) {
if (strcmp(buf.data() + 1, "ELF") == 0) {
fclose(fp);
// Create elfio reader
ELFIO::elfio reader;
@ -1209,10 +1211,10 @@ template uint64_t riscv_hart_msu_vp::enter_trap(uint64_t f
// reset trap state
this->reg.machine_state = new_priv;
this->reg.trap_state = 0;
char buffer[32];
sprintf(buffer, "0x%016lx", addr);
std::array<char, 32> buffer;
sprintf(buffer.data(), "0x%016lx", addr);
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause])<<"' ("<<trap_id<<")"
<< " at address " << buffer << " occurred, changing privilege level from " << lvl[cur_priv]
<< " at address " << buffer.data() << " occurred, changing privilege level from " << lvl[cur_priv]
<< " to " << lvl[new_priv];
update_vm_info();
return this->reg.NEXT_PC;

+ 5
- 4
riscv/incl/iss/arch/rv32imac.h View File

@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Sat Dec 30 12:50:15 CET 2017
// Created on: Tue Feb 06 17:18:49 UTC 2018
// * rv32imac.h Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@ -39,6 +39,7 @@
#include <iss/arch_if.h>
#include <iss/vm_if.h>
#include <iss/arch/traits.h>
#include <array>
namespace iss {
namespace arch {
@ -103,12 +104,12 @@ struct traits {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV32IMAC_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64};
constexpr std::array<const uint32_t, 38> RV32IMAC_reg_size{{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
return RV32IMAC_reg_size[r];
}
constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV32IMAC_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160};
class="n">constexpr class="n">std class="o">::array<const uint32_t, 39> RV32IMAC_reg_byte_offset{{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160}};
return RV32IMAC_reg_byte_offset[r];
}
@ -197,7 +198,7 @@ protected:
uint64_t icount = 0;
} reg;
address_type addr_mode[4];
std::array<address_type, 4> addr_mode;
uint64_t cycles = 0;

+ 6
- 5
riscv/incl/iss/arch/rv64ia.h View File

@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Sat Dec 30 12:50:15 CET 2017
// Created on: Tue Feb 06 17:18:50 UTC 2018
// * rv64ia.h Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@ -39,6 +39,7 @@
#include <iss/arch_if.h>
#include <iss/vm_if.h>
#include <iss/arch/traits.h>
#include <array>
namespace iss {
namespace arch {
@ -103,12 +104,12 @@ struct traits {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV64IA_reg_size[] = {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64};
constexpr std::array<const uint32_t, 38> RV64IA_reg_size{{64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64}};
return RV64IA_reg_size[r];
}
constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV64IA_reg_byte_offset[] = {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296};
class="n">constexpr class="n">std class="o">::array<const uint32_t, 39> RV64IA_reg_byte_offset{{0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296}};
return RV64IA_reg_byte_offset[r];
}
@ -197,10 +198,10 @@ protected:
uint64_t icount = 0;
} reg;
address_type addr_mode[4];
std::array<address_type, 4> addr_mode;
uint64_t cycles = 0;
};
}

+ 5
- 4
riscv/incl/iss/debugger/riscv_target_adapter.h View File

@ -15,6 +15,7 @@
#include <memory>
#include <util/logging.h>
#include <array>
namespace iss {
namespace debugger {
@ -279,10 +280,10 @@ template status riscv_target_adapter::threadinfo_query(int
template <typename ARCH>
status riscv_target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref &thread, std::string &out_buf) {
char buf[20];
memset(buf, 0, 20);
sprintf(buf, "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
out_buf = buf;
std::array<char, 20> buf;
memset(buf.data(), 0, 20);
sprintf(buf.data(), "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
out_buf = buf.data();
return Ok;
}

+ 7
- 6
riscv/src/internal/vm_riscv.in.cpp View File

@ -45,6 +45,7 @@
#include <boost/format.hpp>
#include <iss/debugger/riscv_target_adapter.h>
#include <array>
namespace iss {
namespace CORE_DEF_NAME {
@ -121,14 +122,14 @@ protected:
using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock *> (this_class::*)(virt_addr_t &pc,
code_word_t instr,
llvm::BasicBlock *bb);
compile_func lut[LUT_SIZE];
std::array<compile_func, LUT_SIZE> lut;
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
std::array<compile_func, LUT_SIZE> lut_11;
compile_func *qlut[4]; // = {lut_00, lut_01, lut_10, lut_11};
std::array<compile_func*, 4> qlut;
const uint32_t lutmasks[4] = {EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32};
class="n">std class="o">: class="o">: class="n">array<const uint32_t, 4> lutmasks = { { EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32 } };
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
compile_func f) {
@ -179,14 +180,14 @@ private:
};
/* «start generated code» */
InstructionDesriptor instr_descr[0] = {};
std::array<InstructionDesriptor, 0> instr_descr = { { } };
/* «end generated code» */
/****************************************************************************
* end opcode definitions
****************************************************************************/
std::tuple<vm::continuation_e, llvm::BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr,
llvm::BasicBlock *bb) {
this->gen_sync(iss::PRE_SYNC, sizeof(instr_descr)/sizeof(InstructionDesriptor));
this->gen_sync(iss::PRE_SYNC, instr_descr.size());
this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
get_reg_ptr(traits<ARCH>::PC), true);
this->builder.CreateStore(
@ -195,7 +196,7 @@ private:
get_reg_ptr(traits<ARCH>::ICOUNT), true);
pc = pc + ((instr & 3) == 3 ? 4 : 2);
this->gen_raise_trap(0, 2); // illegal instruction trap
this->gen_sync(iss::POST_SYNC, sizeof(instr_descr)/sizeof(InstructionDesriptor));
this->gen_sync(iss::POST_SYNC, instr_descr.size());
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
}

+ 230
- 31
riscv/src/internal/vm_rv32imac.cpp
File diff suppressed because it is too large
View File


+ 196
- 23
riscv/src/internal/vm_rv64ia.cpp View File

@ -45,6 +45,7 @@
#include <boost/format.hpp>
#include <iss/debugger/riscv_target_adapter.h>
#include <array>
namespace iss {
namespace rv64ia {
@ -121,14 +122,14 @@ protected:
using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock *> (this_class::*)(virt_addr_t &pc,
code_word_t instr,
llvm::BasicBlock *bb);
compile_func lut[LUT_SIZE];
std::array<compile_func, LUT_SIZE> lut;
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
std::array<compile_func, LUT_SIZE> lut_11;
compile_func *qlut[4]; // = {lut_00, lut_01, lut_10, lut_11};
std::array<compile_func*, 4> qlut;
const uint32_t lutmasks[4] = {EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32};
class="n">std class="o">: class="o">: class="n">array<const uint32_t, 4> lutmasks = { { EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32 } };
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
compile_func f) {
@ -179,7 +180,7 @@ private:
};
/* start generated code */
const InstructionDesriptor instr_descr[86] = {
const std::array<InstructionDesriptor, 86> instr_descr = {{
/* entries are: valid value, valid mask, function ptr */
/* instruction LWU */
{32, 0b00000000000000000110000000000011, 0b00000000000000000111000001111111, &this_class::__lwu},
@ -353,7 +354,7 @@ private:
{32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominu_w},
/* instruction AMOMAXU.W */
{32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_w},
};
}};
//0: instruction LWU
std::tuple<vm::continuation_e, llvm::BasicBlock*> __lwu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
bb->setName("LWU");
@ -374,6 +375,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
@ -413,6 +416,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
@ -452,6 +457,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
@ -489,6 +496,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_shamt_val > 31){
@ -528,6 +537,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_shamt_val > 31){
@ -567,6 +578,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_shamt_val > 31){
@ -606,6 +619,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -648,6 +663,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -690,6 +707,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -732,6 +751,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -772,6 +793,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -815,6 +838,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -860,6 +885,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -909,6 +936,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -958,6 +987,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -1006,6 +1037,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -1038,11 +1071,13 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* X_rd_val = this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, fld_imm_val));
this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
}
@ -1072,16 +1107,18 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* X_rd_val = this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, 4));
this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
}
Value* PC_val = this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, fld_imm_val));
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
this->gen_sync(iss::POST_SYNC, 17);
@ -1109,6 +1146,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* new_pc_val = this->builder.CreateAdd(
@ -1136,7 +1175,7 @@ private:
{
if(fld_rd_val != 0){
Value* X_rd_val = this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 1),
cur_pc_val,
this->gen_const(64U, 4));
this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
}
@ -1173,6 +1212,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* PC_val = this->gen_choose(
@ -1181,10 +1222,10 @@ private:
this->gen_reg_load(fld_rs1_val, 0),
this->gen_reg_load(fld_rs2_val, 0)),
this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, fld_imm_val)),
this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, 4)),
64);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
@ -1213,6 +1254,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* PC_val = this->gen_choose(
@ -1221,10 +1264,10 @@ private:
this->gen_reg_load(fld_rs1_val, 0),
this->gen_reg_load(fld_rs2_val, 0)),
this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, fld_imm_val)),
this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, 4)),
64);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
@ -1253,6 +1296,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* PC_val = this->gen_choose(
@ -1265,10 +1310,10 @@ private:
this->gen_reg_load(fld_rs2_val, 0),
64, true)),
this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, fld_imm_val)),
this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, 4)),
64);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
@ -1297,6 +1342,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* PC_val = this->gen_choose(
@ -1309,10 +1356,10 @@ private:
this->gen_reg_load(fld_rs2_val, 0),
64, true)),
this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, fld_imm_val)),
this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, 4)),
64);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
@ -1341,6 +1388,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* PC_val = this->gen_choose(
@ -1349,10 +1398,10 @@ private:
this->gen_reg_load(fld_rs1_val, 0),
this->gen_reg_load(fld_rs2_val, 0)),
this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, fld_imm_val)),
this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, 4)),
64);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
@ -1381,6 +1430,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* PC_val = this->gen_choose(
@ -1389,10 +1440,10 @@ private:
this->gen_reg_load(fld_rs1_val, 0),
this->gen_reg_load(fld_rs2_val, 0)),
this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, fld_imm_val)),
this->builder.CreateAdd(
this->gen_reg_load(traits<ARCH>::PC, 0),
cur_pc_val,
this->gen_const(64U, 4)),
64);
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
@ -1421,6 +1472,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
@ -1460,6 +1513,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
@ -1499,6 +1554,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
@ -1538,6 +1595,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
@ -1577,6 +1636,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
@ -1616,6 +1677,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
@ -1653,6 +1716,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
@ -1690,6 +1755,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
@ -1727,6 +1794,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -1762,6 +1831,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -1806,6 +1877,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
int64_t full_imm_val = fld_imm_val;
@ -1851,6 +1924,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -1886,6 +1961,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -1921,6 +1998,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
@ -1956,6 +2035,8 @@ private:
};
this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
}
Value* cur_pc_val = this->gen_const(64, pc.val);