Browse Source

Improved disassembly of running ISS

Eyck Jentzsch 6 months ago
parent
commit
769610d6fc

+ 5
- 3
conanfile.txt View File

@@ -1,6 +1,7 @@
1 1
 [requires]
2
-	gsl_microsoft/20180102@bincrafters/stable
3
-	spdlog/0.16.3@bincrafters/stable
2
+    gsl_microsoft/20180102@bincrafters/stable
3
+    spdlog/0.16.3@bincrafters/stable
4
+    fmt/5.2.1@bincrafters/stable 
4 5
     Seasocks/1.3.2@minres/stable
5 6
     SystemC/2.3.2@minres/stable
6 7
     SystemCVerification/2.0.1@minres/stable
@@ -11,7 +12,8 @@
11 12
 
12 13
 [options]
13 14
     Seasocks:shared=True
15
+    fmt:header_only=True
14 16
     SystemC:stdcxx=14
15 17
     SystemC:shared=True
16 18
     SystemCVerification:stdcxx=14
17
-    SystemC-CCI:stdcxx=14
19
+    SystemC-CCI:stdcxx=14

+ 1
- 1
dbt-core

@@ -1 +1 @@
1
-Subproject commit 0b499d216a2835015b889180ca5108b2daaed9b9
1
+Subproject commit 83cd591e4935d5c1916e4e56d9c6147e3aab8480

+ 11
- 11
riscv/gen_input/RV32A.core_desc View File

@@ -9,7 +9,7 @@ InsructionSet RV32A extends RV32IBase{
9 9
     instructions{
10 10
         LR.W {
11 11
             encoding: b00010 | aq[0:0] | rl[0:0]  | b00000 | rs1[4:0] | b010 | rd[4:0] | b0101111;
12
-            args_disass: "x%rd$d, x%rs1$d";
12
+            args_disass: "{name(rd)}, {name(rs1)}";
13 13
             if(rd!=0){
14 14
                 val offs[XLEN] <= X[rs1];
15 15
                 X[rd]<= sext(MEM[offs]{32}, XLEN);
@@ -18,7 +18,7 @@ InsructionSet RV32A extends RV32IBase{
18 18
         }
19 19
         SC.W {
20 20
             encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
21
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d";
21
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)}";
22 22
             val offs[XLEN] <= X[rs1];
23 23
             val res1[32] <= RES[offs]{32};
24 24
             if(res1!=0)
@@ -27,14 +27,14 @@ InsructionSet RV32A extends RV32IBase{
27 27
         }
28 28
         AMOSWAP.W{
29 29
             encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
30
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
30
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
31 31
             val offs[XLEN]<=X[rs1];
32 32
             if(rd!=0) X[rd]<=sext(MEM[offs]{32});
33 33
             MEM[offs]{32}<=X[rs2];
34 34
         }
35 35
         AMOADD.W{
36 36
             encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
37
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
37
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
38 38
             val offs[XLEN]<=X[rs1];
39 39
             val res1[XLEN] <= sext(MEM[offs]{32});
40 40
             if(rd!=0) X[rd]<=res1;
@@ -43,7 +43,7 @@ InsructionSet RV32A extends RV32IBase{
43 43
         }
44 44
         AMOXOR.W{
45 45
             encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
46
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
46
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
47 47
             val offs[XLEN]<=X[rs1];
48 48
             val res1[XLEN] <= sext(MEM[offs]{32});
49 49
             if(rd!=0) X[rd]<=res1;
@@ -52,7 +52,7 @@ InsructionSet RV32A extends RV32IBase{
52 52
         }
53 53
         AMOAND.W{
54 54
             encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
55
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
55
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
56 56
             val offs[XLEN]<=X[rs1];
57 57
             val res1[XLEN] <= sext(MEM[offs]{32});
58 58
             if(rd!=0) X[rd]<=res1;
@@ -61,7 +61,7 @@ InsructionSet RV32A extends RV32IBase{
61 61
         }
62 62
         AMOOR.W {
63 63
             encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
64
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
64
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
65 65
             val offs[XLEN]<=X[rs1];
66 66
             val res1[XLEN] <= sext(MEM[offs]{32});
67 67
             if(rd!=0) X[rd]<=res1;
@@ -70,7 +70,7 @@ InsructionSet RV32A extends RV32IBase{
70 70
         }
71 71
         AMOMIN.W{
72 72
             encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
73
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
73
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
74 74
             val offs[XLEN]<=X[rs1];
75 75
             val res1[XLEN] <= sext(MEM[offs]{32});
76 76
             if(rd!=0) X[rd]<=res1;
@@ -79,7 +79,7 @@ InsructionSet RV32A extends RV32IBase{
79 79
         }
80 80
         AMOMAX.W{
81 81
             encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
82
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
82
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
83 83
             val offs[XLEN]<=X[rs1];
84 84
             val res1[XLEN] <= sext(MEM[offs]{32});
85 85
             if(rd!=0) X[rd]<=res1;
@@ -88,7 +88,7 @@ InsructionSet RV32A extends RV32IBase{
88 88
         }
89 89
         AMOMINU.W{
90 90
             encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
91
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
91
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
92 92
             val offs[XLEN]<=X[rs1];
93 93
             val res1[XLEN] <= zext(MEM[offs]{32});
94 94
             if(rd!=0) X[rd]<=res1;
@@ -97,7 +97,7 @@ InsructionSet RV32A extends RV32IBase{
97 97
         }
98 98
         AMOMAXU.W{
99 99
             encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
100
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
100
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
101 101
             val offs[XLEN]<=X[rs1];
102 102
             val res1[XLEN] <= zext(MEM[offs]{32});
103 103
             if(rd!=0) X[rd]<=res1;

+ 37
- 37
riscv/gen_input/RV32C.core_desc View File

@@ -14,7 +14,7 @@ InsructionSet RV32IC {
14 14
     instructions{
15 15
         JALR(no_cont){ // overwriting the implementation if rv32i, alignment does not need to be word
16 16
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
17
-            args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
17
+            args_disass: "{name(rd)}, {name(rs1)}, {imm:#0x}";
18 18
             val new_pc[XLEN] <= X[rs1]s+ imm;
19 19
             val align[XLEN] <= new_pc & 0x1;
20 20
             if(align != 0){
@@ -26,25 +26,25 @@ InsructionSet RV32IC {
26 26
         }
27 27
         C.ADDI4SPN { //(RES, imm=0)
28 28
             encoding: b000 | imm[5:4] | imm[9:6] | imm[2:2] | imm[3:3] | rd[2:0] | b00;
29
-            args_disass: "x%rd$d, 0x%imm$05x";
29
+            args_disass: "{name(rd)}, {imm:#05x}";
30 30
             if(imm == 0) raise(0, 2);
31 31
             X[rd+8] <= X[2] + imm;
32 32
         }
33 33
         C.LW { // (RV32)
34 34
             encoding: b010 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
35
-            args_disass: "x(8+%rd$d), x(8+%rs1$d), 0x%uimm$05x";
35
+            args_disass: "{name(8+rd)}, {name(8+rs1)}, {uimm:#05x}";
36 36
             val offs[XLEN] <= X[rs1+8]+uimm;
37 37
             X[rd+8] <= MEM[offs]{32};
38 38
         }
39 39
         C.SW {//(RV32)
40 40
             encoding: b110 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
41
-            args_disass: "x(8+%rs1$d), x(8+%rs2$d), 0x%uimm$05x";
41
+            args_disass: "{name(8+rs1)}, {name(8+rs2)}, {uimm:#05x}";
42 42
             val offs[XLEN] <= X[rs1+8]+uimm;
43 43
             MEM[offs]{32} <= X[rs2+8];
44 44
         }
45 45
         C.ADDI {//(RV32)
46 46
             encoding:b000 | imm[5:5]s | rs1[4:0] | imm[4:0]s | b01;
47
-            args_disass: "x%rs1$d, 0x%imm$05x";
47
+            args_disass: "{name(rs1)}, {imm:#05x}";
48 48
             X[rs1] <= X[rs1]'s + imm;
49 49
         }
50 50
         C.NOP {
@@ -53,118 +53,118 @@ InsructionSet RV32IC {
53 53
         // C.JAL will be overwritten by C.ADDIW for RV64/128
54 54
         C.JAL(no_cont) {//(RV32)
55 55
             encoding: b001 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
56
-            args_disass: "0x%imm$05x";
56
+            args_disass: "{imm:#05x}";
57 57
             X[1] <= PC+2;
58 58
             PC<=PC's+imm;
59 59
         }
60 60
         C.LI {//(RV32)
61 61
             encoding:b010 | imm[5:5]s | rd[4:0] | imm[4:0]s | b01;
62
-            args_disass: "x%rd$d, 0x%imm$05x";
62
+            args_disass: "{name(rd)}, {imm:#05x}";
63 63
             if(rd == 0)    raise(0, 2);   //TODO: should it be handled as trap?
64 64
             X[rd] <= imm;
65 65
         }
66 66
         // order matters here as C.ADDI16SP overwrites C.LUI vor rd==2
67 67
         C.LUI {//(RV32)
68 68
             encoding:b011 | imm[17:17] | rd[4:0] | imm[16:12]s | b01;
69
-            args_disass: "x%rd$d, 0x%imm$05x";
69
+            args_disass: "{name(rd)}, {imm:#05x}";
70 70
             if(rd == 0) raise(0, 2);   //TODO: should it be handled as trap?
71 71
             if(imm == 0) raise(0, 2);   //TODO: should it be handled as trap?
72 72
             X[rd] <= imm;
73 73
         }
74 74
         C.ADDI16SP {//(RV32)
75 75
             encoding:b011 | imm[9:9]s | b00010 | imm[4:4]s | imm[6:6]s | imm[8:7]s | imm[5:5]s | b01;
76
-            args_disass: "0x%imm$05x";
76
+            args_disass: "{imm:#05x}";
77 77
             X[2] <= X[2]s + imm;
78 78
         }
79 79
         C.SRLI {//(RV32 nse)
80 80
             encoding:b100 | b0 | b00 | rs1[2:0] | shamt[4:0] | b01;
81
-            args_disass: "x(8+%rs1$d), %shamt$d";
81
+            args_disass: "{name(8+rs1)}, {shamt}";
82 82
             val rs1_idx[5] <= rs1+8;
83 83
             X[rs1_idx] <= shrl(X[rs1_idx], shamt);
84 84
         }
85 85
         C.SRAI {//(RV32)
86 86
             encoding:b100 | b0 | b01 | rs1[2:0] | shamt[4:0] | b01;
87
-            args_disass: "x(8+%rs1$d), %shamt$d";
87
+            args_disass: "{name(8+rs1)}, {shamt}";
88 88
             val rs1_idx[5] <= rs1+8;
89 89
             X[rs1_idx] <= shra(X[rs1_idx], shamt);
90 90
         }
91 91
         C.ANDI {//(RV32)
92 92
             encoding:b100 | imm[5:5] | b10 | rs1[2:0] | imm[4:0] | b01;
93
-            args_disass: "x(8+%rs1$d), 0x%imm$05x";
93
+            args_disass: "{name(8+rs1)}, {imm:#05x}";
94 94
             val rs1_idx[5] <= rs1 + 8;
95 95
             X[rs1_idx] <= X[rs1_idx] & imm;
96 96
         }
97 97
         C.SUB {//(RV32)
98 98
             encoding:b100 | b0 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
99
-            args_disass: "x(8+%rd$d), x(8+%rs2$d)";
99
+            args_disass: "{name(8+rd)}, {name(8+rs2)}";
100 100
             val rd_idx[5] <= rd + 8;
101 101
             X[rd_idx] <= X[rd_idx] - X[rs2 + 8];
102 102
         }
103 103
         C.XOR {//(RV32)
104 104
             encoding:b100 | b0 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
105
-            args_disass: "x(8+%rd$d), x(8+%rs2$d)";
105
+            args_disass: "{name(8+rd)}, {name(8+rs2)}";
106 106
             val rd_idx[5] <= rd + 8;
107 107
             X[rd_idx] <= X[rd_idx] ^ X[rs2 + 8];
108 108
         }
109 109
         C.OR {//(RV32)
110 110
             encoding:b100 | b0 | b11 | rd[2:0] | b10 | rs2[2:0] | b01;
111
-            args_disass: "x(8+%rd$d), x(8+%rs2$d)";
111
+            args_disass: "{name(8+rd)}, {name(8+rs2)}";
112 112
             val rd_idx[5] <= rd + 8;
113 113
             X[rd_idx] <= X[rd_idx] | X[rs2 + 8];
114 114
         }
115 115
         C.AND {//(RV32)
116 116
             encoding:b100 | b0 | b11 | rd[2:0] | b11 | rs2[2:0] | b01;
117
-            args_disass: "x(8+%rd$d), x(8+%rs2$d)";
117
+            args_disass: "{name(8+rd)}, {name(8+rs2)}";
118 118
             val rd_idx[5] <= rd + 8;
119 119
             X[rd_idx] <= X[rd_idx] & X[rs2 + 8];
120 120
         }
121 121
         C.J(no_cont) {//(RV32)
122 122
             encoding:b101 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
123
-            args_disass: "0x%imm$05x";
123
+            args_disass: "{imm:#05x}";
124 124
             PC<=PC's+imm;
125 125
         }
126 126
         C.BEQZ(no_cont,cond) {//(RV32)
127 127
             encoding:b110 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s |imm[2:1]s | imm[5:5]s | b01;
128
-            args_disass: "x(8+%rs1$d), 0x%imm$05x";
128
+            args_disass: "{name(8+rs1)}, {imm:#05x}";
129 129
             PC<=choose(X[rs1+8]==0, PC's+imm, PC+2);
130 130
         }
131 131
         C.BNEZ(no_cont,cond) {//(RV32)
132 132
             encoding:b111 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s | imm[2:1]s | imm[5:5]s | b01;
133
-            args_disass: "x(8+%rs1$d), 0x%imm$05x";
133
+            args_disass: "{name(8+rs1)}, {imm:#05x}";
134 134
             PC<=choose(X[rs1+8]!=0, PC's+imm, PC+2);
135 135
         }
136 136
         C.SLLI {//(RV32)
137 137
             encoding:b000 | b0 | rs1[4:0] | shamt[4:0] | b10;
138
-            args_disass: "x%rs1$d, %shamt$d";
138
+            args_disass: "{name(rs1)}, {shamt}";
139 139
             if(rs1 == 0) raise(0, 2);
140 140
             X[rs1] <= shll(X[rs1], shamt);
141 141
         }
142 142
         C.LWSP {//
143 143
             encoding:b010 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
144
-            args_disass: "x%rd$d, sp, 0x%uimm$05x";
144
+            args_disass: "{name(rd)}, sp, {uimm:#05x}";
145 145
             val offs[XLEN] <= X[2] + uimm;
146 146
             X[rd] <= MEM[offs]{32};
147 147
         }
148 148
         // order matters as C.JR is a special case of C.MV
149 149
         C.MV {//(RV32)
150 150
             encoding:b100 | b0 | rd[4:0] | rs2[4:0] | b10;
151
-            args_disass: "x%rd$d, x%rs2$d";
151
+            args_disass: "{name(rd)}, {name(rs2)}";
152 152
             X[rd] <= X[rs2];
153 153
         }
154 154
         C.JR(no_cont) {//(RV32)
155 155
             encoding:b100 | b0 | rs1[4:0] | b00000 | b10;
156
-            args_disass: "x%rs1$d";
156
+            args_disass: "{name(rs1)}";
157 157
             PC <= X[rs1];
158 158
         }
159 159
         // order matters as C.EBREAK is a special case of C.JALR which is a special case of C.ADD
160 160
         C.ADD {//(RV32)
161 161
             encoding:b100 | b1 | rd[4:0] | rs2[4:0] | b10;
162
-            args_disass: "x%rd$d, x%rs2$d";
162
+            args_disass: "{name(rd)}, {name(rs2)}";
163 163
             X[rd] <= X[rd] + X[rs2];
164 164
         }
165 165
         C.JALR(no_cont) {//(RV32)
166 166
             encoding:b100 | b1 | rs1[4:0] | b00000 | b10;
167
-            args_disass: "x%rs1$d";
167
+            args_disass: "{name(rs1)}";
168 168
             X[1] <= PC+2;
169 169
             PC<=X[rs1];
170 170
         }
@@ -174,7 +174,7 @@ InsructionSet RV32IC {
174 174
         }
175 175
         C.SWSP {//
176 176
             encoding:b110 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
177
-            args_disass: "x2+0x%uimm$05x, x%rs2$d";
177
+            args_disass: "x2+{uimm:#05x}, {name(rs2)}";
178 178
             val offs[XLEN] <= X[2] + uimm;
179 179
             MEM[offs]{32} <= X[rs2];
180 180
         }
@@ -199,7 +199,7 @@ InsructionSet RV32FC extends RV32IC{
199 199
     instructions{
200 200
         C.FLW {
201 201
             encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
202
-            args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))";
202
+            args_disass:"f(8+{rd}), {uimm}({name(8+rs1)})";
203 203
             val offs[XLEN] <= X[rs1+8]+uimm;
204 204
             val res[32] <= MEM[offs]{32};
205 205
             if(FLEN==32)
@@ -211,13 +211,13 @@ InsructionSet RV32FC extends RV32IC{
211 211
         } 
212 212
         C.FSW {
213 213
             encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
214
-            args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))";
214
+            args_disass:"f(8+{rs2}), {uimm}({name(8+rs1)})";
215 215
             val offs[XLEN] <= X[rs1+8]+uimm;
216 216
             MEM[offs]{32}<=F[rs2+8]{32};
217 217
         }
218 218
         C.FLWSP {
219 219
             encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
220
-            args_disass:"f%rd$d, %uimm%(x2)";
220
+            args_disass:"f{rd}, {uimm}(x2)";
221 221
             val offs[XLEN] <= X[2]+uimm;
222 222
             val res[32] <= MEM[offs]{32};
223 223
             if(FLEN==32)
@@ -229,7 +229,7 @@ InsructionSet RV32FC extends RV32IC{
229 229
         }
230 230
         C.FSWSP {
231 231
             encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
232
-            args_disass:"f%rs2$d, %uimm%(x2), ";
232
+            args_disass:"f{rs2}, {uimm}(x2), ";
233 233
             val offs[XLEN] <= X[2]+uimm;
234 234
             MEM[offs]{32}<=F[rs2]{32};
235 235
         }        
@@ -250,7 +250,7 @@ InsructionSet RV32DC extends RV32IC{
250 250
     instructions{
251 251
         C.FLD { //(RV32/64)
252 252
             encoding: b001 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
253
-            args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))";
253
+            args_disass:"f(8+{rd}), {uimm}({name(8+rs1)})";
254 254
             val offs[XLEN] <= X[rs1+8]+uimm;
255 255
             val res[64] <= MEM[offs]{64};
256 256
             if(FLEN==64)
@@ -262,13 +262,13 @@ InsructionSet RV32DC extends RV32IC{
262 262
          }
263 263
         C.FSD { //(RV32/64)
264 264
             encoding: b101 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
265
-            args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))";
265
+            args_disass:"f(8+{rs2}), {uimm}({name(8+rs1)})";
266 266
             val offs[XLEN] <= X[rs1+8]+uimm;
267 267
             MEM[offs]{64}<=F[rs2+8]{64};
268 268
         } 
269 269
         C.FLDSP {//(RV32/64)
270 270
             encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
271
-            args_disass:"f%rd$d, %uimm%(x2)";
271
+            args_disass:"f{rd}, {uimm}(x2)";
272 272
             val offs[XLEN] <= X[2]+uimm;
273 273
             val res[64] <= MEM[offs]{64};
274 274
             if(FLEN==64)
@@ -280,7 +280,7 @@ InsructionSet RV32DC extends RV32IC{
280 280
         }
281 281
         C.FSDSP {//(RV32/64)
282 282
             encoding:b101 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
283
-            args_disass:"f%rs2$d, %uimm%(x2), ";
283
+            args_disass:"f{rs2}, {uimm}(x2), ";
284 284
             val offs[XLEN] <= X[2]+uimm;
285 285
             MEM[offs]{64}<=F[rs2]{64};
286 286
         }
@@ -307,11 +307,11 @@ InsructionSet RV64IC extends RV32IC {
307 307
         }
308 308
         C.SUBW {//(RV64/128, RV32 res)
309 309
             encoding:b100 | b1 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
310
-            args_disass: "x%rd$d, sp, 0x%imm$05x";
310
+            args_disass: "{name(rd)}, sp, {imm:#05x}";
311 311
         }
312 312
         C.ADDW {//(RV64/128 RV32 res)
313 313
             encoding:b100 | b1 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
314
-            args_disass: "x%rd$d, sp, 0x%imm$05x";
314
+            args_disass: "{name(rd)}, sp, {imm:#05x}";
315 315
         }
316 316
         C.ADDIW {//(RV64/128)
317 317
             encoding:b001 | imm[5:5] | rs1[4:0] | imm[4:0] | b01;
@@ -327,7 +327,7 @@ InsructionSet RV64IC extends RV32IC {
327 327
         }
328 328
         C.LDSP {//(RV64/128
329 329
             encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
330
-            args_disass: "x%rd$d, sp, 0x%imm$05x";
330
+            args_disass: "{name(rd)}, sp, {imm:#05x}";
331 331
         }
332 332
         C.SDSP {//(RV64/128)
333 333
             encoding:b111 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;

+ 26
- 26
riscv/gen_input/RV32D.core_desc View File

@@ -10,7 +10,7 @@ InsructionSet RV32D extends RV32IBase{
10 10
     instructions{
11 11
         FLD {
12 12
             encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000111;
13
-            args_disass:"f%rd$d, %imm%(x%rs1$d)";
13
+            args_disass:"f{rd}, {imm}({rs1})";
14 14
             val offs[XLEN] <= X[rs1]'s + imm;
15 15
             val res[64] <= MEM[offs]{64};
16 16
             if(FLEN==64)
@@ -22,13 +22,13 @@ InsructionSet RV32D extends RV32IBase{
22 22
         }
23 23
         FSD {
24 24
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100111;
25
-            args_disass:"f%rs2$d, %imm%(x%rs1$d)";
25
+            args_disass:"f{rs2}, {imm}({rs1})";
26 26
             val offs[XLEN] <= X[rs1]'s + imm;
27 27
             MEM[offs]{64}<=F[rs2]{64};
28 28
         }
29 29
         FMADD.D {
30 30
             encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
31
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
31
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
32 32
             //F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
33 33
             val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(0, 64), choose(rm<7, rm{8}, FCSR{8}));
34 34
             if(FLEN==64)
@@ -42,7 +42,7 @@ InsructionSet RV32D extends RV32IBase{
42 42
         }
43 43
         FMSUB.D {
44 44
             encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
45
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
45
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
46 46
             //F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
47 47
             val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
48 48
             if(FLEN==64)
@@ -56,7 +56,7 @@ InsructionSet RV32D extends RV32IBase{
56 56
         }
57 57
         FNMADD.D {
58 58
             encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
59
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
59
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
60 60
             //F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
61 61
             val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
62 62
             if(FLEN==64)
@@ -70,7 +70,7 @@ InsructionSet RV32D extends RV32IBase{
70 70
         }
71 71
         FNMSUB.D {
72 72
             encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
73
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
73
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}, f{rs3}";
74 74
             //F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
75 75
             val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
76 76
             if(FLEN==64)
@@ -84,7 +84,7 @@ InsructionSet RV32D extends RV32IBase{
84 84
         }
85 85
         FADD.D {
86 86
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
87
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
87
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}";
88 88
             // F[rd]f <= F[rs1]f + F[rs2]f;
89 89
             val res[64] <= fdispatch_fadd_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
90 90
             if(FLEN==64)
@@ -98,7 +98,7 @@ InsructionSet RV32D extends RV32IBase{
98 98
         }
99 99
         FSUB.D {
100 100
             encoding: b0000101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
101
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
101
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}";
102 102
             // F[rd]f <= F[rs1]f - F[rs2]f;
103 103
             val res[64] <= fdispatch_fsub_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
104 104
             if(FLEN==64)
@@ -112,7 +112,7 @@ InsructionSet RV32D extends RV32IBase{
112 112
         }
113 113
         FMUL.D {
114 114
             encoding: b0001001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
115
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
115
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}";
116 116
             // F[rd]f <= F[rs1]f * F[rs2]f;
117 117
             val res[64] <= fdispatch_fmul_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
118 118
             if(FLEN==64)
@@ -126,7 +126,7 @@ InsructionSet RV32D extends RV32IBase{
126 126
         }
127 127
         FDIV.D {
128 128
             encoding: b0001101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
129
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
129
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}";
130 130
             // F[rd]f <= F[rs1]f / F[rs2]f;
131 131
             val res[64] <= fdispatch_fdiv_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
132 132
             if(FLEN==64)
@@ -140,7 +140,7 @@ InsructionSet RV32D extends RV32IBase{
140 140
         }
141 141
         FSQRT.D {
142 142
             encoding: b0101101 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
143
-            args_disass:"x%rd$d, f%rs1$d";
143
+            args_disass:"{name(rd)}, f{rs1}";
144 144
             //F[rd]f<=sqrt(F[rs1]f);
145 145
             val res[64] <= fdispatch_fsqrt_d(F[rs1]{64}, choose(rm<7, rm{8}, FCSR{8}));
146 146
             if(FLEN==64)
@@ -154,7 +154,7 @@ InsructionSet RV32D extends RV32IBase{
154 154
         }
155 155
         FSGNJ.D {
156 156
             encoding: b0010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
157
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
157
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
158 158
             val res[64] <= (F[rs1]{64} & 0x7fffffff) | (F[rs2]{64} & 0x80000000);
159 159
             if(FLEN==64)
160 160
                 F[rd] <= res;
@@ -165,7 +165,7 @@ InsructionSet RV32D extends RV32IBase{
165 165
         }
166 166
         FSGNJN.D {
167 167
             encoding: b0010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
168
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
168
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
169 169
             val res[64] <= (F[rs1]{64} & 0x7fffffff) | (~F[rs2]{64} & 0x80000000);
170 170
             if(FLEN==64)
171 171
                 F[rd] <= res;
@@ -176,7 +176,7 @@ InsructionSet RV32D extends RV32IBase{
176 176
         }
177 177
         FSGNJX.D {
178 178
             encoding: b0010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
179
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
179
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
180 180
             val res[64] <= F[rs1]{64} ^ (F[rs2]{64} & 0x80000000);
181 181
             if(FLEN==64)
182 182
                 F[rd] <= res;
@@ -187,7 +187,7 @@ InsructionSet RV32D extends RV32IBase{
187 187
         }
188 188
         FMIN.D  {
189 189
             encoding: b0010101 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
190
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
190
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
191 191
             //F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
192 192
             val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32));
193 193
             if(FLEN==64)
@@ -201,7 +201,7 @@ InsructionSet RV32D extends RV32IBase{
201 201
         }
202 202
         FMAX.D {
203 203
             encoding: b0010101 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
204
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
204
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
205 205
             //F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
206 206
             val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32));
207 207
             if(FLEN==64)
@@ -215,7 +215,7 @@ InsructionSet RV32D extends RV32IBase{
215 215
         }
216 216
         FCVT.S.D {
217 217
             encoding: b0100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
218
-            args_disass:"f%rd$d, f%rs1$d";
218
+            args_disass:"f{rd}, f{rs1}";
219 219
             val res[32] <= fdispatch_fconv_d2f(F[rs1], rm{8});
220 220
             // NaN boxing
221 221
             val upper[FLEN] <= -1;
@@ -223,7 +223,7 @@ InsructionSet RV32D extends RV32IBase{
223 223
         }
224 224
         FCVT.D.S {
225 225
             encoding: b0100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
226
-            args_disass:"f%rd$d, f%rs1$d";
226
+            args_disass:"f{rd}, f{rs1}";
227 227
             val res[64] <= fdispatch_fconv_f2d(F[rs1]{32}, rm{8});
228 228
             if(FLEN==64){
229 229
                 F[rd] <= res;
@@ -234,47 +234,47 @@ InsructionSet RV32D extends RV32IBase{
234 234
         }
235 235
         FEQ.D {
236 236
             encoding: b1010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
237
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
237
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}";
238 238
             X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32));
239 239
             val flags[32] <= fdispatch_fget_flags();
240 240
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
241 241
         }
242 242
         FLT.D {
243 243
             encoding: b1010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
244
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
244
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}";
245 245
             X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(2, 32));
246 246
             val flags[32] <= fdispatch_fget_flags();
247 247
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
248 248
         }
249 249
         FLE.D {
250 250
             encoding: b1010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
251
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
251
+            args_disass:"{name(rd)}, f{rs1}, f{rs2}";
252 252
             X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32));
253 253
             val flags[32] <= fdispatch_fget_flags();
254 254
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
255 255
         }
256 256
         FCLASS.D {
257 257
             encoding: b1110001 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
258
-            args_disass:"x%rd$d, f%rs1$d";
258
+            args_disass:"{name(rd)}, f{rs1}";
259 259
             X[rd]<=fdispatch_fclass_d(F[rs1]{64});
260 260
         }
261 261
         FCVT.W.D {
262 262
             encoding: b1100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
263
-            args_disass:"x%rd$d, f%rs1$d";
263
+            args_disass:"{name(rd)}, f{rs1}";
264 264
             X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(0, 32), rm{8}), XLEN);
265 265
             val flags[32] <= fdispatch_fget_flags();
266 266
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
267 267
         }
268 268
         FCVT.WU.D {
269 269
             encoding: b1100001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
270
-            args_disass:"x%rd$d, f%rs1$d";
270
+            args_disass:"{name(rd)}, f{rs1}";
271 271
             X[rd]<= zext(fdispatch_fcvt_d(F[rs1]{64}, zext(1, 32), rm{8}), XLEN);
272 272
             val flags[32] <= fdispatch_fget_flags();
273 273
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
274 274
         }
275 275
         FCVT.D.W {
276 276
             encoding: b1101001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
277
-            args_disass:"f%rd$d, x%rs1$d";
277
+            args_disass:"f{rd}, {rs1}";
278 278
             val res[64] <= fdispatch_fcvt_d(sext(X[rs1],64), zext(2, 32), rm{8});
279 279
             if(FLEN==64)
280 280
                 F[rd] <= res;
@@ -285,7 +285,7 @@ InsructionSet RV32D extends RV32IBase{
285 285
         }
286 286
         FCVT.D.WU {
287 287
             encoding: b1101001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
288
-            args_disass:"f%rd$d, x%rs1$d";
288
+            args_disass:"f{rd}, {rs1}";
289 289
             val res[64] <=fdispatch_fcvt_d(zext(X[rs1],64), zext(3,32), rm{8});
290 290
             if(FLEN==64)
291 291
                 F[rd] <= res;

+ 26
- 26
riscv/gen_input/RV32F.core_desc View File

@@ -10,7 +10,7 @@ InsructionSet RV32F extends RV32IBase{
10 10
     instructions{
11 11
         FLW {
12 12
             encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
13
-            args_disass:"f%rd$d, %imm%(x%rs1$d)";
13
+            args_disass:"f{rd}, {imm}(x{rs1})";
14 14
             val offs[XLEN] <= X[rs1]'s + imm;
15 15
             val res[32] <= MEM[offs]{32};
16 16
             if(FLEN==32)
@@ -22,13 +22,13 @@ InsructionSet RV32F extends RV32IBase{
22 22
         }
23 23
         FSW {
24 24
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
25
-            args_disass:"f%rs2$d, %imm%(x%rs1$d)";
25
+            args_disass:"f{rs2}, {imm}(x{rs1})";
26 26
             val offs[XLEN] <= X[rs1]'s + imm;
27 27
             MEM[offs]{32}<=F[rs2]{32};
28 28
         }
29 29
         FMADD.S {
30 30
             encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
31
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
31
+            args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
32 32
             //F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
33 33
             val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
34 34
             if(FLEN==32)
@@ -42,7 +42,7 @@ InsructionSet RV32F extends RV32IBase{
42 42
         }
43 43
         FMSUB.S {
44 44
             encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
45
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
45
+            args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
46 46
             //F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
47 47
             val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
48 48
             if(FLEN==32)
@@ -56,7 +56,7 @@ InsructionSet RV32F extends RV32IBase{
56 56
         }
57 57
         FNMADD.S {
58 58
             encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
59
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
59
+            args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
60 60
             //F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
61 61
             val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
62 62
             if(FLEN==32)
@@ -70,7 +70,7 @@ InsructionSet RV32F extends RV32IBase{
70 70
         }
71 71
         FNMSUB.S {
72 72
             encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
73
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
73
+            args_disass:"x{rd}, f{rs1}, f{rs2}, f{rs3}";
74 74
             //F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
75 75
             val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
76 76
             if(FLEN==32)
@@ -84,7 +84,7 @@ InsructionSet RV32F extends RV32IBase{
84 84
         }
85 85
         FADD.S {
86 86
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
87
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
87
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
88 88
             // F[rd]f <= F[rs1]f + F[rs2]f;
89 89
             val res[32] <= fdispatch_fadd_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
90 90
             if(FLEN==32)
@@ -98,7 +98,7 @@ InsructionSet RV32F extends RV32IBase{
98 98
         }
99 99
         FSUB.S {
100 100
             encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
101
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
101
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
102 102
             // F[rd]f <= F[rs1]f - F[rs2]f;
103 103
             val res[32] <= fdispatch_fsub_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
104 104
             if(FLEN==32)
@@ -112,7 +112,7 @@ InsructionSet RV32F extends RV32IBase{
112 112
         }
113 113
         FMUL.S {
114 114
             encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
115
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
115
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
116 116
             // F[rd]f <= F[rs1]f * F[rs2]f;
117 117
             val res[32] <= fdispatch_fmul_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
118 118
             if(FLEN==32)
@@ -126,7 +126,7 @@ InsructionSet RV32F extends RV32IBase{
126 126
         }
127 127
         FDIV.S {
128 128
             encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
129
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
129
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
130 130
             // F[rd]f <= F[rs1]f / F[rs2]f;
131 131
             val res[32] <= fdispatch_fdiv_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
132 132
             if(FLEN==32)
@@ -140,7 +140,7 @@ InsructionSet RV32F extends RV32IBase{
140 140
         }
141 141
         FSQRT.S {
142 142
             encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
143
-            args_disass:"f%rd$d, f%rs1$d";
143
+            args_disass:"f{rd}, f{rs1}";
144 144
             //F[rd]f<=sqrt(F[rs1]f);
145 145
             val res[32] <= fdispatch_fsqrt_s(F[rs1]{32}, choose(rm<7, rm{8}, FCSR{8}));
146 146
             if(FLEN==32)
@@ -154,7 +154,7 @@ InsructionSet RV32F extends RV32IBase{
154 154
         }
155 155
         FSGNJ.S {
156 156
             encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
157
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
157
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
158 158
             val res[32] <= (F[rs1]{32} & 0x7fffffff) | (F[rs2]{32} & 0x80000000);
159 159
             if(FLEN==32)
160 160
                 F[rd] <= res;
@@ -165,7 +165,7 @@ InsructionSet RV32F extends RV32IBase{
165 165
         }
166 166
         FSGNJN.S {
167 167
             encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
168
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
168
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
169 169
             val res[32] <= (F[rs1]{32} & 0x7fffffff) | (~F[rs2]{32} & 0x80000000);
170 170
             if(FLEN==32)
171 171
                 F[rd] <= res;
@@ -176,7 +176,7 @@ InsructionSet RV32F extends RV32IBase{
176 176
         }
177 177
         FSGNJX.S {
178 178
             encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
179
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
179
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
180 180
             val res[32] <= F[rs1]{32} ^ (F[rs2]{32} & 0x80000000);
181 181
             if(FLEN==32)
182 182
                 F[rd] <= res;
@@ -187,7 +187,7 @@ InsructionSet RV32F extends RV32IBase{
187 187
         }
188 188
         FMIN.S  {
189 189
             encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
190
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
190
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
191 191
             //F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
192 192
             val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
193 193
             if(FLEN==32)
@@ -201,7 +201,7 @@ InsructionSet RV32F extends RV32IBase{
201 201
         }
202 202
         FMAX.S {
203 203
             encoding: b0010100 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
204
-            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
204
+            args_disass:"f{rd}, f{rs1}, f{rs2}";
205 205
             //F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
206 206
             val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
207 207
             if(FLEN==32)
@@ -215,47 +215,47 @@ InsructionSet RV32F extends RV32IBase{
215 215
         }
216 216
         FCVT.W.S {
217 217
             encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
218
-            args_disass:"x%rd$d, f%rs1$d";
218
+            args_disass:"x{rd}, f{rs1}";
219 219
             X[rd]<= sext(fdispatch_fcvt_s(F[rs1]{32}, zext(0, 32), rm{8}), XLEN);
220 220
             val flags[32] <= fdispatch_fget_flags();
221 221
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
222 222
         }
223 223
         FCVT.WU.S {
224 224
             encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
225
-            args_disass:"x%rd$d, f%rs1$d";
225
+            args_disass:"x{rd}, f{rs1}";
226 226
             X[rd]<= zext(fdispatch_fcvt_s(F[rs1]{32}, zext(1, 32), rm{8}), XLEN);
227 227
             val flags[32] <= fdispatch_fget_flags();
228 228
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
229 229
         }
230 230
         FEQ.S {
231 231
             encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
232
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
232
+            args_disass:"x{rd}, f{rs1}, f{rs2}";
233 233
             X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
234 234
             val flags[32] <= fdispatch_fget_flags();
235 235
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
236 236
         }
237 237
         FLT.S {
238 238
             encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
239
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
239
+            args_disass:"x{rd}, f{rs1}, f{rs2}";
240 240
             X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32));
241 241
             val flags[32] <= fdispatch_fget_flags();
242 242
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
243 243
         }
244 244
         FLE.S {
245 245
             encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
246
-            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
246
+            args_disass:"x{rd}, f{rs1}, f{rs2}";
247 247
             X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
248 248
             val flags[32] <= fdispatch_fget_flags();
249 249
             FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
250 250
         }
251 251
         FCLASS.S {
252 252
             encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
253
-            args_disass:"x%rd$d, f%rs1$d";
253
+            args_disass:"x{rd}, f{rs1}";
254 254
             X[rd]<=fdispatch_fclass_s(F[rs1]{32});
255 255
         }
256 256
         FCVT.S.W {
257 257
             encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
258
-            args_disass:"f%rd$d, x%rs1$d";
258
+            args_disass:"f{rd}, x{rs1}";
259 259
             val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
260 260
             if(FLEN==32)
261 261
                 F[rd] <= res;
@@ -266,7 +266,7 @@ InsructionSet RV32F extends RV32IBase{
266 266
         }
267 267
         FCVT.S.WU {
268 268
             encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
269
-            args_disass:"f%rd$d, x%rs1$d";
269
+            args_disass:"f{rd}, x{rs1}";
270 270
             val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
271 271
             if(FLEN==32)
272 272
                 F[rd] <= res;
@@ -277,12 +277,12 @@ InsructionSet RV32F extends RV32IBase{
277 277
         }
278 278
         FMV.X.W {
279 279
             encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
280
-            args_disass:"x%rd$d, f%rs1$d";
280
+            args_disass:"x{rd}, f{rs1}";
281 281
             X[rd]<=sext(F[rs1]{32});
282 282
         }
283 283
         FMV.W.X {
284 284
             encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
285
-            args_disass:"f%rd$d, x%rs1$d";
285
+            args_disass:"f{rd}, x{rs1}";
286 286
             if(FLEN==32)
287 287
                 F[rd] <= X[rs1];
288 288
             else { // NaN boxing

+ 75
- 44
riscv/gen_input/RV32IBase.core_desc View File

@@ -14,29 +14,60 @@ InsructionSet RV32IBase {
14 14
     registers { 
15 15
         [31:0]   X[XLEN],
16 16
                 PC[XLEN](is_pc),
17
-                alias ZERO[XLEN] is X[0]
17
+                alias ZERO[XLEN] is X[0],
18
+                alias RA[XLEN] is X[1],
19
+                alias SP[XLEN] is X[2],
20
+                alias GP[XLEN] is X[3],
21
+                alias TP[XLEN] is X[4],
22
+                alias T0[XLEN] is X[5],
23
+                alias T1[XLEN] is X[6],
24
+                alias T2[XLEN] is X[7],
25
+                alias S0[XLEN] is X[8],
26
+                alias S1[XLEN] is X[9],
27
+                alias A0[XLEN] is X[10],
28
+                alias A1[XLEN] is X[11],
29
+                alias A2[XLEN] is X[12],
30
+                alias A3[XLEN] is X[13],
31
+                alias A4[XLEN] is X[14],
32
+                alias A5[XLEN] is X[15],
33
+                alias A6[XLEN] is X[16],
34
+                alias A7[XLEN] is X[17],
35
+                alias S2[XLEN] is X[18],
36
+                alias S3[XLEN] is X[19],
37
+                alias S4[XLEN] is X[20],
38
+                alias S5[XLEN] is X[21],
39
+                alias S6[XLEN] is X[22],
40
+                alias S7[XLEN] is X[23],
41
+                alias S8[XLEN] is X[24],
42
+                alias S9[XLEN] is X[25],
43
+                alias S10[XLEN] is X[26],
44
+                alias S11[XLEN] is X[27],
45
+                alias T3[XLEN] is X[28],
46
+                alias T4[XLEN] is X[29],
47
+                alias T5[XLEN] is X[30],
48
+                alias T6[XLEN] is X[31]
18 49
     }
19 50
      
20 51
     instructions { 
21 52
         LUI{
22 53
             encoding: imm[31:12]s | rd[4:0] | b0110111;
23
-            args_disass: "x%rd$d, 0x%imm$05x";
54
+            args_disass: "{name(rd)}, {imm:#05x}";
24 55
             if(rd!=0) X[rd] <= imm;
25 56
         }
26 57
         AUIPC{
27 58
             encoding: imm[31:12]s | rd[4:0] | b0010111;
28
-            args_disass: "x%rd%, 0x%imm$08x";
59
+            args_disass: "{name(rd)}, {imm:#08x}";
29 60
             if(rd!=0) X[rd] <= PC's+imm;
30 61
         }
31 62
         JAL(no_cont){
32 63
             encoding: imm[20:20]s | imm[10:1]s | imm[11:11]s | imm[19:12]s | rd[4:0] | b1101111;
33
-            args_disass: "x%rd$d, 0x%imm$x";
64
+            args_disass: "{name(rd)}, {imm:#0x}";
34 65
             if(rd!=0) X[rd] <= PC+4;
35 66
             PC<=PC's+imm;
36 67
         }
37 68
         JALR(no_cont){
38 69
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
39
-            args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
70
+            args_disass: "{name(rd)}, {name(rs1)}, {imm:#0x}";
40 71
             val new_pc[XLEN] <= X[rs1]'s+ imm;
41 72
             val align[XLEN] <= new_pc & 0x2;
42 73
             if(align != 0){
@@ -48,116 +79,116 @@ InsructionSet RV32IBase {
48 79
         }
49 80
         BEQ(no_cont,cond){
50 81
             encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011;
51
-            args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
82
+            args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
52 83
             PC<=choose(X[rs1]==X[rs2], PC's+imm, PC+4);
53 84
         }
54 85
         BNE(no_cont,cond){
55 86
             encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011;
56
-            args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
87
+            args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
57 88
             PC<=choose(X[rs1]!=X[rs2], PC's+imm, PC+4);
58 89
         }
59 90
         BLT(no_cont,cond){
60 91
             encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011;
61
-            args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
92
+            args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
62 93
             PC<=choose(X[rs1]s<X[rs2]s, PC's+imm, PC+4);
63 94
         }
64 95
         BGE(no_cont,cond) {
65 96
             encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b101 | imm[4:1]s | imm[11:11]s | b1100011;
66
-            args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
97
+            args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
67 98
             PC<=choose(X[rs1]s>=X[rs2]s, PC's+imm, PC+4);
68 99
         }
69 100
         BLTU(no_cont,cond) {
70 101
             encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011;
71
-            args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
102
+            args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
72 103
             PC<=choose(X[rs1]<X[rs2],PC's+imm, PC+4);
73 104
         }
74 105
         BGEU(no_cont,cond) {
75 106
             encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b111 | imm[4:1]s | imm[11:11]s | b1100011;
76
-            args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
107
+            args_disass:"{name(rs1)}, {name(rs2)}, {imm:#0x}";
77 108
             PC<=choose(X[rs1]>=X[rs2], PC's+imm, PC+4);
78 109
         }
79 110
         LB {
80 111
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0000011;
81
-            args_disass:"x%rd$d, %imm%(x%rs1$d)";
112
+            args_disass:"{name(rd)}, {imm}({name(rs1)})";
82 113
             val offs[XLEN] <= X[rs1]'s+imm;
83 114
             if(rd!=0) X[rd]<=sext(MEM[offs]);
84 115
         }
85 116
         LH {
86 117
             encoding: imm[11:0]s | rs1[4:0] | b001 | rd[4:0] | b0000011;
87
-            args_disass:"x%rd$d, %imm%(x%rs1$d)";
118
+            args_disass:"{name(rd)}, {imm}({name(rs1)})";
88 119
             val offs[XLEN] <= X[rs1]'s+imm;
89 120
             if(rd!=0) X[rd]<=sext(MEM[offs]{16});            
90 121
         }
91 122
         LW {
92 123
             encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011;
93
-            args_disass:"x%rd$d, %imm%(x%rs1$d)";
124
+            args_disass:"{name(rd)}, {imm}({name(rs1)})";
94 125
             val offs[XLEN] <= X[rs1]'s+imm;
95 126
             if(rd!=0) X[rd]<=sext(MEM[offs]{32});
96 127
         }
97 128
         LBU {
98 129
             encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0000011;
99
-            args_disass:"x%rd$d, %imm%(x%rs1$d)";
130
+            args_disass:"{name(rd)}, {imm}({name(rs1)})";
100 131
             val offs[XLEN] <= X[rs1]'s+imm;
101 132
             if(rd!=0) X[rd]<=zext(MEM[offs]);
102 133
         }
103 134
         LHU {
104 135
             encoding: imm[11:0]s | rs1[4:0] | b101 | rd[4:0] | b0000011;
105
-            args_disass:"x%rd$d, %imm%(x%rs1$d)";
136
+            args_disass:"{name(rd)}, {imm}({name(rs1)})";
106 137
             val offs[XLEN] <= X[rs1]'s+imm;
107 138
             if(rd!=0) X[rd]<=zext(MEM[offs]{16});            
108 139
         }
109 140
         SB {
110 141
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:0]s | b0100011;
111
-            args_disass:"x%rs2$d, %imm%(x%rs1$d)";
142
+            args_disass:"{name(rs2)}, {imm}({name(rs1)})";
112 143
             val offs[XLEN] <= X[rs1]'s + imm;
113 144
             MEM[offs] <= X[rs2];
114 145
         }
115 146
         SH {
116 147
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:0]s | b0100011;
117
-            args_disass:"x%rs2$d, %imm%(x%rs1$d)";
148
+            args_disass:"{name(rs2)}, {imm}({name(rs1)})";
118 149
             val offs[XLEN] <= X[rs1]'s + imm;
119 150
             MEM[offs]{16} <= X[rs2];
120 151
         }
121 152
         SW {
122 153
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100011;
123
-            args_disass:"x%rs2$d, %imm%(x%rs1$d)";
154
+            args_disass:"{name(rs2)}, {imm}({name(rs1)})";
124 155
             val offs[XLEN] <= X[rs1]'s + imm;
125 156
             MEM[offs]{32} <= X[rs2];
126 157
         }
127 158
         ADDI {
128 159
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0010011;
129
-            args_disass:"x%rd$d, x%rs1$d, %imm%";
160
+            args_disass:"{name(rd)}, {name(rs1)}, {imm}";
130 161
             if(rd != 0) X[rd] <= X[rs1]'s + imm;
131 162
         }
132 163
         SLTI {
133 164
             encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0010011;
134
-            args_disass:"x%rd$d, x%rs1$d, %imm%";
165
+            args_disass:"{name(rd)}, {name(rs1)}, {imm}";
135 166
             if (rd != 0) X[rd] <= choose(X[rs1]s < imm's, 1, 0);
136 167
         }
137 168
         SLTIU {
138 169
             encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0010011;
139
-            args_disass:"x%rd$d, x%rs1$d, %imm%";
170
+            args_disass:"{name(rd)}, {name(rs1)}, {imm}";
140 171
             val full_imm[XLEN] <= imm's;
141 172
             if (rd != 0) X[rd] <= choose(X[rs1]'u < full_imm'u, 1, 0);
142 173
         }
143 174
         XORI {
144 175
             encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0010011;
145
-            args_disass:"x%rd$d, x%rs1$d, %imm%";
176
+            args_disass:"{name(rd)}, {name(rs1)}, {imm}";
146 177
             if(rd != 0) X[rd] <= X[rs1]s ^ imm;
147 178
         }
148 179
         ORI {
149 180
             encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0010011;
150
-            args_disass:"x%rd$d, x%rs1$d, %imm%";
181
+            args_disass:"{name(rd)}, {name(rs1)}, {imm}";
151 182
             if(rd != 0) X[rd] <= X[rs1]s | imm;
152 183
         }
153 184
         ANDI {
154 185
             encoding: imm[11:0]s | rs1[4:0] | b111 | rd[4:0] | b0010011;
155
-            args_disass:"x%rd$d, x%rs1$d, %imm%";
186
+            args_disass:"{name(rd)}, {name(rs1)}, {imm}";
156 187
             if(rd != 0) X[rd] <= X[rs1]s & imm;
157 188
         }
158 189
         SLLI {
159 190
             encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
160
-            args_disass:"x%rd$d, x%rs1$d, %shamt%";
191
+            args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
161 192
             if(shamt > 31){
162 193
                 raise(0,0);
163 194
             } else {
@@ -166,7 +197,7 @@ InsructionSet RV32IBase {
166 197
         }
167 198
         SRLI {
168 199
             encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
169
-            args_disass:"x%rd$d, x%rs1$d, %shamt%";
200
+            args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
170 201
             if(shamt > 31){
171 202
                 raise(0,0);
172 203
             } else {
@@ -175,7 +206,7 @@ InsructionSet RV32IBase {
175 206
         }
176 207
         SRAI {
177 208
             encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
178
-            args_disass:"x%rd$d, x%rs1$d, %shamt%";
209
+            args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
179 210
             if(shamt > 31){
180 211
                 raise(0,0);
181 212
             } else {
@@ -184,52 +215,52 @@ InsructionSet RV32IBase {
184 215
         }
185 216
         ADD {
186 217
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
187
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
218
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
188 219
             if(rd != 0) X[rd] <= X[rs1] + X[rs2];
189 220
         }
190 221
         SUB {
191 222
             encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
192
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
223
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
193 224
             if(rd != 0) X[rd] <= X[rs1] - X[rs2];
194 225
         }
195 226
         SLL {
196 227
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
197
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
228
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
198 229
             if(rd != 0) X[rd] <= shll(X[rs1], X[rs2]&(XLEN-1));
199 230
         }
200 231
         SLT {
201 232
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
202
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
233
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
203 234
             if (rd != 0) X[rd] <= choose(X[rs1]s < X[rs2]s, 1, 0);
204 235
         }
205 236
         SLTU {
206 237
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
207
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
238
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
208 239
             if (rd != 0) X[rd] <= choose(zext(X[rs1]) < zext(X[rs2]), 1, 0);
209 240
         }
210 241
         XOR {
211 242
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011;
212
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
243
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
213 244
             if(rd != 0) X[rd] <= X[rs1] ^ X[rs2];
214 245
         }
215 246
         SRL {
216 247
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
217
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
248
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
218 249
             if(rd != 0) X[rd] <= shrl(X[rs1], X[rs2]&(XLEN-1));
219 250
         }
220 251
         SRA {
221 252
             encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
222
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
253
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
223 254
             if(rd != 0) X[rd] <= shra(X[rs1], X[rs2]&(XLEN-1));
224 255
         }
225 256
         OR {
226 257
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
227
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
258
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
228 259
             if(rd != 0) X[rd] <= X[rs1] | X[rs2];
229 260
         }
230 261
         AND {
231 262
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011;
232
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
263
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
233 264
             if(rd != 0) X[rd] <= X[rs1] & X[rs2];
234 265
         }
235 266
         FENCE {
@@ -271,7 +302,7 @@ InsructionSet RV32IBase {
271 302
         }
272 303
         CSRRW {
273 304
             encoding: csr[11:0] | rs1[4:0] | b001 | rd[4:0] | b1110011;
274
-            args_disass:"x%rd$d, %csr$d, x%rs1$d";
305
+            args_disass:"{name(rd)}, {csr}, {name(rs1)}";
275 306
             val rs_val[XLEN] <= X[rs1];
276 307
             if(rd!=0){
277 308
                 val csr_val[XLEN] <= CSR[csr];
@@ -284,7 +315,7 @@ InsructionSet RV32IBase {
284 315
         }
285 316
         CSRRS {
286 317
             encoding: csr[11:0] | rs1[4:0] | b010 | rd[4:0] | b1110011;
287
-            args_disass:"x%rd$d, %csr$d, x%rs1$d";
318
+            args_disass:"{name(rd)}, {csr}, {name(rs1)}";
288 319
             val xrd[XLEN] <= CSR[csr];
289 320
             val xrs1[XLEN] <= X[rs1];
290 321
             if(rd!=0) X[rd] <= xrd;
@@ -292,7 +323,7 @@ InsructionSet RV32IBase {
292 323
         }
293 324
         CSRRC {
294 325
             encoding: csr[11:0] | rs1[4:0] | b011 | rd[4:0] | b1110011;
295
-            args_disass:"x%rd$d, %csr$d, x%rs1$d";
326
+            args_disass:"{name(rd)}, {csr}, {name(rs1)}";
296 327
             val xrd[XLEN] <= CSR[csr];
297 328
             val xrs1[XLEN] <= X[rs1];
298 329
             if(rd!=0) X[rd] <= xrd;
@@ -300,13 +331,13 @@ InsructionSet RV32IBase {
300 331
         }
301 332
         CSRRWI {
302 333
             encoding: csr[11:0] | zimm[4:0] | b101 | rd[4:0] | b1110011;
303
-            args_disass:"x%rd$d, %csr$d, 0x%zimm$x";
334
+            args_disass:"{name(rd)}, {csr}, {zimm:#0x}";
304 335
             if(rd!=0) X[rd] <= CSR[csr];
305 336
             CSR[csr] <= zext(zimm);    
306 337
         }
307 338
         CSRRSI {
308 339
             encoding: csr[11:0] | zimm[4:0] | b110 | rd[4:0] | b1110011;
309
-            args_disass:"x%rd$d, %csr$d, 0x%zimm$x";
340
+            args_disass:"{name(rd)}, {csr}, {zimm:#0x}";
310 341
             val res[XLEN] <= CSR[csr];
311 342
             if(zimm!=0) CSR[csr] <= res | zext(zimm);
312 343
             // make sure rd is written after csr write succeeds    
@@ -314,7 +345,7 @@ InsructionSet RV32IBase {
314 345
         }
315 346
         CSRRCI {
316 347
             encoding: csr[11:0] | zimm[4:0] | b111 | rd[4:0] | b1110011;
317
-            args_disass:"x%rd$d, %csr$d, 0x%zimm$x";
348
+            args_disass:"{name(rd)}, {csr}, {zimm:#0x}";
318 349
             val res[XLEN] <= CSR[csr];
319 350
             if(rd!=0) X[rd] <= res;
320 351
             if(zimm!=0) CSR[csr] <= res & ~zext(zimm, XLEN);    

+ 8
- 8
riscv/gen_input/RV32M.core_desc View File

@@ -7,7 +7,7 @@ InsructionSet RV32M extends RV32IBase {
7 7
     instructions{       
8 8
         MUL{
9 9
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
10
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
10
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
11 11
             if(rd != 0){
12 12
                 val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
13 13
                 X[rd]<= zext(res , XLEN);
@@ -15,7 +15,7 @@ InsructionSet RV32M extends RV32IBase {
15 15
         }
16 16
         MULH {
17 17
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
18
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
18
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
19 19
             if(rd != 0){
20 20
                 val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN);
21 21
                 X[rd]<= zext(res >> XLEN, XLEN);
@@ -23,7 +23,7 @@ InsructionSet RV32M extends RV32IBase {
23 23
         }
24 24
         MULHSU {
25 25
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
26
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
26
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
27 27
             if(rd != 0){
28 28
                 val res[MAXLEN] <= sext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
29 29
                 X[rd]<= zext(res >> XLEN, XLEN);
@@ -31,7 +31,7 @@ InsructionSet RV32M extends RV32IBase {
31 31
         }
32 32
         MULHU {
33 33
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
34
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
34
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
35 35
             if(rd != 0){
36 36
                 val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
37 37
                 X[rd]<= zext(res >> XLEN, XLEN);
@@ -39,7 +39,7 @@ InsructionSet RV32M extends RV32IBase {
39 39
         }
40 40
         DIV {
41 41
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011;
42
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
42
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
43 43
             if(rd != 0){
44 44
                 if(X[rs2]!=0){
45 45
                     val M1[XLEN] <= -1;
@@ -57,7 +57,7 @@ InsructionSet RV32M extends RV32IBase {
57 57
         }
58 58
         DIVU {
59 59
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011;
60
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
60
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
61 61
             if(rd != 0){
62 62
                 if(X[rs2]!=0)
63 63
                     X[rd] <= zext(X[rs1], 32) / zext(X[rs2], 32);
@@ -67,7 +67,7 @@ InsructionSet RV32M extends RV32IBase {
67 67
         }
68 68
         REM {
69 69
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
70
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
70
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
71 71
             if(rd != 0){
72 72
                 if(X[rs2]!=0) {
73 73
                     val M1[XLEN] <= -1;
@@ -85,7 +85,7 @@ InsructionSet RV32M extends RV32IBase {
85 85
         }
86 86
         REMU {
87 87
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011;
88
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
88
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
89 89
             if(rd != 0){
90 90
                 if(X[rs2]!=0)
91 91
                     X[rd] <= zext(X[rs1], 32) % zext(X[rs2], 32);

+ 11
- 11
riscv/gen_input/RV64A.core_desc View File

@@ -10,7 +10,7 @@ InsructionSet RV64A extends RV64IBase {
10 10
     instructions{
11 11
         LR.D {
12 12
             encoding: b00010 | aq[0:0] | rl[0:0]  | b00000 | rs1[4:0] | b011 | rd[4:0] | b0101111;
13
-            args_disass: "x%rd$d, x%rs1$d";
13
+            args_disass: "{name(rd)}, {name(rs1)}";
14 14
             if(rd!=0){
15 15
                 val offs[XLEN] <= X[rs1];
16 16
                 X[rd]<= sext(MEM[offs]{64}, XLEN);
@@ -19,7 +19,7 @@ InsructionSet RV64A extends RV64IBase {
19 19
         }
20 20
         SC.D {
21 21
             encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
22
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d";
22
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)}";
23 23
             val offs[XLEN] <= X[rs1];
24 24
             val res[64] <= RES[offs];
25 25
             if(res!=0){
@@ -31,14 +31,14 @@ InsructionSet RV64A extends RV64IBase {
31 31
         }
32 32
         AMOSWAP.D{
33 33
             encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
34
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
34
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
35 35
             val offs[XLEN] <= X[rs1];
36 36
             if(rd!=0) X[rd] <= sext(MEM[offs]{64});
37 37
             MEM[offs]{64} <= X[rs2];            
38 38
         }
39 39
         AMOADD.D{
40 40
             encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
41
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
41
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
42 42
             val offs[XLEN] <= X[rs1];
43 43
             val res[XLEN] <= sext(MEM[offs]{64});
44 44
             if(rd!=0) X[rd]<=res;
@@ -47,7 +47,7 @@ InsructionSet RV64A extends RV64IBase {
47 47
         }
48 48
         AMOXOR.D{
49 49
             encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
50
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
50
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
51 51
             val offs[XLEN] <= X[rs1];
52 52
             val res[XLEN] <= sext(MEM[offs]{64});
53 53
             if(rd!=0) X[rd] <= res;
@@ -56,7 +56,7 @@ InsructionSet RV64A extends RV64IBase {
56 56
         }
57 57
         AMOAND.D{
58 58
             encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
59
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
59
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
60 60
             val offs[XLEN] <= X[rs1];
61 61
             val res[XLEN] <= sext(MEM[offs]{64});
62 62
             if(rd!=0) X[rd] <= res;
@@ -65,7 +65,7 @@ InsructionSet RV64A extends RV64IBase {
65 65
         }
66 66
         AMOOR.D {
67 67
             encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
68
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
68
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
69 69
             val offs[XLEN] <= X[rs1];
70 70
             val res[XLEN] <= sext(MEM[offs]{64});
71 71
             if(rd!=0) X[rd] <= res;
@@ -74,7 +74,7 @@ InsructionSet RV64A extends RV64IBase {
74 74
         }
75 75
         AMOMIN.D{
76 76
             encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
77
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
77
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
78 78
             val offs[XLEN] <= X[rs1];
79 79
             val res[XLEN] <= sext(MEM[offs]{64});
80 80
             if(rd!=0) X[rd] <= res;
@@ -83,7 +83,7 @@ InsructionSet RV64A extends RV64IBase {
83 83
         }
84 84
         AMOMAX.D{
85 85
             encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
86
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
86
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
87 87
             val offs[XLEN] <= X[rs1];
88 88
             val res[XLEN] <= sext(MEM[offs]{64});
89 89
             if(rd!=0) X[rd] <= res;
@@ -92,7 +92,7 @@ InsructionSet RV64A extends RV64IBase {
92 92
         }
93 93
         AMOMINU.D{
94 94
             encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
95
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
95
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
96 96
             val offs[XLEN] <= X[rs1];
97 97
             val res[XLEN] <= zext(MEM[offs]{64});
98 98
             if(rd!=0) X[rd] <= res;
@@ -101,7 +101,7 @@ InsructionSet RV64A extends RV64IBase {
101 101
         }
102 102
         AMOMAXU.D{
103 103
             encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111;
104
-            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)";
104
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
105 105
             val offs[XLEN] <= X[rs1];
106 106
             val res[XLEN] <= zext(MEM[offs]{64});
107 107
             if(rd!=0) X[rd] <= res;

+ 13
- 13
riscv/gen_input/RV64IBase.core_desc View File

@@ -4,40 +4,40 @@ InsructionSet RV64IBase extends RV32IBase {
4 4
     instructions{
5 5
         LWU { //    80000104: 0000ef03            lwu t5,0(ra)
6 6
             encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0000011;
7
-            args_disass:"x%rd$d, %imm%(x%rs1$d)";
7
+            args_disass:"{name(rd)}, {imm}({name(rs1)})";
8 8
             val offs[XLEN] <= X[rs1]'s+imm;
9 9
             if(rd!=0) X[rd]<=zext(MEM[offs]{32});
10 10
         }
11 11
         LD{
12 12
             encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000011;
13
-            args_disass:"x%rd$d, %imm%(x%rs1$d)";
13
+            args_disass:"{name(rd)}, {imm}({name(rs1)})";
14 14
             val offs[XLEN] <= X[rs1]'s + imm;
15 15
             if(rd!=0) X[rd]<=sext(MEM[offs]{64});
16 16
         }
17 17
         SD{
18 18
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100011;
19
-            args_disass:"x%rs2$d, %imm%(x%rs1$d)";
19
+            args_disass:"{name(rs2)}, {imm}({name(rs1)})";
20 20
             val offs[XLEN] <= X[rs1]'s + imm;
21 21
             MEM[offs]{64} <= X[rs2];
22 22
         }
23 23
         SLLI {
24 24
             encoding: b000000 | shamt[5:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
25
-            args_disass:"x%rd$d, x%rs1$d, %shamt%";
25
+            args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
26 26
             if(rd != 0) X[rd] <= shll(X[rs1], shamt);
27 27
         }
28 28
         SRLI {
29 29
             encoding: b000000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
30
-            args_disass:"x%rd$d, x%rs1$d, %shamt%";
30
+            args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
31 31
             if(rd != 0) X[rd] <= shrl(X[rs1], shamt);
32 32
         }
33 33
         SRAI {
34 34
             encoding: b010000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
35
-            args_disass:"x%rd$d, x%rs1$d, %shamt%";
35
+            args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
36 36
             if(rd != 0) X[rd] <= shra(X[rs1], shamt);
37 37
         }
38 38
         ADDIW {
39 39
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0011011;
40
-            args_disass:"x%rd$d, x%rs1$d, %imm%";
40
+            args_disass:"{name(rd)}, {name(rs1)}, {imm}";
41 41
             if(rd != 0){
42 42
                 val res[32] <= X[rs1]{32}'s + imm;
43 43
                 X[rd] <= sext(res);
@@ -45,7 +45,7 @@ InsructionSet RV64IBase extends RV32IBase {
45 45
         }
46 46
         SLLIW {
47 47
             encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0011011;
48
-            args_disass:"x%rd$d, x%rs1$d, %shamt%";
48
+            args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
49 49
             if(rd != 0){
50 50
                 val sh_val[32] <= shll(X[rs1]{32}, shamt);
51 51
                 X[rd] <= sext(sh_val);
@@ -53,7 +53,7 @@ InsructionSet RV64IBase extends RV32IBase {
53 53
         }
54 54
         SRLIW {
55 55
             encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011;
56
-            args_disass:"x%rd$d, x%rs1$d, %shamt%";
56
+            args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
57 57
             if(rd != 0){
58 58
                 val sh_val[32] <= shrl(X[rs1]{32}, shamt);
59 59
                 X[rd] <= sext(sh_val);
@@ -61,7 +61,7 @@ InsructionSet RV64IBase extends RV32IBase {
61 61
         }
62 62
         SRAIW {
63 63
             encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011;
64
-            args_disass:"x%rd$d, x%rs1$d, %shamt%";
64
+            args_disass:"{name(rd)}, {name(rs1)}, {shamt}";
65 65
             if(rd != 0){
66 66
                 val sh_val[32] <= shra(X[rs1]{32}, shamt);    
67 67
                 X[rd] <= sext(sh_val);
@@ -83,7 +83,7 @@ InsructionSet RV64IBase extends RV32IBase {
83 83
         }
84 84
         SLLW {
85 85
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0111011;
86
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
86
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
87 87
             if(rd != 0){
88 88
                 val mask[32] <= 0x1f;
89 89
                 val count[32] <= X[rs2]{32} & mask;
@@ -93,7 +93,7 @@ InsructionSet RV64IBase extends RV32IBase {
93 93
         }
94 94
         SRLW {
95 95
             encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
96
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
96
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
97 97
             if(rd != 0){
98 98
                 val mask[32] <= 0x1f;
99 99
                 val count[32] <= X[rs2]{32} & mask;
@@ -103,7 +103,7 @@ InsructionSet RV64IBase extends RV32IBase {
103 103
         }
104 104
         SRAW {
105 105
             encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
106
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
106
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
107 107
             if(rd != 0){
108 108
                 val mask[32] <= 0x1f;
109 109
                 val count[32] <= X[rs2]{32} & mask;

+ 5
- 5
riscv/gen_input/RV64M.core_desc View File

@@ -4,35 +4,35 @@ InsructionSet RV64M extends RV64IBase {
4 4
     instructions{       
5 5
         MULW{
6 6
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
7
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
7
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
8 8
             if(rd != 0){
9 9
                 X[rd]<= X[rs1] * X[rs2];
10 10
             }
11 11
         }
12 12
         DIVW {
13 13
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0111011;
14
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
14
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
15 15
             if(rd != 0){
16 16
                 X[rd] <= X[rs1]s / X[rs2]s;
17 17
             }
18 18
         }
19 19
         DIVUW {
20 20
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
21
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
21
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
22 22
             if(rd != 0){
23 23
                 X[rd] <= X[rs1] / X[rs2];
24 24
             }
25 25
         }
26 26
         REMW {
27 27
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0111011;
28
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
28
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
29 29
             if(rd != 0){
30 30
                 X[rd] <= X[rs1]s % X[rs2]s;
31 31
             }
32 32
         }
33 33
         REMUW {
34 34
             encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0111011;
35
-            args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
35
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
36 36
             if(rd != 0){
37 37
                 X[rd] <= X[rs1] % X[rs2];
38 38
             }

+ 50
- 8
riscv/gen_input/templates/incl-CORENAME.h.gtl View File

@@ -33,9 +33,44 @@
33 33
 <% 
34 34
 import com.minres.coredsl.coreDsl.Register
35 35
 import com.minres.coredsl.coreDsl.RegisterFile
36
+import com.minres.coredsl.coreDsl.RegisterAlias
36 37
 def getTypeSize(size){
37 38
 	if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
38 39
 }
40
+def getOriginalName(reg){
41
+    if( reg.original instanceof RegisterFile) {
42
+    	if( reg.index != null ) {
43
+        	return reg.original.name+generator.generateHostCode(reg.index)
44
+        } else {
45
+        	return reg.original.name
46
+        }
47
+    } else if(reg.original instanceof Register){
48
+        return reg.original.name
49
+    }
50
+}
51
+def getRegisterNames(){
52
+	def regNames = []
53
+ 	allRegs.each { reg -> 
54
+		if( reg instanceof RegisterFile) {
55
+			(reg.range.right..reg.range.left).each{
56
+    			regNames+=reg.name.toLowerCase()+it
57
+            }
58
+        } else if(reg instanceof Register){
59
+    		regNames+=reg.name.toLowerCase()
60
+        }
61
+    }
62
+    return regNames
63
+}
64
+def getRegisterAliasNames(){
65
+	def regMap = allRegs.findAll{it instanceof RegisterAlias }.collectEntries {[getOriginalName(it), it.name]}
66
+ 	return allRegs.findAll{it instanceof Register || it instanceof RegisterFile}.collect{reg ->
67
+		if( reg instanceof RegisterFile) {
68
+			return (reg.range.right..reg.range.left).collect{ (regMap[reg.name]?:regMap[reg.name+it]?:reg.name.toLowerCase()+it).toLowerCase() }
69
+        } else if(reg instanceof Register){
70
+    		regMap[reg.name]?:reg.name.toLowerCase()
71
+        }
72
+ 	}.flatten()
73
+}
39 74
 %>
40 75
 #ifndef _${coreDef.name.toUpperCase()}_H_
41 76
 #define _${coreDef.name.toUpperCase()}_H_
@@ -54,6 +89,12 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
54 89
 
55 90
 	constexpr static char const* const core_type = "${coreDef.name}";
56 91
     
92
+  	static constexpr std::array<const char*, ${getRegisterNames().size}> reg_names{
93
+ 		{"${getRegisterNames().join("\", \"")}"}};
94
+ 
95
+  	static constexpr std::array<const char*, ${getRegisterAliasNames().size}> reg_aliases{
96
+ 		{"${getRegisterAliasNames().join("\", \"")}"}};
97
+
57 98
     enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
58 99
 
59 100
     constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
@@ -65,7 +106,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
65 106
         ${reg.name}${it},<%
66 107
                 }
67 108
             } else if(reg instanceof Register){ %>
68
-        ${reg.name},<%
109
+        ${reg.name},<%  
69 110
             }
70 111
         }%>
71 112
         NUM_REGS,
@@ -74,7 +115,12 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
74 115
         PENDING_TRAP,
75 116
         MACHINE_STATE,
76 117
         LAST_BRANCH,
77
-        ICOUNT
118
+        ICOUNT<% 
119
+     	allRegs.each { reg -> 
120
+    		if(reg instanceof RegisterAlias){ def aliasname=getOriginalName(reg)%>,
121
+        ${reg.name} = ${aliasname}<%
122
+            }
123
+        }%>
78 124
     };
79 125
 
80 126
     using reg_t = uint${regDataWidth}_t;
@@ -87,16 +133,12 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
87 133
 
88 134
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
89 135
 
90
- 	static constexpr std::array<const uint32_t, ${regSizes.size}> ${coreDef.name}_reg_size{
136
+ 	static constexpr std::array<const uint32_t, ${regSizes.size}> reg_bit_widths{
91 137
  		{${regSizes.join(",")}}};
92 138
 
93
-    static constexpr unsigned reg_bit_width(unsigned r) { return ${coreDef.name}_reg_size[r]; }
94
-
95
-    static constexpr std::array<const uint32_t, ${regOffsets.size}> ${coreDef.name}_reg_byte_offset{
139
+    static constexpr std::array<const uint32_t, ${regOffsets.size}> reg_byte_offsets{
96 140
     	{${regOffsets.join(",")}}};
97 141
 
98
-    constexpr static unsigned reg_byte_offset(unsigned r) { return ${coreDef.name}_reg_byte_offset[r]; }
99
-
100 142
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
101 143
 
102 144
     enum sreg_flag_e { FLAGS };

+ 2
- 2
riscv/gen_input/templates/src-CORENAME.cpp.gtl View File

@@ -49,8 +49,8 @@ extern "C" {
49 49
 
50 50
 using namespace iss::arch;
51 51
 
52
-constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::${coreDef.name}_reg_size;
53
-constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::${coreDef.name}_reg_byte_offset;
52
+constexpr std::array<const uint32_t, 39> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_sizes;
53
+constexpr std::array<const uint32_t, 40> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offset;
54 54
 
55 55
 ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() {
56 56
     reg.icount = 0;

+ 41
- 46
riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl View File

@@ -38,7 +38,7 @@
38 38
 #include <iss/llvm/vm_base.h>
39 39
 #include <util/logging.h>
40 40
 
41
-#include <boost/format.hpp>
41
+#include <fmt/format.h>
42 42
 
43 43
 #include <array>
44 44
 #include <iss/debugger/riscv_target_adapter.h>
@@ -54,10 +54,11 @@ namespace ${coreDef.name.toLowerCase()} {
54 54
 using namespace iss::arch;
55 55
 using namespace llvm;
56 56
 using namespace iss::debugger;
57
+using namespace iss::vm::llvm;
57 58
 
58
-template <typename ARCH> class vm_impl : public vm::vm_base<ARCH> {
59
+template <typename ARCH> class vm_impl : public vm_base<ARCH> {
59 60
 public:
60
-    using super = typename vm::vm_base<ARCH>;
61
+    using super = typename iss::vm::llvm::vm_base<ARCH>;
61 62
     using virt_addr_t = typename super::virt_addr_t;
62 63
     using phys_addr_t = typename super::phys_addr_t;
63 64
     using code_word_t = typename super::code_word_t;
@@ -71,31 +72,32 @@ public:
71 72
 
72 73
     target_adapter_if *accquire_target_adapter(server_if *srv) override {
73 74
         debugger_if::dbg_enabled = true;
74
-        if (vm::vm_base<ARCH>::tgt_adapter == nullptr)
75
-            vm::vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
76
-        return vm::vm_base<ARCH>::tgt_adapter;
75
+        if (vm_base<ARCH>::tgt_adapter == nullptr)
76
+            vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
77
+        return vm_base<ARCH>::tgt_adapter;
77 78
     }
78 79
 
79 80
 protected:
80
-    using vm::vm_base<ARCH>::get_reg_ptr;
81
+    using vm_base<ARCH>::get_reg_ptr;
81 82
 
82
-    template <typename T> inline llvm::ConstantInt *size(T type) {
83
-        return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
83
+    inline const char *name(size_t index){return traits<ARCH>::reg_aliases.at(index);}
84
+
85
+    template <typename T> inline ConstantInt *size(T type) {
86
+        return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
84 87
     }
85 88
 
86
-    void setup_module(llvm::Module *m) override {
89
+    void setup_module(Module* m) override {
87 90
         super::setup_module(m);
88
-        vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE);
91
+        iss::vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE);
89 92
     }
90 93
 
91
-    inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal, unsigned size) {
94
+    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
92 95
         return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
93 96
     }
94 97
 
95
-    std::tuple<vm::continuation_e, llvm::BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &,
96
-                                                                                llvm::BasicBlock *) override;
98
+    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
97 99
 
98
-    void gen_leave_behavior(llvm::BasicBlock *leave_blk) override;
100
+    void gen_leave_behavior(BasicBlock *leave_blk) override;
99 101
 
100 102
     void gen_raise_trap(uint16_t trap_id, uint16_t cause);
101 103
 
@@ -103,17 +105,17 @@ protected:
103 105
 
104 106
     void gen_wait(unsigned type);
105 107
 
106
-    void gen_trap_behavior(llvm::BasicBlock *) override;
108
+    void gen_trap_behavior(BasicBlock *) override;
107 109
 
108
-    void gen_trap_check(llvm::BasicBlock *bb);
110
+    void gen_trap_check(BasicBlock *bb);
109 111
 
110
-    inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) {
112
+    inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
111 113
         return this->builder.CreateLoad(get_reg_ptr(i), false);
112 114
     }
113 115
 
114 116
     inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
115
-        llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
116
-                                                                 this->get_type(traits<ARCH>::XLEN));
117
+        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
118
+                                                           this->get_type(traits<ARCH>::XLEN));
117 119
         this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
118 120
     }
119 121
 
@@ -124,9 +126,9 @@ protected:
124 126
     enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
125 127
 
126 128
     using this_class = vm_impl<ARCH>;
127
-    using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock *> (this_class::*)(virt_addr_t &pc,
128
-                                                                                            code_word_t instr,
129
-                                                                                            llvm::BasicBlock *bb);
129
+    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
130
+                                                                                  code_word_t instr,
131
+                                                                                  BasicBlock *bb);
130 132
     std::array<compile_func, LUT_SIZE> lut;
131 133
 
132 134
     std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
@@ -192,15 +194,14 @@ private:
192 194
  
193 195
     /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
194 196
     /* instruction ${idx}: ${instr.name} */
195
-    std::tuple<vm::continuation_e, llvm::BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){<%instr.code.eachLine{%>
197
+    std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){<%instr.code.eachLine{%>
196 198
     	${it}<%}%>
197 199
     }
198 200
     <%}%>
199 201
     /****************************************************************************
200 202
      * end opcode definitions
201 203
      ****************************************************************************/
202
-    std::tuple<vm::continuation_e, llvm::BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr,
203
-                                                                          llvm::BasicBlock *bb) {
204
+    std::tuple<continuation_e, BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
204 205
 		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
205 206
         this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
206 207
                                    get_reg_ptr(traits<ARCH>::PC), true);
@@ -212,7 +213,7 @@ private:
212 213
         this->gen_raise_trap(0, 2);     // illegal instruction trap
213 214
 		this->gen_sync(iss::POST_SYNC, instr_descr.size());
214 215
         this->gen_trap_check(this->leave_blk);
215
-        return std::make_tuple(iss::vm::BRANCH, nullptr);
216
+        return std::make_tuple(BRANCH, nullptr);
216 217
     }
217 218
 };
218 219
 
@@ -225,7 +226,7 @@ template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
225 226
 
226 227
 template <typename ARCH>
227 228
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
228
-: vm::vm_base<ARCH>(core, core_id, cluster_id) {
229
+: vm_base<ARCH>(core, core_id, cluster_id) {
229 230
     qlut[0] = lut_00.data();
230 231
     qlut[1] = lut_01.data();
231 232
     qlut[2] = lut_10.data();
@@ -237,8 +238,8 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
237 238
 }
238 239
 
239 240
 template <typename ARCH>
240
-std::tuple<vm::continuation_e, llvm::BasicBlock *>
241
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, llvm::BasicBlock *this_block) {
241
+std::tuple<continuation_e, BasicBlock *>
242
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
242 243
     // we fetch at max 4 byte, alignment is 2
243 244
     code_word_t insn = 0;
244 245
     const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
@@ -270,7 +271,7 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
270 271
     return (this->*f)(pc, insn, this_block);
271 272
 }
272 273
 
273
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock *leave_blk) {
274
+template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
274 275
     this->builder.SetInsertPoint(leave_blk);
275 276
     this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
276 277
 }
@@ -278,45 +279,39 @@ template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock
278 279
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
279 280
     auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
280 281
     this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
281
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
282
-    						  get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
282
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
283 283
 }
284 284
 
285 285
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
286
-    std::vector<llvm::Value *> args{
287
-        this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)),
288
-    };
286
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
289 287
     this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
290 288
     auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
291 289
     this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
292
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
293
-                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
290
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
294 291
 }
295 292
 
296 293
 template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
297
-    std::vector<llvm::Value *> args{
298
-        this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)),
299
-    };
294
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
300 295
     this->builder.CreateCall(this->mod->getFunction("wait"), args);
301 296
 }
302 297
 
303
-template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(llvm::BasicBlock *trap_blk) {
298
+template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
304 299
     this->builder.SetInsertPoint(trap_blk);
305 300
     auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
306 301
     this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
307 302
                               get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
308
-    std::vector<llvm::Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
309
-                                    this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
303
+    std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
304
+                              this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
310 305
     this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
311 306
     auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
312 307
     this->builder.CreateRet(trap_addr_val);
313 308
 }
314 309
 
315
-template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBlock *bb) {
310
+template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
316 311
     auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
317 312
     this->gen_cond_branch(this->builder.CreateICmp(
318 313
                               ICmpInst::ICMP_EQ, v,
319
-                              llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))),
314
+                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
320 315
                           bb, this->trap_blk, 1);
321 316
 }
322 317
 

+ 0
- 322
riscv/gen_input/templates/vm_riscv.in.cpp View File

@@ -1,322 +0,0 @@
1
-/*******************************************************************************
2
- * Copyright (C) 2017, 2018 MINRES Technologies GmbH
3
- * All rights reserved.
4
- *
5
- * Redistribution and use in source and binary forms, with or without
6
- * modification, are permitted provided that the following conditions are met:
7
- *
8
- * 1. Redistributions of source code must retain the above copyright notice,
9
- *    this list of conditions and the following disclaimer.
10
- *
11
- * 2. Redistributions in binary form must reproduce the above copyright notice,
12
- *    this list of conditions and the following disclaimer in the documentation
13
- *    and/or other materials provided with the distribution.
14
- *
15
- * 3. Neither the name of the copyright holder nor the names of its contributors
16
- *    may be used to endorse or promote products derived from this software
17
- *    without specific prior written permission.
18
- *
19
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
- * POSSIBILITY OF SUCH DAMAGE.
30
- *
31
- *******************************************************************************/
32
-
33
-#include <iss/arch/CORE_DEF_NAME.h>
34
-#include <iss/arch/riscv_hart_msu_vp.h>
35
-#include <iss/debugger/gdb_session.h>
36
-#include <iss/debugger/server.h>
37
-#include <iss/iss.h>
38
-#include <iss/llvm/vm_base.h>
39
-#include <util/logging.h>
40
-
41
-#include <boost/format.hpp>
42
-
43
-#include <array>
44
-#include <iss/debugger/riscv_target_adapter.h>
45
-
46
-namespace iss {
47
-namespace vm {
48
-namespace fp_impl {
49
-void add_fp_functions_2_module(llvm::Module *, unsigned);
50
-}
51
-}
52
-
53
-namespace CORE_DEF_NAME {
54
-using namespace iss::arch;
55
-using namespace llvm;
56
-using namespace iss::debugger;
57
-
58
-template <typename ARCH> class vm_impl : public vm::vm_base<ARCH> {
59
-public:
60
-    using super = typename vm::vm_base<ARCH>;
61
-    using virt_addr_t = typename super::virt_addr_t;
62
-    using phys_addr_t = typename super::phys_addr_t;
63
-    using code_word_t = typename super::code_word_t;
64
-    using addr_t = typename super::addr_t;
65
-
66
-    vm_impl();
67
-
68
-    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
69
-
70
-    void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
71
-
72
-    target_adapter_if *accquire_target_adapter(server_if *srv) override {
73
-        debugger_if::dbg_enabled = true;
74
-        if (vm::vm_base<ARCH>::tgt_adapter == nullptr)
75
-            vm::vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
76
-        return vm::vm_base<ARCH>::tgt_adapter;
77
-    }
78
-
79
-protected:
80
-    using vm::vm_base<ARCH>::get_reg_ptr;
81
-
82
-    template <typename T> inline llvm::ConstantInt *size(T type) {
83
-        return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
84
-    }
85
-
86
-    void setup_module(llvm::Module *m) override {
87
-        super::setup_module(m);
88
-        vm::fp_impl::add_fp_functions_2_module(m, traits<ARCH>::FP_REGS_SIZE);
89
-    }
90
-
91
-    inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal, unsigned size) {
92
-        return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
93
-    }
94
-
95
-    std::tuple<vm::continuation_e, llvm::BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &,
96
-                                                                                llvm::BasicBlock *) override;
97
-
98
-    void gen_leave_behavior(llvm::BasicBlock *leave_blk) override;
99
-
100
-    void gen_raise_trap(uint16_t trap_id, uint16_t cause);
101
-
102
-    void gen_leave_trap(unsigned lvl);
103
-
104
-    void gen_wait(unsigned type);
105
-
106
-    void gen_trap_behavior(llvm::BasicBlock *) override;
107
-
108
-    void gen_trap_check(llvm::BasicBlock *bb);
109
-
110
-    inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) {
111
-        return this->builder.CreateLoad(get_reg_ptr(i), false);
112
-    }
113
-
114
-    inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
115
-        llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
116
-                                                                 this->get_type(traits<ARCH>::XLEN));
117
-        this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
118
-    }
119
-
120
-    // some compile time constants
121
-    // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
122
-    enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
123
-    enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
124
-    enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
125
-
126
-    using this_class = vm_impl<ARCH>;
127
-    using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock *> (this_class::*)(virt_addr_t &pc,
128
-                                                                                            code_word_t instr,
129
-                                                                                            llvm::BasicBlock *bb);
130
-    std::array<compile_func, LUT_SIZE> lut;
131
-
132
-    std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
133
-    std::array<compile_func, LUT_SIZE> lut_11;
134
-
135
-    std::array<compile_func *, 4> qlut;
136
-
137
-    std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
138
-
139
-    void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
140
-                         compile_func f) {
141
-        if (pos < 0) {
142
-            lut[idx] = f;
143
-        } else {
144
-            auto bitmask = 1UL << pos;
145
-            if ((mask & bitmask) == 0) {
146
-                expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
147
-            } else {
148
-                if ((valid & bitmask) == 0) {
149
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
150
-                    expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
151
-                } else {
152
-                    auto new_val = idx << 1;
153
-                    if ((value & bitmask) != 0) new_val++;
154
-                    expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
155
-                }
156
-            }
157
-        }
158
-    }
159
-
160
-    inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
161
-
162
-    uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
163
-        if (pos >= 0) {
164
-            auto bitmask = 1UL << pos;
165
-            if ((mask & bitmask) == 0) {
166
-                lut_val = extract_fields(pos - 1, val, mask, lut_val);
167
-            } else {
168
-                auto new_val = lut_val << 1;
169
-                if ((val & bitmask) != 0) new_val++;
170
-                lut_val = extract_fields(pos - 1, val, mask, new_val);
171
-            }
172
-        }
173
-        return lut_val;
174
-    }
175
-
176
-private:
177
-    /****************************************************************************
178
-     * start opcode definitions
179
-     ****************************************************************************/
180
-    struct InstructionDesriptor {
181
-        size_t length;
182
-        uint32_t value;
183
-        uint32_t mask;
184
-        compile_func op;
185
-    };
186
-
187
-    /* «start generated code» */
188
-    std::array<InstructionDesriptor, 0> instr_descr = {{}};
189
-    /* «end generated code»  */
190
-    /****************************************************************************
191
-     * end opcode definitions
192
-     ****************************************************************************/
193
-    std::tuple<vm::continuation_e, llvm::BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr,
194
-                                                                          llvm::BasicBlock *bb) {
195
-        this->gen_sync(iss::PRE_SYNC, instr_descr.size());
196
-        this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
197
-                                  get_reg_ptr(traits<ARCH>::PC), true);
198
-        this->builder.CreateStore(
199
-            this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
200
-                                    this->gen_const(64U, 1)),
201
-            get_reg_ptr(traits<ARCH>::ICOUNT), true);
202
-        pc = pc + ((instr & 3) == 3 ? 4 : 2);
203
-        this->gen_raise_trap(0, 2); // illegal instruction trap
204
-        this->gen_sync(iss::POST_SYNC, instr_descr.size());
205
-        this->gen_trap_check(this->leave_blk);
206
-        return std::make_tuple(iss::vm::BRANCH, nullptr);
207
-    }
208
-};
209
-
210
-template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
211
-    volatile CODE_WORD x = insn;
212
-    insn = 2 * x;
213
-}
214
-
215
-template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
216
-
217
-template <typename ARCH>
218
-vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
219
-: vm::vm_base<ARCH>(core, core_id, cluster_id) {
220
-    qlut[0] = lut_00.data();
221
-    qlut[1] = lut_01.data();
222
-    qlut[2] = lut_10.data();
223
-    qlut[3] = lut_11.data();
224
-    for (auto instr : instr_descr) {
225
-        auto quantrant = instr.value & 0x3;
226
-        expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
227
-    }
228
-}
229
-
230
-template <typename ARCH>
231
-std::tuple<vm::continuation_e, llvm::BasicBlock *>
232
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, llvm::BasicBlock *this_block) {
233
-    // we fetch at max 4 byte, alignment is 2
234
-    code_word_t insn = 0;
235
-    const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
236
-    phys_addr_t paddr(pc);
237
-    try {
238
-        auto *const data = (uint8_t *)&insn;
239
-        paddr = this->core.v2p(pc);
240
-        if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
241
-            auto res = this->core.read(paddr, 2, data);
242
-            if (res != iss::Ok) throw trap_access(1, pc.val);
243
-            if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
244
-                res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
245
-            }
246
-        } else {
247
-            auto res = this->core.read(paddr, 4, data);
248
-            if (res != iss::Ok) throw trap_access(1, pc.val);
249
-        }
250
-    } catch (trap_access &ta) {
251
-        throw trap_access(ta.id, pc.val);
252
-    }
253
-    if (insn == 0x0000006f || (insn & 0xffff) == 0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
254
-    // curr pc on stack
255
-    ++inst_cnt;
256
-    auto lut_val = extract_fields(insn);
257
-    auto f = qlut[insn & 0x3][lut_val];
258
-    if (f == nullptr) {
259
-        f = &this_class::illegal_intruction;
260
-    }
261
-    return (this->*f)(pc, insn, this_block);
262
-}
263
-
264
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock *leave_blk) {
265
-    this->builder.SetInsertPoint(leave_blk);
266
-    this->builder.CreateRet(this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
267
-}
268
-
269
-template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
270
-    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
271
-    this->builder.CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
272
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
273
-                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
274
-}
275
-
276
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
277
-    std::vector<llvm::Value *> args{
278
-        this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)),
279
-    };
280
-    this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
281
-    auto *PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl << 8) + 0x41, traits<ARCH>::XLEN / 8);
282
-    this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
283
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
284
-                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
285
-}
286
-
287
-template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
288
-    std::vector<llvm::Value *> args{
289
-        this->core_ptr, llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)),
290
-    };
291
-    this->builder.CreateCall(this->mod->getFunction("wait"), args);
292
-}
293
-
294
-template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(llvm::BasicBlock *trap_blk) {
295
-    this->builder.SetInsertPoint(trap_blk);
296
-    auto *trap_state_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
297
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
298
-                              get_reg_ptr(traits<ARCH>::LAST_BRANCH), false);
299
-    std::vector<llvm::Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
300
-                                    this->adj_to64(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))};
301
-    this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
302
-    auto *trap_addr_val = this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
303
-    this->builder.CreateRet(trap_addr_val);
304
-}
305
-
306
-template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBlock *bb) {
307
-    auto *v = this->builder.CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
308
-    this->gen_cond_branch(this->builder.CreateICmp(
309
-                              ICmpInst::ICMP_EQ, v,
310
-                              llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))),
311
-                          bb, this->trap_blk, 1);
312
-}
313
-
314
-} // namespace CORE_DEF_NAME
315
-
316
-template <> std::unique_ptr<vm_if> create<arch::CORE_DEF_NAME>(arch::CORE_DEF_NAME *core, unsigned short port, bool dump) {
317
-    auto ret = new CORE_DEF_NAME::vm_impl<arch::CORE_DEF_NAME>(*core, dump);
318
-    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
319
-    return std::unique_ptr<vm_if>(ret);
320
-}
321
-
322
-} // namespace iss

+ 3
- 4
riscv/incl/iss/arch/riscv_hart_msu_vp.h View File

@@ -40,6 +40,7 @@
40 40
 #include "iss/instrumentation_if.h"
41 41
 #include "iss/log_categories.h"
42 42
 #include "iss/vm_if.h"
43
+#include <fmt/format.h>
43 44
 #include <array>
44 45
 #include <elfio/elfio.hpp>
45 46
 #include <iomanip>
@@ -478,10 +479,8 @@ public:
478 479
     void wait_until(uint64_t flags) override;
479 480
 
480 481
     void disass_output(uint64_t pc, const std::string instr) override {
481
-        std::stringstream s;
482
-        s << "[p:" << lvl[this->reg.machine_state] << ";s:0x" << std::hex << std::setfill('0')
483
-          << std::setw(sizeof(reg_t) * 2) << (reg_t)state.mstatus << std::dec << ";c:" << this->reg.icount << "]";
484
-        CLOG(INFO, disass) << "0x" << std::setw(16) << std::setfill('0') << std::hex << pc << "\t\t" << instr << "\t" << s.str();
482
+        CLOG(INFO, disass) << fmt::format("0x{:016x}    {:40} [p:{};s:0x{:x};c:{}]",
483
+                pc, instr, lvl[this->reg.machine_state], (reg_t)state.mstatus, this->reg.icount);
485 484
     };
486 485
 
487 486
     iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }

+ 84
- 52
riscv/incl/iss/arch/rv32gc.h View File

@@ -1,53 +1,59 @@
1
-////////////////////////////////////////////////////////////////////////////////
2
-// Copyright (C) 2017, MINRES Technologies GmbH
3
-// All rights reserved.
4
-// 
5
-// Redistribution and use in source and binary forms, with or without
6
-// modification, are permitted provided that the following conditions are met:
7
-// 
8
-// 1. Redistributions of source code must retain the above copyright notice,
9
-//    this list of conditions and the following disclaimer.
10
-// 
11
-// 2. Redistributions in binary form must reproduce the above copyright notice,
12
-//    this list of conditions and the following disclaimer in the documentation
13
-//    and/or other materials provided with the distribution.
14
-// 
15
-// 3. Neither the name of the copyright holder nor the names of its contributors
16
-//    may be used to endorse or promote products derived from this software
17
-//    without specific prior written permission.
18
-// 
19
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
-// POSSIBILITY OF SUCH DAMAGE.
30
-// 
31
-////////////////////////////////////////////////////////////////////////////////
1
+/*******************************************************************************
2
+ * Copyright (C) 2017, 2018 MINRES Technologies GmbH
3
+ * All rights reserved.
4
+ *
5
+ * Redistribution and use in source and binary forms, with or without
6
+ * modification, are permitted provided that the following conditions are met:
7
+ *
8
+ * 1. Redistributions of source code must retain the above copyright notice,
9
+ *    this list of conditions and the following disclaimer.
10
+ *
11
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
12
+ *    this list of conditions and the following disclaimer in the documentation
13
+ *    and/or other materials provided with the distribution.
14
+ *
15
+ * 3. Neither the name of the copyright holder nor the names of its contributors
16
+ *    may be used to endorse or promote products derived from this software
17
+ *    without specific prior written permission.
18
+ *
19
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+ * POSSIBILITY OF SUCH DAMAGE.
30
+ *
31
+ *******************************************************************************/
32
+
32 33
 
33 34
 #ifndef _RV32GC_H_
34 35
 #define _RV32GC_H_
35 36
 
37
+#include <array>
38
+#include <iss/arch/traits.h>
36 39
 #include <iss/arch_if.h>
37 40
 #include <iss/vm_if.h>
38
-#include <iss/arch/traits.h>
39
-#include <array>
40 41
 
41 42
 namespace iss {
42 43
 namespace arch {
43 44
 
44 45
 struct rv32gc;
45 46
 
46
-template<>
47
-struct traits<rv32gc> {
47
+template <> struct traits<rv32gc> {
48 48
 
49 49
 	constexpr static char const* const core_type = "RV32GC";
50 50
     
51
+  	static constexpr std::array<const char*, 66> reg_names{
52
+ 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}};
53
+ 
54
+  	static constexpr std::array<const char*, 66> reg_aliases{
55
+ 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fcsr"}};
56
+
51 57
     enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
52 58
 
53 59
     constexpr static unsigned FP_REGS_SIZE = 64;
@@ -125,7 +131,39 @@ struct traits<rv32gc> {
125 131
         PENDING_TRAP,
126 132
         MACHINE_STATE,
127 133
         LAST_BRANCH,
128
-        ICOUNT
134
+        ICOUNT,
135
+        ZERO = X0,
136
+        RA = X1,
137
+        SP = X2,
138
+        GP = X3,
139
+        TP = X4,
140
+        T0 = X5,
141
+        T1 = X6,
142
+        T2 = X7,
143
+        S0 = X8,
144
+        S1 = X9,
145
+        A0 = X10,
146
+        A1 = X11,
147
+        A2 = X12,
148
+        A3 = X13,
149
+        A4 = X14,
150
+        A5 = X15,
151
+        A6 = X16,
152
+        A7 = X17,
153
+        S2 = X18,
154
+        S3 = X19,
155
+        S4 = X20,
156
+        S5 = X21,
157
+        S6 = X22,
158
+        S7 = X23,
159
+        S8 = X24,
160
+        S9 = X25,
161
+        S10 = X26,
162
+        S11 = X27,
163
+        T3 = X28,
164
+        T4 = X29,
165
+        T5 = X30,
166
+        T6 = X31
129 167
     };
130 168
 
131 169
     using reg_t = uint32_t;
@@ -138,21 +176,17 @@ struct traits<rv32gc> {
138 176
 
139 177
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
140 178
 
141
-    constexpr static unsigned reg_bit_width(unsigned r) {
142
-        constexpr std::array<const uint32_t, 72> RV32GC_reg_size{{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,32,32,32,64}};
143
-        return RV32GC_reg_size[r];
144
-    }
179
+ 	static constexpr std::array<const uint32_t, 72> reg_bit_widths{
180
+ 		{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,32,32,32,64}};
145 181
 
146
-    constexpr static unsigned reg_byte_offset(unsigned r) {
147
-    	constexpr std::array<const uint32_t, 73> RV32GC_reg_byte_offset{{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,280,288,296,304,312,320,328,336,344,352,360,368,376,384,392,396,400,404,408,412,416,424}};
148
-        return RV32GC_reg_byte_offset[r];
149
-    }
182
+    static constexpr std::array<const uint32_t, 73> reg_byte_offsets{
183
+    	{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,280,288,296,304,312,320,328,336,344,352,360,368,376,384,392,396,400,404,408,412,416,424}};
150 184
 
151 185
     static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
152 186
 
153
-    enum sreg_flag_e {FLAGS};
187
+    enum sreg_flag_e { FLAGS };
154 188
 
155
-    enum mem_type_e {MEM, CSR, FENCE, RES};
189
+    enum mem_type_e { MEM, CSR, FENCE, RES };
156 190
 };
157 191
 
158 192
 struct rv32gc: public arch_if {
@@ -177,14 +211,13 @@ struct rv32gc: public arch_if {
177 211
     /// deprecated
178 212
     void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
179 213
 
180
-    uint64_t get_icount() { return reg.icount;}
214
+    inline uint64_t get_icount() { return reg.icount; }
181 215
 
182 216
     inline bool should_stop() { return interrupt_sim; }
183 217
 
184 218
     inline phys_addr_t v2p(const iss::addr_t& addr){
185
-        if(addr.space != traits<rv32gc>::MEM ||
186
-                addr.type == iss::address_type::PHYSICAL ||
187
-                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL){
219
+        if (addr.space != traits<rv32gc>::MEM || addr.type == iss::address_type::PHYSICAL ||
220
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
188 221
             return phys_addr_t(addr.access, addr.space, addr.val&traits<rv32gc>::addr_mask);
189 222
         } else
190 223
             return virt2phys(addr);
@@ -194,8 +227,7 @@ struct rv32gc: public arch_if {
194 227
 
195 228
     virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
196 229
 
197
-    inline
198
-    uint32_t get_last_branch(){return reg.last_branch;}
230
+    inline uint32_t get_last_branch() { return reg.last_branch; }
199 231
 
200 232
 protected:
201 233
     struct RV32GC_regs {

+ 67
- 38
riscv/incl/iss/arch/rv32imac.h View File

@@ -30,6 +30,7 @@
30 30
  *
31 31
  *******************************************************************************/
32 32
 
33
+
33 34
 #ifndef _RV32IMAC_H_
34 35
 #define _RV32IMAC_H_
35 36
 
@@ -45,15 +46,15 @@ struct rv32imac;
45 46
 
46 47
 template <> struct traits<rv32imac> {
47 48
 
48
-    constexpr static char const *const core_type = "RV32IMAC";
49
+	constexpr static char const* const core_type = "RV32IMAC";
50
+    
51
+  	static constexpr std::array<const char*, 33> reg_names{
52
+ 		{"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc"}};
53
+ 
54
+  	static constexpr std::array<const char*, 33> reg_aliases{
55
+ 		{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}};
49 56
 
50
-    enum constants {
51
-        XLEN = 32,
52
-        PCLEN = 32,
53
-        MISA_VAL = 0b1000000000101000001000100000101,
54
-        PGSIZE = 0x1000,
55
-        PGMASK = 0xfff
56
-    };
57
+    enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000101000001000100000101, PGSIZE=0x1000, PGMASK=0xfff};
57 58
 
58 59
     constexpr static unsigned FP_REGS_SIZE = 0;
59 60
 
@@ -92,35 +93,61 @@ template <> struct traits<rv32imac> {
92 93
         X31,
93 94
         PC,
94 95
         NUM_REGS,
95
-        NEXT_PC = NUM_REGS,
96
+        NEXT_PC=NUM_REGS,
96 97
         TRAP_STATE,
97 98
         PENDING_TRAP,
98 99
         MACHINE_STATE,
99 100
         LAST_BRANCH,
100
-        ICOUNT
101
+        ICOUNT,
102
+        ZERO = X0,
103
+        RA = X1,
104
+        SP = X2,
105
+        GP = X3,
106
+        TP = X4,
107
+        T0 = X5,
108
+        T1 = X6,
109
+        T2 = X7,
110
+        S0 = X8,
111
+        S1 = X9,
112
+        A0 = X10,
113
+        A1 = X11,
114
+        A2 = X12,
115
+        A3 = X13,
116
+        A4 = X14,
117
+        A5 = X15,
118
+        A6 = X16,
119
+        A7 = X17,
120