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Fixed validation errors in core dsl files.

pull/1/head
Eyck Jentzsch 2 years ago
parent
19b660962b
commit
5b6dc36c9d
8 changed files with 528 additions and 327 deletions
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  1. +15
    -10
      riscv/gen_input/RV32C.core_desc
  2. +2
    -2
      riscv/gen_input/RV32D.core_desc
  3. +2
    -2
      riscv/gen_input/RV32F.core_desc
  4. +21
    -21
      riscv/gen_input/RV32IBase.core_desc
  5. +4
    -4
      riscv/gen_input/RV64IBase.core_desc
  6. +247
    -167
      riscv/src/internal/vm_rv32gc.cpp
  7. +148
    -76
      riscv/src/internal/vm_rv32imac.cpp
  8. +89
    -45
      riscv/src/internal/vm_rv64ia.cpp

+ 15
- 10
riscv/gen_input/RV32C.core_desc View File

@ -15,9 +15,14 @@ InsructionSet RV32IC {
JALR(no_cont){ // overwriting the implementation if rv32i, alignment does not need to be word
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
if(rd!=0) X[rd] <= PC+4;
val ret[XLEN] <= X[rs1]+ imm;
PC<=ret& ~0x1;
val new_pc[XLEN] <= X[rs1]s+ imm;
val align[XLEN] <= new_pc & 0x1;
if(align != 0){
raise(0, 0);
} else {
if(rd!=0) X[rd] <= PC+4;
PC<=new_pc & ~0x1;
}
}
C.ADDI4SPN { //(RES, imm=0)
encoding: b000 | imm[5:4] | imm[9:6] | imm[2:2] | imm[3:3] | rd[2:0] | b00;
@ -40,7 +45,7 @@ InsructionSet RV32IC {
C.ADDI {//(RV32)
encoding:b000 | imm[5:5]s | rs1[4:0] | imm[4:0]s | b01;
args_disass: "x%rs1$d, 0x%imm$05x";
X[rs1] <= X[rs1] + imm;
X[rs1] <= X[rs1]'s + imm;
}
C.NOP {
encoding:b000 | b0 | b00000 | b00000 | b01;
@ -50,7 +55,7 @@ InsructionSet RV32IC {
encoding: b001 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
args_disass: "0x%imm$05x";
X[1] <= PC+2;
PC<=PC+imm;
PC<=PC's+imm;
}
C.LI {//(RV32)
encoding:b010 | imm[5:5]s | rd[4:0] | imm[4:0]s | b01;
@ -60,7 +65,7 @@ InsructionSet RV32IC {
}
// order matters here as C.ADDI16SP overwrites C.LUI vor rd==2
C.LUI {//(RV32)
encoding:b011 | imm[17:17]s | rd[4:0] | imm[16:12]s | b01;
encoding:b011 | imm[17:17] | rd[4:0] | imm[16:12]s | b01;
args_disass: "x%rd$d, 0x%imm$05x";
if(rd == 0) raise(0, 2); //TODO: should it be handled as trap?
if(imm == 0) raise(0, 2); //TODO: should it be handled as trap?
@ -84,7 +89,7 @@ InsructionSet RV32IC {
X[rs1_idx] <= shra(X[rs1_idx], shamt);
}
C.ANDI {//(RV32)
encoding:b100 | imm[5:5]s | b10 | rs1[2:0] | imm[4:0]s | b01;
encoding:b100 | imm[5:5] | b10 | rs1[2:0] | imm[4:0] | b01;
args_disass: "x(8+%rs1$d), 0x%imm$05x";
val rs1_idx[5] <= rs1 + 8;
X[rs1_idx] <= X[rs1_idx] & imm;
@ -116,17 +121,17 @@ InsructionSet RV32IC {
C.J(no_cont) {//(RV32)
encoding:b101 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
args_disass: "0x%imm$05x";
PC<=PC+imm;
PC<=PC's+imm;
}
C.BEQZ(no_cont,cond) {//(RV32)
encoding:b110 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s |imm[2:1]s | imm[5:5]s | b01;
args_disass: "x(8+%rs1$d), 0x%imm$05x";
PC<=choose(X[rs1+8]==0, PC+imm, PC+2);
PC<=choose(X[rs1+8]==0, PC's+imm, PC+2);
}
C.BNEZ(no_cont,cond) {//(RV32)
encoding:b111 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s | imm[2:1]s | imm[5:5]s | b01;
args_disass: "x(8+%rs1$d), 0x%imm$05x";
PC<=choose(X[rs1+8]!=0, PC+imm, PC+2);
PC<=choose(X[rs1+8]!=0, PC's+imm, PC+2);
}
C.SLLI {//(RV32)
encoding:b000 | b0 | rs1[4:0] | shamt[4:0] | b10;

+ 2
- 2
riscv/gen_input/RV32D.core_desc View File

@ -11,7 +11,7 @@ InsructionSet RV32D extends RV32IBase{
FLD {
encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000111;
args_disass:"f%rd$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s + imm;
val res[64] <= MEM[offs]{64};
if(FLEN==64)
F[rd] <= res;
@ -23,7 +23,7 @@ InsructionSet RV32D extends RV32IBase{
FSD {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100111;
args_disass:"f%rs2$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{64}<=F[rs2]{64};
}
FMADD.D {

+ 2
- 2
riscv/gen_input/RV32F.core_desc View File

@ -11,7 +11,7 @@ InsructionSet RV32F extends RV32IBase{
FLW {
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
args_disass:"f%rd$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s + imm;
val res[32] <= MEM[offs]{32};
if(FLEN==32)
F[rd] <= res;
@ -23,7 +23,7 @@ InsructionSet RV32F extends RV32IBase{
FSW {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
args_disass:"f%rs2$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{32}<=F[rs2]{32};
}
FMADD.S {

+ 21
- 21
riscv/gen_input/RV32IBase.core_desc View File

@ -28,18 +28,18 @@ InsructionSet RV32IBase {
AUIPC{
encoding: imm[31:12]s | rd[4:0] | b0010111;
args_disass: "x%rd%, 0x%imm$08x";
if(rd!=0) X[rd] <= PC+imm;
if(rd!=0) X[rd] <= PC's+imm;
}
JAL(no_cont){
encoding: imm[20:20]s | imm[10:1]s | imm[11:11]s | imm[19:12]s | rd[4:0] | b1101111;
args_disass: "x%rd$d, 0x%imm$x";
if(rd!=0) X[rd] <= PC+4;
PC<=PC+imm;
PC<=PC's+imm;
}
JALR(no_cont){
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
val new_pc[XLEN] <= X[rs1]+ imm;
val new_pc[XLEN] <= X[rs1]'s+ imm;
val align[XLEN] <= new_pc & 0x2;
if(align != 0){
raise(0, 0);
@ -51,85 +51,85 @@ InsructionSet RV32IBase {
BEQ(no_cont,cond){
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011;
args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
PC<=choose(X[rs1]==X[rs2], PC+imm, PC+4);
PC<=choose(X[rs1]==X[rs2], PC's+imm, PC+4);
}
BNE(no_cont,cond){
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011;
args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
PC<=choose(X[rs1]!=X[rs2], PC+imm, PC+4);
PC<=choose(X[rs1]!=X[rs2], PC's+imm, PC+4);
}
BLT(no_cont,cond){
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011;
args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
PC<=choose(X[rs1]s<X[rs2]s, PC+imm, PC+4);
PC<=choose(X[rs1]s<X[rs2]s, PC's+imm, PC+4);
}
BGE(no_cont,cond) {
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b101 | imm[4:1]s | imm[11:11]s | b1100011;
args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
PC<=choose(X[rs1]s>=X[rs2]s, PC+imm, PC+4);
PC<=choose(X[rs1]s>=X[rs2]s, PC's+imm, PC+4);
}
BLTU(no_cont,cond) {
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011;
args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
PC<=choose(X[rs1]<X[rs2],PC+imm, PC+4);
PC<=choose(X[rs1]<X[rs2],PC's+imm, PC+4);
}
BGEU(no_cont,cond) {
encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b111 | imm[4:1]s | imm[11:11]s | b1100011;
args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
PC<=choose(X[rs1]>=X[rs2], PC+imm, PC+4);
PC<=choose(X[rs1]>=X[rs2], PC's+imm, PC+4);
}
LB {
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0000011;
args_disass:"x%rd$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s+imm;
if(rd!=0) X[rd]<=sext(MEM[offs]);
}
LH {
encoding: imm[11:0]s | rs1[4:0] | b001 | rd[4:0] | b0000011;
args_disass:"x%rd$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s+imm;
if(rd!=0) X[rd]<=sext(MEM[offs]{16});
}
LW {
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011;
args_disass:"x%rd$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s+imm;
if(rd!=0) X[rd]<=sext(MEM[offs]{32});
}
LBU {
encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0000011;
args_disass:"x%rd$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s+imm;
if(rd!=0) X[rd]<=zext(MEM[offs]);
}
LHU {
encoding: imm[11:0]s | rs1[4:0] | b101 | rd[4:0] | b0000011;
args_disass:"x%rd$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s+imm;
if(rd!=0) X[rd]<=zext(MEM[offs]{16});
}
SB {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:0]s | b0100011;
args_disass:"x%rs2$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1] + imm;
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs] <= X[rs2];
}
SH {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:0]s | b0100011;
args_disass:"x%rs2$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1] + imm;
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{16} <= X[rs2];
}
SW {
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100011;
args_disass:"x%rs2$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1] + imm;
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{32} <= X[rs2];
}
ADDI {
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0010011;
args_disass:"x%rd$d, x%rs1$d, %imm%";
if(rd != 0) X[rd] <= X[rs1] + imm;
if(rd != 0) X[rd] <= X[rs1]'s + imm;
}
SLTI {
encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0010011;
@ -143,17 +143,17 @@ InsructionSet RV32IBase {
if (rd != 0) X[rd] <= choose(X[rs1]'u < full_imm'u, 1, 0);
}
XORI {
encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0010011;
encoding: imm[11:0] | rs1[4:0] | b100 | rd[4:0] | b0010011;
args_disass:"x%rd$d, x%rs1$d, %imm%";
if(rd != 0) X[rd] <= X[rs1] ^ imm;
}
ORI {
encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0010011;
encoding: imm[11:0] | rs1[4:0] | b110 | rd[4:0] | b0010011;
args_disass:"x%rd$d, x%rs1$d, %imm%";
if(rd != 0) X[rd] <= X[rs1] | imm;
}
ANDI {
encoding: imm[11:0]s | rs1[4:0] | b111 | rd[4:0] | b0010011;
encoding: imm[11:0] | rs1[4:0] | b111 | rd[4:0] | b0010011;
args_disass:"x%rd$d, x%rs1$d, %imm%";
if(rd != 0) X[rd] <= X[rs1] & imm;
}

+ 4
- 4
riscv/gen_input/RV64IBase.core_desc View File

@ -5,19 +5,19 @@ InsructionSet RV64IBase extends RV32IBase {
LWU { // 80000104: 0000ef03 lwu t5,0(ra)
encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0000011;
args_disass:"x%rd$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s+imm;
if(rd!=0) X[rd]<=zext(MEM[offs]{32});
}
LD{
encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000011;
args_disass:"x%rd$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1]+imm;
val offs[XLEN] <= X[rs1]'s + imm;
if(rd!=0) X[rd]<=sext(MEM[offs]{64});
}
SD{
encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100011;
args_disass:"x%rs2$d, %imm%(x%rs1$d)";
val offs[XLEN] <= X[rs1] + imm;
val offs[XLEN] <= X[rs1]'s + imm;
MEM[offs]{64} <= X[rs2];
}
SLLI {
@ -39,7 +39,7 @@ InsructionSet RV64IBase extends RV32IBase {
encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0011011;
args_disass:"x%rd$d, x%rs1$d, %imm%";
if(rd != 0){
val res[32] <= X[rs1]{32} + imm;
val res[32] <= X[rs1]{32}'s + imm;
X[rd] <= sext(res);
}
}

+ 247
- 167
riscv/src/internal/vm_rv32gc.cpp
File diff suppressed because it is too large
View File


+ 148
- 76
riscv/src/internal/vm_rv32imac.cpp View File

@ -451,7 +451,9 @@ private:
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
@ -492,7 +494,9 @@ private:
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
Value* PC_val = this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
this->gen_sync(iss::POST_SYNC, 2);
@ -524,19 +528,47 @@ private:
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+4;
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAdd(
cur_pc_val,
this->gen_const(32U, 4));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
Value* ret_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
Value* new_pc_val = this->builder.CreateAdd(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
Value* PC_val = this->builder.CreateAnd(
ret_val,
this->builder.CreateNot(this->gen_const(32U, 0x1)));
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
Value* align_val = this->builder.CreateAnd(
new_pc_val,
this->gen_const(32U, 0x1));
{
llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk);
llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext);
llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext);
// this->builder.SetInsertPoint(bb);
this->gen_cond_branch(this->builder.CreateICmp(
ICmpInst::ICMP_NE,
align_val,
this->gen_const(64U, 0)),
bb_then,
bb_else);
this->builder.SetInsertPoint(bb_then);
{
this->gen_raise_trap(0, 0);
}
this->builder.CreateBr(bbnext);
this->builder.SetInsertPoint(bb_else);
{
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAdd(
cur_pc_val,
this->gen_const(32U, 4));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
Value* PC_val = this->builder.CreateAnd(
new_pc_val,
this->builder.CreateNot(this->gen_const(32U, 0x1)));
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
}
this->builder.CreateBr(bbnext);
bb=bbnext;
}
this->builder.SetInsertPoint(bb);
this->gen_sync(iss::POST_SYNC, 3);
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
@ -572,7 +604,9 @@ private:
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -614,7 +648,9 @@ private:
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -660,7 +696,9 @@ private:
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
32, true)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -706,7 +744,9 @@ private:
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
32, true)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -748,7 +788,9 @@ private:
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -790,7 +832,9 @@ private:
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -827,7 +871,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
@ -868,7 +914,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
@ -909,7 +957,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
@ -950,7 +1000,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
@ -991,7 +1043,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
@ -1032,7 +1086,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
this->gen_write_mem(
@ -1071,7 +1127,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
this->gen_write_mem(
@ -1110,7 +1168,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
this->gen_write_mem(
@ -1150,7 +1210,9 @@ private:
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
@ -1256,11 +1318,11 @@ private:
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("XORI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
@ -1293,11 +1355,11 @@ private:
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("ORI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
@ -1330,11 +1392,11 @@ private:
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
@ -1545,8 +1607,8 @@ private:
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateSub(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
@ -2652,13 +2714,13 @@ private:
this->gen_cond_branch(this->builder.CreateICmp(
ICmpInst::ICMP_NE,
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
this->gen_const(32U, 0)),
this->gen_const(64U, 0)),
bb_then,
bb_else);
this->builder.SetInsertPoint(bb_then);
{
int32_t M1_val = (-1);
uint32_t MMIN_val = (-1) << (32 - 1);
uint32_t M1_val = - 1;
uint32_t MMIN_val = - 1 << 32 - 1;
{
llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk);
llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext);
@ -2781,7 +2843,7 @@ private:
this->gen_cond_branch(this->builder.CreateICmp(
ICmpInst::ICMP_NE,
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
this->gen_const(32U, 0)),
this->gen_const(64U, 0)),
bb_then,
bb_else);
this->builder.SetInsertPoint(bb_then);
@ -2848,13 +2910,13 @@ private:
this->gen_cond_branch(this->builder.CreateICmp(
ICmpInst::ICMP_NE,
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
this->gen_const(32U, 0)),
this->gen_const(64U, 0)),
bb_then,
bb_else);
this->builder.SetInsertPoint(bb_then);
{
int32_t M1_val = (-1);
uint32_t MMIN_val = (-1) << (32 - 1);
uint32_t M1_val = - 1;
uint32_t MMIN_val = - 1 << 32 - 1;
{
llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk);
llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext);
@ -2895,7 +2957,7 @@ private:
this->builder.CreateBr(bbnext);
this->builder.SetInsertPoint(bb_else);
{
Value* Xtmp1_val = this->builder.CreateSRem(
Value* Xtmp1_val = this->builder.CreateURem(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 3),
32,
@ -2914,7 +2976,7 @@ private:
this->builder.CreateBr(bbnext);
this->builder.SetInsertPoint(bb_else);
{
Value* Xtmp2_val = this->builder.CreateSRem(
Value* Xtmp2_val = this->builder.CreateURem(
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 2),
32,
@ -2981,7 +3043,7 @@ private:
this->gen_cond_branch(this->builder.CreateICmp(
ICmpInst::ICMP_NE,
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
this->gen_const(32U, 0)),
this->gen_const(64U, 0)),
bb_then,
bb_else);
this->builder.SetInsertPoint(bb_then);
@ -3098,7 +3160,7 @@ private:
this->gen_cond_branch(this->builder.CreateICmp(
ICmpInst::ICMP_NE,
res1_val,
this->gen_const(32U, 0)),
this->gen_const(64U, 0)),
bb_then,
bbnext);
this->builder.SetInsertPoint(bb_then);
@ -3634,7 +3696,7 @@ private:
Value* Xtmp0_val = this->builder.CreateAdd(
this->gen_reg_load(2 + traits<ARCH>::X0, 0),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr((fld_rd_val + 8) + traits<ARCH>::X0), false);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + 8 + traits<ARCH>::X0), false);
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 71);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
@ -3667,10 +3729,10 @@ private:
pc=pc+2;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load((fld_rs1_val + 8) + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs1_val + 8 + traits<ARCH>::X0, 0),
this->gen_const(32U, fld_uimm_val));
Value* Xtmp0_val = this->gen_read_mem(traits<ARCH>::MEM, offs_val, 32/8);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr((fld_rd_val + 8) + traits<ARCH>::X0), false);
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + 8 + traits<ARCH>::X0), false);
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 72);
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
@ -3703,9 +3765,9 @@ private:
pc=pc+2;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load((fld_rs1_val + 8) + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs1_val + 8 + traits<ARCH>::X0, 0),
this->gen_const(32U, fld_uimm_val));
Value* MEMtmp0_val = this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0);
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0);
this->gen_write_mem(
traits<ARCH>::MEM,
offs_val,
@ -3741,7 +3803,9 @@ private:
pc=pc+2;
Value* Xtmp0_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
32, true),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rs1_val + traits<ARCH>::X0), false);
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
@ -3806,7 +3870,9 @@ private:
this->gen_const(32U, 2));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(1 + traits<ARCH>::X0), false);
Value* PC_val = this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
this->gen_sync(iss::POST_SYNC, 76);
@ -3855,12 +3921,12 @@ private:
this->gen_sync(iss::PRE_SYNC, 78);
int32_t fld_imm_val = 0 | (bit_sub<2,5>(instr) << 12) | (signed_bit_sub<12,1>(instr) << 17);
int32_t fld_imm_val = 0 | (bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17);
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("C.LUI x%1$d, 0x%2$05x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
@ -3945,7 +4011,7 @@ private:
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+2;
uint8_t rs1_idx_val = (fld_rs1_val + 8);
uint8_t rs1_idx_val = fld_rs1_val + 8;
Value* Xtmp0_val = this->builder.CreateLShr(
this->gen_reg_load(rs1_idx_val + traits<ARCH>::X0, 0),
this->gen_const(32U, fld_shamt_val));
@ -3980,7 +4046,7 @@ private:
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+2;
uint8_t rs1_idx_val = (fld_rs1_val + 8);
uint8_t rs1_idx_val = fld_rs1_val + 8;
Value* Xtmp0_val = this->builder.CreateAShr(
this->gen_reg_load(rs1_idx_val + traits<ARCH>::X0, 0),
this->gen_const(32U, fld_shamt_val));
@ -3998,12 +4064,12 @@ private:
this->gen_sync(iss::PRE_SYNC, 82);
int8_t fld_imm_val = 0 | (bit_sub<2,5>(instr)) | (signed_bit_sub<12,1>(instr) << 5);
uint8_t fld_imm_val = 0 | (bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5);
uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("C.ANDI x(8+%1$d), 0x%2$05x");
ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
@ -4015,7 +4081,7 @@ private:
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+2;
uint8_t rs1_idx_val = (fld_rs1_val + 8);
uint8_t rs1_idx_val = fld_rs1_val + 8;
Value* Xtmp0_val = this->builder.CreateAnd(
this->gen_reg_load(rs1_idx_val + traits<ARCH>::X0, 0),
this->gen_const(32U, fld_imm_val));
@ -4050,10 +4116,10 @@ private:
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+2;
uint8_t rd_idx_val = (fld_rd_val + 8);
uint8_t rd_idx_val = fld_rd_val + 8;
Value* Xtmp0_val = this->builder.CreateSub(
this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0),
this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0));
this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits<ARCH>::X0), false);
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 83);
@ -4085,10 +4151,10 @@ private:
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+2;
uint8_t rd_idx_val = (fld_rd_val + 8);
uint8_t rd_idx_val = fld_rd_val + 8;
Value* Xtmp0_val = this->builder.CreateXor(
this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0),
this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0));
this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits<ARCH>::X0), false);
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 84);
@ -4120,10 +4186,10 @@ private:
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+2;
uint8_t rd_idx_val = (fld_rd_val + 8);
uint8_t rd_idx_val = fld_rd_val + 8;
Value* Xtmp0_val = this->builder.CreateOr(
this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0),
this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0));
this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits<ARCH>::X0), false);
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 85);
@ -4155,10 +4221,10 @@ private:
Value* cur_pc_val = this->gen_const(32, pc.val);
pc=pc+2;
uint8_t rd_idx_val = (fld_rd_val + 8);
uint8_t rd_idx_val = fld_rd_val + 8;
Value* Xtmp0_val = this->builder.CreateAnd(
this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0),
this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0));
this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits<ARCH>::X0), false);
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
this->gen_sync(iss::POST_SYNC, 86);
@ -4190,7 +4256,9 @@ private:
pc=pc+2;
Value* PC_val = this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val));
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
this->gen_sync(iss::POST_SYNC, 87);
@ -4224,10 +4292,12 @@ private:
Value* PC_val = this->gen_choose(
this->builder.CreateICmp(
ICmpInst::ICMP_EQ,
this->gen_reg_load((fld_rs1_val + 8) + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs1_val + 8 + traits<ARCH>::X0, 0),
this->gen_const(32U, 0)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -4265,10 +4335,12 @@ private:
Value* PC_val = this->gen_choose(
this->builder.CreateICmp(
ICmpInst::ICMP_NE,
this->gen_reg_load((fld_rs1_val + 8) + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs1_val + 8 + traits<ARCH>::X0, 0),
this->gen_const(32U, 0)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
32, true),
this->gen_const(32U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,

+ 89
- 45
riscv/src/internal/vm_rv64ia.cpp View File

@ -391,7 +391,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
@ -432,7 +434,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
@ -473,7 +477,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
this->gen_write_mem(
@ -636,10 +642,12 @@ private:
if(fld_rd_val != 0){
Value* res_val = this->builder.CreateAdd(
this->builder.CreateTrunc(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this-> get_type(32)
),
this->gen_ext(
this->builder.CreateTrunc(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this-> get_type(32)
),
32, true),
this->gen_const(32U, fld_imm_val));
Value* Xtmp0_val = this->gen_ext(
res_val,
@ -855,14 +863,14 @@ private:
if(fld_rd_val != 0){
Value* res_val = this->builder.CreateSub(
this->builder.CreateTrunc(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this-> get_type(32)
),
this->builder.CreateTrunc(
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
this-> get_type(32)
));
this->builder.CreateTrunc(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this-> get_type(32)
),
this->builder.CreateTrunc(
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
this-> get_type(32)
));
Value* Xtmp0_val = this->gen_ext(
res_val,
64,
@ -901,7 +909,7 @@ private:
pc=pc+4;
if(fld_rd_val != 0){
int32_t mask_val = 0x1f;
uint32_t mask_val = 0x1f;
Value* count_val = this->builder.CreateAnd(
this->builder.CreateTrunc(
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
@ -952,7 +960,7 @@ private:
pc=pc+4;
if(fld_rd_val != 0){
int32_t mask_val = 0x1f;
uint32_t mask_val = 0x1f;
Value* count_val = this->builder.CreateAnd(
this->builder.CreateTrunc(
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
@ -1003,7 +1011,7 @@ private:
pc=pc+4;
if(fld_rd_val != 0){
int32_t mask_val = 0x1f;
uint32_t mask_val = 0x1f;
Value* count_val = this->builder.CreateAnd(
this->builder.CreateTrunc(
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
@ -1088,7 +1096,9 @@ private:
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
64, true),
this->gen_const(64U, fld_imm_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
@ -1129,7 +1139,9 @@ private:
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
Value* PC_val = this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
64, true),
this->gen_const(64U, fld_imm_val));
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
this->gen_sync(iss::POST_SYNC, 17);
@ -1162,7 +1174,9 @@ private:
pc=pc+4;
Value* new_pc_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
Value* align_val = this->builder.CreateAnd(
new_pc_val,
@ -1235,7 +1249,9 @@ private:
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
64, true),
this->gen_const(64U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -1277,7 +1293,9 @@ private:
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
64, true),
this->gen_const(64U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -1323,7 +1341,9 @@ private:
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
64, true)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
64, true),
this->gen_const(64U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -1369,7 +1389,9 @@ private:
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
64, true)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
64, true),
this->gen_const(64U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -1411,7 +1433,9 @@ private:
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
64, true),
this->gen_const(64U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -1453,7 +1477,9 @@ private:
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
this->builder.CreateAdd(
cur_pc_val,
this->gen_ext(
cur_pc_val,
64, true),
this->gen_const(64U, fld_imm_val)),
this->builder.CreateAdd(
cur_pc_val,
@ -1490,7 +1516,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
@ -1531,7 +1559,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
@ -1572,7 +1602,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
@ -1613,7 +1645,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
@ -1654,7 +1688,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
if(fld_rd_val != 0){
Value* Xtmp0_val = this->gen_ext(
@ -1695,7 +1731,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
this->gen_write_mem(
@ -1734,7 +1772,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
this->gen_write_mem(
@ -1773,7 +1813,9 @@ private:
pc=pc+4;
Value* offs_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
this->gen_write_mem(
@ -1813,7 +1855,9 @@ private:
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateAdd(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_ext(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
64, true),
this->gen_const(64U, fld_imm_val));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
@ -1919,11 +1963,11 @@ private:
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("XORI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
@ -1956,11 +2000,11 @@ private:
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("ORI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
@ -1993,11 +2037,11 @@ private:
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
if(this->disass_enabled){
/* generate console output when executing the command */
boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
std::vector<llvm::Value*> args {
this->core_ptr,
this->gen_const(64, pc.val),
@ -2085,8 +2129,8 @@ private:
if(fld_rd_val != 0){
Value* Xtmp0_val = this->builder.CreateSub(
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
}
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
@ -3639,7 +3683,7 @@ private:
this->gen_cond_branch(this->builder.CreateICmp(
ICmpInst::ICMP_NE,