Browse Source

Fixed validation errors in core dsl files.

Eyck Jentzsch 1 year ago
parent
commit
5b6dc36c9d

+ 15
- 10
riscv/gen_input/RV32C.core_desc View File

@@ -15,9 +15,14 @@ InsructionSet RV32IC {
15 15
         JALR(no_cont){ // overwriting the implementation if rv32i, alignment does not need to be word
16 16
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
17 17
             args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
18
-            if(rd!=0) X[rd] <= PC+4;
19
-            val ret[XLEN] <= X[rs1]+ imm;
20
-            PC<=ret& ~0x1;
18
+            val new_pc[XLEN] <= X[rs1]s+ imm;
19
+            val align[XLEN] <= new_pc & 0x1;
20
+            if(align != 0){
21
+                raise(0, 0);
22
+            } else {
23
+                if(rd!=0) X[rd] <= PC+4;
24
+                PC<=new_pc & ~0x1;
25
+            }
21 26
         }
22 27
         C.ADDI4SPN { //(RES, imm=0)
23 28
             encoding: b000 | imm[5:4] | imm[9:6] | imm[2:2] | imm[3:3] | rd[2:0] | b00;
@@ -40,7 +45,7 @@ InsructionSet RV32IC {
40 45
         C.ADDI {//(RV32)
41 46
             encoding:b000 | imm[5:5]s | rs1[4:0] | imm[4:0]s | b01;
42 47
             args_disass: "x%rs1$d, 0x%imm$05x";
43
-            X[rs1] <= X[rs1] + imm;
48
+            X[rs1] <= X[rs1]'s + imm;
44 49
         }
45 50
         C.NOP {
46 51
             encoding:b000 | b0 | b00000 | b00000 | b01;
@@ -50,7 +55,7 @@ InsructionSet RV32IC {
50 55
             encoding: b001 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
51 56
             args_disass: "0x%imm$05x";
52 57
             X[1] <= PC+2;
53
-            PC<=PC+imm;
58
+            PC<=PC's+imm;
54 59
         }
55 60
         C.LI {//(RV32)
56 61
             encoding:b010 | imm[5:5]s | rd[4:0] | imm[4:0]s | b01;
@@ -60,7 +65,7 @@ InsructionSet RV32IC {
60 65
         }
61 66
         // order matters here as C.ADDI16SP overwrites C.LUI vor rd==2
62 67
         C.LUI {//(RV32)
63
-            encoding:b011 | imm[17:17]s | rd[4:0] | imm[16:12]s | b01;
68
+            encoding:b011 | imm[17:17] | rd[4:0] | imm[16:12]s | b01;
64 69
             args_disass: "x%rd$d, 0x%imm$05x";
65 70
             if(rd == 0) raise(0, 2);   //TODO: should it be handled as trap?
66 71
             if(imm == 0) raise(0, 2);   //TODO: should it be handled as trap?
@@ -84,7 +89,7 @@ InsructionSet RV32IC {
84 89
             X[rs1_idx] <= shra(X[rs1_idx], shamt);
85 90
         }
86 91
         C.ANDI {//(RV32)
87
-            encoding:b100 | imm[5:5]s | b10 | rs1[2:0] | imm[4:0]s | b01;
92
+            encoding:b100 | imm[5:5] | b10 | rs1[2:0] | imm[4:0] | b01;
88 93
             args_disass: "x(8+%rs1$d), 0x%imm$05x";
89 94
             val rs1_idx[5] <= rs1 + 8;
90 95
             X[rs1_idx] <= X[rs1_idx] & imm;
@@ -116,17 +121,17 @@ InsructionSet RV32IC {
116 121
         C.J(no_cont) {//(RV32)
117 122
             encoding:b101 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
118 123
             args_disass: "0x%imm$05x";
119
-            PC<=PC+imm;
124
+            PC<=PC's+imm;
120 125
         }
121 126
         C.BEQZ(no_cont,cond) {//(RV32)
122 127
             encoding:b110 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s |imm[2:1]s | imm[5:5]s | b01;
123 128
             args_disass: "x(8+%rs1$d), 0x%imm$05x";
124
-            PC<=choose(X[rs1+8]==0, PC+imm, PC+2);
129
+            PC<=choose(X[rs1+8]==0, PC's+imm, PC+2);
125 130
         }
126 131
         C.BNEZ(no_cont,cond) {//(RV32)
127 132
             encoding:b111 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s | imm[2:1]s | imm[5:5]s | b01;
128 133
             args_disass: "x(8+%rs1$d), 0x%imm$05x";
129
-            PC<=choose(X[rs1+8]!=0, PC+imm, PC+2);
134
+            PC<=choose(X[rs1+8]!=0, PC's+imm, PC+2);
130 135
         }
131 136
         C.SLLI {//(RV32)
132 137
             encoding:b000 | b0 | rs1[4:0] | shamt[4:0] | b10;

+ 2
- 2
riscv/gen_input/RV32D.core_desc View File

@@ -11,7 +11,7 @@ InsructionSet RV32D extends RV32IBase{
11 11
         FLD {
12 12
             encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000111;
13 13
             args_disass:"f%rd$d, %imm%(x%rs1$d)";
14
-            val offs[XLEN] <= X[rs1]+imm;
14
+            val offs[XLEN] <= X[rs1]'s + imm;
15 15
             val res[64] <= MEM[offs]{64};
16 16
             if(FLEN==64)
17 17
                 F[rd] <= res;
@@ -23,7 +23,7 @@ InsructionSet RV32D extends RV32IBase{
23 23
         FSD {
24 24
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100111;
25 25
             args_disass:"f%rs2$d, %imm%(x%rs1$d)";
26
-            val offs[XLEN] <= X[rs1]+imm;
26
+            val offs[XLEN] <= X[rs1]'s + imm;
27 27
             MEM[offs]{64}<=F[rs2]{64};
28 28
         }
29 29
         FMADD.D {

+ 2
- 2
riscv/gen_input/RV32F.core_desc View File

@@ -11,7 +11,7 @@ InsructionSet RV32F extends RV32IBase{
11 11
         FLW {
12 12
             encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
13 13
             args_disass:"f%rd$d, %imm%(x%rs1$d)";
14
-            val offs[XLEN] <= X[rs1]+imm;
14
+            val offs[XLEN] <= X[rs1]'s + imm;
15 15
             val res[32] <= MEM[offs]{32};
16 16
             if(FLEN==32)
17 17
                 F[rd] <= res;
@@ -23,7 +23,7 @@ InsructionSet RV32F extends RV32IBase{
23 23
         FSW {
24 24
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
25 25
             args_disass:"f%rs2$d, %imm%(x%rs1$d)";
26
-            val offs[XLEN] <= X[rs1]+imm;
26
+            val offs[XLEN] <= X[rs1]'s + imm;
27 27
             MEM[offs]{32}<=F[rs2]{32};
28 28
         }
29 29
         FMADD.S {

+ 21
- 21
riscv/gen_input/RV32IBase.core_desc View File

@@ -28,18 +28,18 @@ InsructionSet RV32IBase {
28 28
         AUIPC{
29 29
             encoding: imm[31:12]s | rd[4:0] | b0010111;
30 30
             args_disass: "x%rd%, 0x%imm$08x";
31
-            if(rd!=0) X[rd] <= PC+imm;
31
+            if(rd!=0) X[rd] <= PC's+imm;
32 32
         }
33 33
         JAL(no_cont){
34 34
             encoding: imm[20:20]s | imm[10:1]s | imm[11:11]s | imm[19:12]s | rd[4:0] | b1101111;
35 35
             args_disass: "x%rd$d, 0x%imm$x";
36 36
             if(rd!=0) X[rd] <= PC+4;
37
-            PC<=PC+imm;
37
+            PC<=PC's+imm;
38 38
         }
39 39
         JALR(no_cont){
40 40
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
41 41
             args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
42
-            val new_pc[XLEN] <= X[rs1]+ imm;
42
+            val new_pc[XLEN] <= X[rs1]'s+ imm;
43 43
             val align[XLEN] <= new_pc & 0x2;
44 44
             if(align != 0){
45 45
                 raise(0, 0);
@@ -51,85 +51,85 @@ InsructionSet RV32IBase {
51 51
         BEQ(no_cont,cond){
52 52
             encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011;
53 53
             args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
54
-            PC<=choose(X[rs1]==X[rs2], PC+imm, PC+4);
54
+            PC<=choose(X[rs1]==X[rs2], PC's+imm, PC+4);
55 55
         }
56 56
         BNE(no_cont,cond){
57 57
             encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011;
58 58
             args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
59
-            PC<=choose(X[rs1]!=X[rs2], PC+imm, PC+4);
59
+            PC<=choose(X[rs1]!=X[rs2], PC's+imm, PC+4);
60 60
         }
61 61
         BLT(no_cont,cond){
62 62
             encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011;
63 63
             args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
64
-            PC<=choose(X[rs1]s<X[rs2]s, PC+imm, PC+4);
64
+            PC<=choose(X[rs1]s<X[rs2]s, PC's+imm, PC+4);
65 65
         }
66 66
         BGE(no_cont,cond) {
67 67
             encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b101 | imm[4:1]s | imm[11:11]s | b1100011;
68 68
             args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
69
-            PC<=choose(X[rs1]s>=X[rs2]s, PC+imm, PC+4);
69
+            PC<=choose(X[rs1]s>=X[rs2]s, PC's+imm, PC+4);
70 70
         }
71 71
         BLTU(no_cont,cond) {
72 72
             encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011;
73 73
             args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
74
-            PC<=choose(X[rs1]<X[rs2],PC+imm, PC+4);
74
+            PC<=choose(X[rs1]<X[rs2],PC's+imm, PC+4);
75 75
         }
76 76
         BGEU(no_cont,cond) {
77 77
             encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b111 | imm[4:1]s | imm[11:11]s | b1100011;
78 78
             args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
79
-            PC<=choose(X[rs1]>=X[rs2], PC+imm, PC+4);
79
+            PC<=choose(X[rs1]>=X[rs2], PC's+imm, PC+4);
80 80
         }
81 81
         LB {
82 82
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0000011;
83 83
             args_disass:"x%rd$d, %imm%(x%rs1$d)";
84
-            val offs[XLEN] <= X[rs1]+imm;
84
+            val offs[XLEN] <= X[rs1]'s+imm;
85 85
             if(rd!=0) X[rd]<=sext(MEM[offs]);
86 86
         }
87 87
         LH {
88 88
             encoding: imm[11:0]s | rs1[4:0] | b001 | rd[4:0] | b0000011;
89 89
             args_disass:"x%rd$d, %imm%(x%rs1$d)";
90
-            val offs[XLEN] <= X[rs1]+imm;
90
+            val offs[XLEN] <= X[rs1]'s+imm;
91 91
             if(rd!=0) X[rd]<=sext(MEM[offs]{16});            
92 92
         }
93 93
         LW {
94 94
             encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011;
95 95
             args_disass:"x%rd$d, %imm%(x%rs1$d)";
96
-            val offs[XLEN] <= X[rs1]+imm;
96
+            val offs[XLEN] <= X[rs1]'s+imm;
97 97
             if(rd!=0) X[rd]<=sext(MEM[offs]{32});
98 98
         }
99 99
         LBU {
100 100
             encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0000011;
101 101
             args_disass:"x%rd$d, %imm%(x%rs1$d)";
102
-            val offs[XLEN] <= X[rs1]+imm;
102
+            val offs[XLEN] <= X[rs1]'s+imm;
103 103
             if(rd!=0) X[rd]<=zext(MEM[offs]);
104 104
         }
105 105
         LHU {
106 106
             encoding: imm[11:0]s | rs1[4:0] | b101 | rd[4:0] | b0000011;
107 107
             args_disass:"x%rd$d, %imm%(x%rs1$d)";
108
-            val offs[XLEN] <= X[rs1]+imm;
108
+            val offs[XLEN] <= X[rs1]'s+imm;
109 109
             if(rd!=0) X[rd]<=zext(MEM[offs]{16});            
110 110
         }
111 111
         SB {
112 112
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:0]s | b0100011;
113 113
             args_disass:"x%rs2$d, %imm%(x%rs1$d)";
114
-            val offs[XLEN] <= X[rs1] + imm;
114
+            val offs[XLEN] <= X[rs1]'s + imm;
115 115
             MEM[offs] <= X[rs2];
116 116
         }
117 117
         SH {
118 118
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:0]s | b0100011;
119 119
             args_disass:"x%rs2$d, %imm%(x%rs1$d)";
120
-            val offs[XLEN] <= X[rs1] + imm;
120
+            val offs[XLEN] <= X[rs1]'s + imm;
121 121
             MEM[offs]{16} <= X[rs2];
122 122
         }
123 123
         SW {
124 124
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100011;
125 125
             args_disass:"x%rs2$d, %imm%(x%rs1$d)";
126
-            val offs[XLEN] <= X[rs1] + imm;
126
+            val offs[XLEN] <= X[rs1]'s + imm;
127 127
             MEM[offs]{32} <= X[rs2];
128 128
         }
129 129
         ADDI {
130 130
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0010011;
131 131
             args_disass:"x%rd$d, x%rs1$d, %imm%";
132
-            if(rd != 0) X[rd] <= X[rs1] + imm;
132
+            if(rd != 0) X[rd] <= X[rs1]'s + imm;
133 133
         }
134 134
         SLTI {
135 135
             encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0010011;
@@ -143,17 +143,17 @@ InsructionSet RV32IBase {
143 143
             if (rd != 0) X[rd] <= choose(X[rs1]'u < full_imm'u, 1, 0);
144 144
         }
145 145
         XORI {
146
-            encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0010011;
146
+            encoding: imm[11:0] | rs1[4:0] | b100 | rd[4:0] | b0010011;
147 147
             args_disass:"x%rd$d, x%rs1$d, %imm%";
148 148
             if(rd != 0) X[rd] <= X[rs1] ^ imm;
149 149
         }
150 150
         ORI {
151
-            encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0010011;
151
+            encoding: imm[11:0] | rs1[4:0] | b110 | rd[4:0] | b0010011;
152 152
             args_disass:"x%rd$d, x%rs1$d, %imm%";
153 153
             if(rd != 0) X[rd] <= X[rs1] | imm;
154 154
         }
155 155
         ANDI {
156
-            encoding: imm[11:0]s | rs1[4:0] | b111 | rd[4:0] | b0010011;
156
+            encoding: imm[11:0] | rs1[4:0] | b111 | rd[4:0] | b0010011;
157 157
             args_disass:"x%rd$d, x%rs1$d, %imm%";
158 158
             if(rd != 0) X[rd] <= X[rs1] & imm;
159 159
         }

+ 4
- 4
riscv/gen_input/RV64IBase.core_desc View File

@@ -5,19 +5,19 @@ InsructionSet RV64IBase extends RV32IBase {
5 5
         LWU { //    80000104: 0000ef03            lwu t5,0(ra)
6 6
             encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0000011;
7 7
             args_disass:"x%rd$d, %imm%(x%rs1$d)";
8
-            val offs[XLEN] <= X[rs1]+imm;
8
+            val offs[XLEN] <= X[rs1]'s+imm;
9 9
             if(rd!=0) X[rd]<=zext(MEM[offs]{32});
10 10
         }
11 11
         LD{
12 12
             encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000011;
13 13
             args_disass:"x%rd$d, %imm%(x%rs1$d)";
14
-            val offs[XLEN] <= X[rs1]+imm;
14
+            val offs[XLEN] <= X[rs1]'s + imm;
15 15
             if(rd!=0) X[rd]<=sext(MEM[offs]{64});
16 16
         }
17 17
         SD{
18 18
             encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100011;
19 19
             args_disass:"x%rs2$d, %imm%(x%rs1$d)";
20
-            val offs[XLEN] <= X[rs1] + imm;
20
+            val offs[XLEN] <= X[rs1]'s + imm;
21 21
             MEM[offs]{64} <= X[rs2];
22 22
         }
23 23
         SLLI {
@@ -39,7 +39,7 @@ InsructionSet RV64IBase extends RV32IBase {
39 39
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0011011;
40 40
             args_disass:"x%rd$d, x%rs1$d, %imm%";
41 41
             if(rd != 0){
42
-                val res[32] <= X[rs1]{32} + imm;
42
+                val res[32] <= X[rs1]{32}'s + imm;
43 43
                 X[rd] <= sext(res);
44 44
             } 
45 45
         }

+ 247
- 167
riscv/src/internal/vm_rv32gc.cpp
File diff suppressed because it is too large
View File


+ 148
- 76
riscv/src/internal/vm_rv32imac.cpp View File

@@ -451,7 +451,9 @@ private:
451 451
     	
452 452
     	if(fld_rd_val != 0){
453 453
     	    Value* Xtmp0_val = this->builder.CreateAdd(
454
-    	        cur_pc_val,
454
+    	        this->gen_ext(
455
+    	            cur_pc_val,
456
+    	            32, true),
455 457
     	        this->gen_const(32U, fld_imm_val));
456 458
     	    this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
457 459
     	}
@@ -492,7 +494,9 @@ private:
492 494
     	    this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
493 495
     	}
494 496
     	Value* PC_val = this->builder.CreateAdd(
495
-    	    cur_pc_val,
497
+    	    this->gen_ext(
498
+    	        cur_pc_val,
499
+    	        32, true),
496 500
     	    this->gen_const(32U, fld_imm_val));
497 501
     	this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
498 502
     	this->gen_sync(iss::POST_SYNC, 2);
@@ -524,19 +528,47 @@ private:
524 528
     	Value* cur_pc_val = this->gen_const(32, pc.val);
525 529
     	pc=pc+4;
526 530
     	
527
-    	if(fld_rd_val != 0){
528
-    	    Value* Xtmp0_val = this->builder.CreateAdd(
529
-    	        cur_pc_val,
530
-    	        this->gen_const(32U, 4));
531
-    	    this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
532
-    	}
533
-    	Value* ret_val = this->builder.CreateAdd(
534
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
531
+    	Value* new_pc_val = this->builder.CreateAdd(
532
+    	    this->gen_ext(
533
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
534
+    	        32, true),
535 535
     	    this->gen_const(32U, fld_imm_val));
536
-    	Value* PC_val = this->builder.CreateAnd(
537
-    	    ret_val,
538
-    	    this->builder.CreateNot(this->gen_const(32U, 0x1)));
539
-    	this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
536
+    	Value* align_val = this->builder.CreateAnd(
537
+    	    new_pc_val,
538
+    	    this->gen_const(32U, 0x1));
539
+    	{
540
+    	    llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk);
541
+    	    llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext);
542
+    	    llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext);
543
+    	    // this->builder.SetInsertPoint(bb);
544
+    	    this->gen_cond_branch(this->builder.CreateICmp(
545
+    	        ICmpInst::ICMP_NE,
546
+    	        align_val,
547
+    	        this->gen_const(64U, 0)),
548
+    	        bb_then,
549
+    	        bb_else);
550
+    	    this->builder.SetInsertPoint(bb_then);
551
+    	    {
552
+    	        this->gen_raise_trap(0, 0);
553
+    	    }
554
+    	    this->builder.CreateBr(bbnext);
555
+    	    this->builder.SetInsertPoint(bb_else);
556
+    	    {
557
+    	        if(fld_rd_val != 0){
558
+    	            Value* Xtmp0_val = this->builder.CreateAdd(
559
+    	                cur_pc_val,
560
+    	                this->gen_const(32U, 4));
561
+    	            this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
562
+    	        }
563
+    	        Value* PC_val = this->builder.CreateAnd(
564
+    	            new_pc_val,
565
+    	            this->builder.CreateNot(this->gen_const(32U, 0x1)));
566
+    	        this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
567
+    	    }
568
+    	    this->builder.CreateBr(bbnext);
569
+    	    bb=bbnext;
570
+    	}
571
+    	this->builder.SetInsertPoint(bb);
540 572
     	this->gen_sync(iss::POST_SYNC, 3);
541 573
     	this->gen_trap_check(this->leave_blk);
542 574
     	return std::make_tuple(iss::vm::BRANCH, nullptr);
@@ -572,7 +604,9 @@ private:
572 604
     	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
573 605
     	        this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
574 606
     	    this->builder.CreateAdd(
575
-    	        cur_pc_val,
607
+    	        this->gen_ext(
608
+    	            cur_pc_val,
609
+    	            32, true),
576 610
     	        this->gen_const(32U, fld_imm_val)),
577 611
     	    this->builder.CreateAdd(
578 612
     	        cur_pc_val,
@@ -614,7 +648,9 @@ private:
614 648
     	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
615 649
     	        this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
616 650
     	    this->builder.CreateAdd(
617
-    	        cur_pc_val,
651
+    	        this->gen_ext(
652
+    	            cur_pc_val,
653
+    	            32, true),
618 654
     	        this->gen_const(32U, fld_imm_val)),
619 655
     	    this->builder.CreateAdd(
620 656
     	        cur_pc_val,
@@ -660,7 +696,9 @@ private:
660 696
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
661 697
     	            32, true)),
662 698
     	    this->builder.CreateAdd(
663
-    	        cur_pc_val,
699
+    	        this->gen_ext(
700
+    	            cur_pc_val,
701
+    	            32, true),
664 702
     	        this->gen_const(32U, fld_imm_val)),
665 703
     	    this->builder.CreateAdd(
666 704
     	        cur_pc_val,
@@ -706,7 +744,9 @@ private:
706 744
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
707 745
     	            32, true)),
708 746
     	    this->builder.CreateAdd(
709
-    	        cur_pc_val,
747
+    	        this->gen_ext(
748
+    	            cur_pc_val,
749
+    	            32, true),
710 750
     	        this->gen_const(32U, fld_imm_val)),
711 751
     	    this->builder.CreateAdd(
712 752
     	        cur_pc_val,
@@ -748,7 +788,9 @@ private:
748 788
     	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
749 789
     	        this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
750 790
     	    this->builder.CreateAdd(
751
-    	        cur_pc_val,
791
+    	        this->gen_ext(
792
+    	            cur_pc_val,
793
+    	            32, true),
752 794
     	        this->gen_const(32U, fld_imm_val)),
753 795
     	    this->builder.CreateAdd(
754 796
     	        cur_pc_val,
@@ -790,7 +832,9 @@ private:
790 832
     	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
791 833
     	        this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
792 834
     	    this->builder.CreateAdd(
793
-    	        cur_pc_val,
835
+    	        this->gen_ext(
836
+    	            cur_pc_val,
837
+    	            32, true),
794 838
     	        this->gen_const(32U, fld_imm_val)),
795 839
     	    this->builder.CreateAdd(
796 840
     	        cur_pc_val,
@@ -827,7 +871,9 @@ private:
827 871
     	pc=pc+4;
828 872
     	
829 873
     	Value* offs_val = this->builder.CreateAdd(
830
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
874
+    	    this->gen_ext(
875
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
876
+    	        32, true),
831 877
     	    this->gen_const(32U, fld_imm_val));
832 878
     	if(fld_rd_val != 0){
833 879
     	    Value* Xtmp0_val = this->gen_ext(
@@ -868,7 +914,9 @@ private:
868 914
     	pc=pc+4;
869 915
     	
870 916
     	Value* offs_val = this->builder.CreateAdd(
871
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
917
+    	    this->gen_ext(
918
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
919
+    	        32, true),
872 920
     	    this->gen_const(32U, fld_imm_val));
873 921
     	if(fld_rd_val != 0){
874 922
     	    Value* Xtmp0_val = this->gen_ext(
@@ -909,7 +957,9 @@ private:
909 957
     	pc=pc+4;
910 958
     	
911 959
     	Value* offs_val = this->builder.CreateAdd(
912
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
960
+    	    this->gen_ext(
961
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
962
+    	        32, true),
913 963
     	    this->gen_const(32U, fld_imm_val));
914 964
     	if(fld_rd_val != 0){
915 965
     	    Value* Xtmp0_val = this->gen_ext(
@@ -950,7 +1000,9 @@ private:
950 1000
     	pc=pc+4;
951 1001
     	
952 1002
     	Value* offs_val = this->builder.CreateAdd(
953
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1003
+    	    this->gen_ext(
1004
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1005
+    	        32, true),
954 1006
     	    this->gen_const(32U, fld_imm_val));
955 1007
     	if(fld_rd_val != 0){
956 1008
     	    Value* Xtmp0_val = this->gen_ext(
@@ -991,7 +1043,9 @@ private:
991 1043
     	pc=pc+4;
992 1044
     	
993 1045
     	Value* offs_val = this->builder.CreateAdd(
994
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1046
+    	    this->gen_ext(
1047
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1048
+    	        32, true),
995 1049
     	    this->gen_const(32U, fld_imm_val));
996 1050
     	if(fld_rd_val != 0){
997 1051
     	    Value* Xtmp0_val = this->gen_ext(
@@ -1032,7 +1086,9 @@ private:
1032 1086
     	pc=pc+4;
1033 1087
     	
1034 1088
     	Value* offs_val = this->builder.CreateAdd(
1035
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1089
+    	    this->gen_ext(
1090
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1091
+    	        32, true),
1036 1092
     	    this->gen_const(32U, fld_imm_val));
1037 1093
     	Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
1038 1094
     	this->gen_write_mem(
@@ -1071,7 +1127,9 @@ private:
1071 1127
     	pc=pc+4;
1072 1128
     	
1073 1129
     	Value* offs_val = this->builder.CreateAdd(
1074
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1130
+    	    this->gen_ext(
1131
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1132
+    	        32, true),
1075 1133
     	    this->gen_const(32U, fld_imm_val));
1076 1134
     	Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
1077 1135
     	this->gen_write_mem(
@@ -1110,7 +1168,9 @@ private:
1110 1168
     	pc=pc+4;
1111 1169
     	
1112 1170
     	Value* offs_val = this->builder.CreateAdd(
1113
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1171
+    	    this->gen_ext(
1172
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1173
+    	        32, true),
1114 1174
     	    this->gen_const(32U, fld_imm_val));
1115 1175
     	Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
1116 1176
     	this->gen_write_mem(
@@ -1150,7 +1210,9 @@ private:
1150 1210
     	
1151 1211
     	if(fld_rd_val != 0){
1152 1212
     	    Value* Xtmp0_val = this->builder.CreateAdd(
1153
-    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1213
+    	        this->gen_ext(
1214
+    	            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1215
+    	            32, true),
1154 1216
     	        this->gen_const(32U, fld_imm_val));
1155 1217
     	    this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
1156 1218
     	}
@@ -1256,11 +1318,11 @@ private:
1256 1318
     	
1257 1319
     	uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
1258 1320
     	uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
1259
-    	int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
1321
+    	uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
1260 1322
     	if(this->disass_enabled){
1261 1323
     	    /* generate console output when executing the command */
1262 1324
     	    boost::format ins_fmter("XORI x%1$d, x%2$d, %3%");
1263
-    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
1325
+    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
1264 1326
     	    std::vector<llvm::Value*> args {
1265 1327
     	        this->core_ptr,
1266 1328
     	        this->gen_const(64, pc.val),
@@ -1293,11 +1355,11 @@ private:
1293 1355
     	
1294 1356
     	uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
1295 1357
     	uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
1296
-    	int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
1358
+    	uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
1297 1359
     	if(this->disass_enabled){
1298 1360
     	    /* generate console output when executing the command */
1299 1361
     	    boost::format ins_fmter("ORI x%1$d, x%2$d, %3%");
1300
-    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
1362
+    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
1301 1363
     	    std::vector<llvm::Value*> args {
1302 1364
     	        this->core_ptr,
1303 1365
     	        this->gen_const(64, pc.val),
@@ -1330,11 +1392,11 @@ private:
1330 1392
     	
1331 1393
     	uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
1332 1394
     	uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
1333
-    	int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
1395
+    	uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
1334 1396
     	if(this->disass_enabled){
1335 1397
     	    /* generate console output when executing the command */
1336 1398
     	    boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%");
1337
-    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
1399
+    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
1338 1400
     	    std::vector<llvm::Value*> args {
1339 1401
     	        this->core_ptr,
1340 1402
     	        this->gen_const(64, pc.val),
@@ -1545,8 +1607,8 @@ private:
1545 1607
     	
1546 1608
     	if(fld_rd_val != 0){
1547 1609
     	    Value* Xtmp0_val = this->builder.CreateSub(
1548
-    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1549
-    	        this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
1610
+    	         this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1611
+    	         this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
1550 1612
     	    this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
1551 1613
     	}
1552 1614
     	this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
@@ -2652,13 +2714,13 @@ private:
2652 2714
     	        this->gen_cond_branch(this->builder.CreateICmp(
2653 2715
     	            ICmpInst::ICMP_NE,
2654 2716
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2655
-    	            this->gen_const(32U, 0)),
2717
+    	            this->gen_const(64U, 0)),
2656 2718
     	            bb_then,
2657 2719
     	            bb_else);
2658 2720
     	        this->builder.SetInsertPoint(bb_then);
2659 2721
     	        {
2660
-    	            int32_t M1_val = (-1);
2661
-    	            uint32_t MMIN_val = (-1) << (32 - 1);
2722
+    	            uint32_t M1_val = - 1;
2723
+    	            uint32_t MMIN_val = - 1 << 32 - 1;
2662 2724
     	            {
2663 2725
     	                llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk);
2664 2726
     	                llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext);
@@ -2781,7 +2843,7 @@ private:
2781 2843
     	        this->gen_cond_branch(this->builder.CreateICmp(
2782 2844
     	            ICmpInst::ICMP_NE,
2783 2845
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2784
-    	            this->gen_const(32U, 0)),
2846
+    	            this->gen_const(64U, 0)),
2785 2847
     	            bb_then,
2786 2848
     	            bb_else);
2787 2849
     	        this->builder.SetInsertPoint(bb_then);
@@ -2848,13 +2910,13 @@ private:
2848 2910
     	        this->gen_cond_branch(this->builder.CreateICmp(
2849 2911
     	            ICmpInst::ICMP_NE,
2850 2912
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2851
-    	            this->gen_const(32U, 0)),
2913
+    	            this->gen_const(64U, 0)),
2852 2914
     	            bb_then,
2853 2915
     	            bb_else);
2854 2916
     	        this->builder.SetInsertPoint(bb_then);
2855 2917
     	        {
2856
-    	            int32_t M1_val = (-1);
2857
-    	            uint32_t MMIN_val = (-1) << (32 - 1);
2918
+    	            uint32_t M1_val = - 1;
2919
+    	            uint32_t MMIN_val = - 1 << 32 - 1;
2858 2920
     	            {
2859 2921
     	                llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk);
2860 2922
     	                llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext);
@@ -2895,7 +2957,7 @@ private:
2895 2957
     	                        this->builder.CreateBr(bbnext);
2896 2958
     	                        this->builder.SetInsertPoint(bb_else);
2897 2959
     	                        {
2898
-    	                            Value* Xtmp1_val = this->builder.CreateSRem(
2960
+    	                            Value* Xtmp1_val = this->builder.CreateURem(
2899 2961
     	                                this->gen_ext(
2900 2962
     	                                    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 3),
2901 2963
     	                                    32,
@@ -2914,7 +2976,7 @@ private:
2914 2976
     	                this->builder.CreateBr(bbnext);
2915 2977
     	                this->builder.SetInsertPoint(bb_else);
2916 2978
     	                {
2917
-    	                    Value* Xtmp2_val = this->builder.CreateSRem(
2979
+    	                    Value* Xtmp2_val = this->builder.CreateURem(
2918 2980
     	                        this->gen_ext(
2919 2981
     	                            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 2),
2920 2982
     	                            32,
@@ -2981,7 +3043,7 @@ private:
2981 3043
     	        this->gen_cond_branch(this->builder.CreateICmp(
2982 3044
     	            ICmpInst::ICMP_NE,
2983 3045
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2984
-    	            this->gen_const(32U, 0)),
3046
+    	            this->gen_const(64U, 0)),
2985 3047
     	            bb_then,
2986 3048
     	            bb_else);
2987 3049
     	        this->builder.SetInsertPoint(bb_then);
@@ -3098,7 +3160,7 @@ private:
3098 3160
     	    this->gen_cond_branch(this->builder.CreateICmp(
3099 3161
     	        ICmpInst::ICMP_NE,
3100 3162
     	        res1_val,
3101
-    	        this->gen_const(32U, 0)),
3163
+    	        this->gen_const(64U, 0)),
3102 3164
     	        bb_then,
3103 3165
     	        bbnext);
3104 3166
     	    this->builder.SetInsertPoint(bb_then);
@@ -3634,7 +3696,7 @@ private:
3634 3696
     	Value* Xtmp0_val = this->builder.CreateAdd(
3635 3697
     	    this->gen_reg_load(2 + traits<ARCH>::X0, 0),
3636 3698
     	    this->gen_const(32U, fld_imm_val));
3637
-    	this->builder.CreateStore(Xtmp0_val, get_reg_ptr((fld_rd_val + 8) + traits<ARCH>::X0), false);
3699
+    	this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + 8 + traits<ARCH>::X0), false);
3638 3700
     	this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
3639 3701
     	this->gen_sync(iss::POST_SYNC, 71);
3640 3702
     	bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
@@ -3667,10 +3729,10 @@ private:
3667 3729
     	pc=pc+2;
3668 3730
     	
3669 3731
     	Value* offs_val = this->builder.CreateAdd(
3670
-    	    this->gen_reg_load((fld_rs1_val + 8) + traits<ARCH>::X0, 0),
3732
+    	    this->gen_reg_load(fld_rs1_val + 8 + traits<ARCH>::X0, 0),
3671 3733
     	    this->gen_const(32U, fld_uimm_val));
3672 3734
     	Value* Xtmp0_val = this->gen_read_mem(traits<ARCH>::MEM, offs_val, 32/8);
3673
-    	this->builder.CreateStore(Xtmp0_val, get_reg_ptr((fld_rd_val + 8) + traits<ARCH>::X0), false);
3735
+    	this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + 8 + traits<ARCH>::X0), false);
3674 3736
     	this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
3675 3737
     	this->gen_sync(iss::POST_SYNC, 72);
3676 3738
     	bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
@@ -3703,9 +3765,9 @@ private:
3703 3765
     	pc=pc+2;
3704 3766
     	
3705 3767
     	Value* offs_val = this->builder.CreateAdd(
3706
-    	    this->gen_reg_load((fld_rs1_val + 8) + traits<ARCH>::X0, 0),
3768
+    	    this->gen_reg_load(fld_rs1_val + 8 + traits<ARCH>::X0, 0),
3707 3769
     	    this->gen_const(32U, fld_uimm_val));
3708
-    	Value* MEMtmp0_val = this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0);
3770
+    	Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0);
3709 3771
     	this->gen_write_mem(
3710 3772
     	    traits<ARCH>::MEM,
3711 3773
     	    offs_val,
@@ -3741,7 +3803,9 @@ private:
3741 3803
     	pc=pc+2;
3742 3804
     	
3743 3805
     	Value* Xtmp0_val = this->builder.CreateAdd(
3744
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
3806
+    	    this->gen_ext(
3807
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
3808
+    	        32, true),
3745 3809
     	    this->gen_const(32U, fld_imm_val));
3746 3810
     	this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rs1_val + traits<ARCH>::X0), false);
3747 3811
     	this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
@@ -3806,7 +3870,9 @@ private:
3806 3870
     	    this->gen_const(32U, 2));
3807 3871
     	this->builder.CreateStore(Xtmp0_val, get_reg_ptr(1 + traits<ARCH>::X0), false);
3808 3872
     	Value* PC_val = this->builder.CreateAdd(
3809
-    	    cur_pc_val,
3873
+    	    this->gen_ext(
3874
+    	        cur_pc_val,
3875
+    	        32, true),
3810 3876
     	    this->gen_const(32U, fld_imm_val));
3811 3877
     	this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
3812 3878
     	this->gen_sync(iss::POST_SYNC, 76);
@@ -3855,12 +3921,12 @@ private:
3855 3921
     	
3856 3922
     	this->gen_sync(iss::PRE_SYNC, 78);
3857 3923
     	
3858
-    	int32_t fld_imm_val = 0 | (bit_sub<2,5>(instr) << 12) | (signed_bit_sub<12,1>(instr) << 17);
3924
+    	int32_t fld_imm_val = 0 | (bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17);
3859 3925
     	uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
3860 3926
     	if(this->disass_enabled){
3861 3927
     	    /* generate console output when executing the command */
3862 3928
     	    boost::format ins_fmter("C.LUI x%1$d, 0x%2$05x");
3863
-    	    ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
3929
+    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_imm_val;
3864 3930
     	    std::vector<llvm::Value*> args {
3865 3931
     	        this->core_ptr,
3866 3932
     	        this->gen_const(64, pc.val),
@@ -3945,7 +4011,7 @@ private:
3945 4011
     	Value* cur_pc_val = this->gen_const(32, pc.val);
3946 4012
     	pc=pc+2;
3947 4013
     	
3948
-    	uint8_t rs1_idx_val = (fld_rs1_val + 8);
4014
+    	uint8_t rs1_idx_val = fld_rs1_val + 8;
3949 4015
     	Value* Xtmp0_val = this->builder.CreateLShr(
3950 4016
     	    this->gen_reg_load(rs1_idx_val + traits<ARCH>::X0, 0),
3951 4017
     	    this->gen_const(32U, fld_shamt_val));
@@ -3980,7 +4046,7 @@ private:
3980 4046
     	Value* cur_pc_val = this->gen_const(32, pc.val);
3981 4047
     	pc=pc+2;
3982 4048
     	
3983
-    	uint8_t rs1_idx_val = (fld_rs1_val + 8);
4049
+    	uint8_t rs1_idx_val = fld_rs1_val + 8;
3984 4050
     	Value* Xtmp0_val = this->builder.CreateAShr(
3985 4051
     	    this->gen_reg_load(rs1_idx_val + traits<ARCH>::X0, 0),
3986 4052
     	    this->gen_const(32U, fld_shamt_val));
@@ -3998,12 +4064,12 @@ private:
3998 4064
     	
3999 4065
     	this->gen_sync(iss::PRE_SYNC, 82);
4000 4066
     	
4001
-    	int8_t fld_imm_val = 0 | (bit_sub<2,5>(instr)) | (signed_bit_sub<12,1>(instr) << 5);
4067
+    	uint8_t fld_imm_val = 0 | (bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5);
4002 4068
     	uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr));
4003 4069
     	if(this->disass_enabled){
4004 4070
     	    /* generate console output when executing the command */
4005 4071
     	    boost::format ins_fmter("C.ANDI x(8+%1$d), 0x%2$05x");
4006
-    	    ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
4072
+    	    ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
4007 4073
     	    std::vector<llvm::Value*> args {
4008 4074
     	        this->core_ptr,
4009 4075
     	        this->gen_const(64, pc.val),
@@ -4015,7 +4081,7 @@ private:
4015 4081
     	Value* cur_pc_val = this->gen_const(32, pc.val);
4016 4082
     	pc=pc+2;
4017 4083
     	
4018
-    	uint8_t rs1_idx_val = (fld_rs1_val + 8);
4084
+    	uint8_t rs1_idx_val = fld_rs1_val + 8;
4019 4085
     	Value* Xtmp0_val = this->builder.CreateAnd(
4020 4086
     	    this->gen_reg_load(rs1_idx_val + traits<ARCH>::X0, 0),
4021 4087
     	    this->gen_const(32U, fld_imm_val));
@@ -4050,10 +4116,10 @@ private:
4050 4116
     	Value* cur_pc_val = this->gen_const(32, pc.val);
4051 4117
     	pc=pc+2;
4052 4118
     	
4053
-    	uint8_t rd_idx_val = (fld_rd_val + 8);
4119
+    	uint8_t rd_idx_val = fld_rd_val + 8;
4054 4120
     	Value* Xtmp0_val = this->builder.CreateSub(
4055
-    	    this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0),
4056
-    	    this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0));
4121
+    	     this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0),
4122
+    	     this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0));
4057 4123
     	this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits<ARCH>::X0), false);
4058 4124
     	this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
4059 4125
     	this->gen_sync(iss::POST_SYNC, 83);
@@ -4085,10 +4151,10 @@ private:
4085 4151
     	Value* cur_pc_val = this->gen_const(32, pc.val);
4086 4152
     	pc=pc+2;
4087 4153
     	
4088
-    	uint8_t rd_idx_val = (fld_rd_val + 8);
4154
+    	uint8_t rd_idx_val = fld_rd_val + 8;
4089 4155
     	Value* Xtmp0_val = this->builder.CreateXor(
4090 4156
     	    this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0),
4091
-    	    this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0));
4157
+    	    this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0));
4092 4158
     	this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits<ARCH>::X0), false);
4093 4159
     	this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
4094 4160
     	this->gen_sync(iss::POST_SYNC, 84);
@@ -4120,10 +4186,10 @@ private:
4120 4186
     	Value* cur_pc_val = this->gen_const(32, pc.val);
4121 4187
     	pc=pc+2;
4122 4188
     	
4123
-    	uint8_t rd_idx_val = (fld_rd_val + 8);
4189
+    	uint8_t rd_idx_val = fld_rd_val + 8;
4124 4190
     	Value* Xtmp0_val = this->builder.CreateOr(
4125 4191
     	    this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0),
4126
-    	    this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0));
4192
+    	    this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0));
4127 4193
     	this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits<ARCH>::X0), false);
4128 4194
     	this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
4129 4195
     	this->gen_sync(iss::POST_SYNC, 85);
@@ -4155,10 +4221,10 @@ private:
4155 4221
     	Value* cur_pc_val = this->gen_const(32, pc.val);
4156 4222
     	pc=pc+2;
4157 4223
     	
4158
-    	uint8_t rd_idx_val = (fld_rd_val + 8);
4224
+    	uint8_t rd_idx_val = fld_rd_val + 8;
4159 4225
     	Value* Xtmp0_val = this->builder.CreateAnd(
4160 4226
     	    this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0),
4161
-    	    this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0));
4227
+    	    this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0));
4162 4228
     	this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits<ARCH>::X0), false);
4163 4229
     	this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
4164 4230
     	this->gen_sync(iss::POST_SYNC, 86);
@@ -4190,7 +4256,9 @@ private:
4190 4256
     	pc=pc+2;
4191 4257
     	
4192 4258
     	Value* PC_val = this->builder.CreateAdd(
4193
-    	    cur_pc_val,
4259
+    	    this->gen_ext(
4260
+    	        cur_pc_val,
4261
+    	        32, true),
4194 4262
     	    this->gen_const(32U, fld_imm_val));
4195 4263
     	this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
4196 4264
     	this->gen_sync(iss::POST_SYNC, 87);
@@ -4224,10 +4292,12 @@ private:
4224 4292
     	Value* PC_val = this->gen_choose(
4225 4293
     	    this->builder.CreateICmp(
4226 4294
     	        ICmpInst::ICMP_EQ,
4227
-    	        this->gen_reg_load((fld_rs1_val + 8) + traits<ARCH>::X0, 0),
4295
+    	        this->gen_reg_load(fld_rs1_val + 8 + traits<ARCH>::X0, 0),
4228 4296
     	        this->gen_const(32U, 0)),
4229 4297
     	    this->builder.CreateAdd(
4230
-    	        cur_pc_val,
4298
+    	        this->gen_ext(
4299
+    	            cur_pc_val,
4300
+    	            32, true),
4231 4301
     	        this->gen_const(32U, fld_imm_val)),
4232 4302
     	    this->builder.CreateAdd(
4233 4303
     	        cur_pc_val,
@@ -4265,10 +4335,12 @@ private:
4265 4335
     	Value* PC_val = this->gen_choose(
4266 4336
     	    this->builder.CreateICmp(
4267 4337
     	        ICmpInst::ICMP_NE,
4268
-    	        this->gen_reg_load((fld_rs1_val + 8) + traits<ARCH>::X0, 0),
4338
+    	        this->gen_reg_load(fld_rs1_val + 8 + traits<ARCH>::X0, 0),
4269 4339
     	        this->gen_const(32U, 0)),
4270 4340
     	    this->builder.CreateAdd(
4271
-    	        cur_pc_val,
4341
+    	        this->gen_ext(
4342
+    	            cur_pc_val,
4343
+    	            32, true),
4272 4344
     	        this->gen_const(32U, fld_imm_val)),
4273 4345
     	    this->builder.CreateAdd(
4274 4346
     	        cur_pc_val,

+ 89
- 45
riscv/src/internal/vm_rv64ia.cpp View File

@@ -391,7 +391,9 @@ private:
391 391
     	pc=pc+4;
392 392
     	
393 393
     	Value* offs_val = this->builder.CreateAdd(
394
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
394
+    	    this->gen_ext(
395
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
396
+    	        64, true),
395 397
     	    this->gen_const(64U, fld_imm_val));
396 398
     	if(fld_rd_val != 0){
397 399
     	    Value* Xtmp0_val = this->gen_ext(
@@ -432,7 +434,9 @@ private:
432 434
     	pc=pc+4;
433 435
     	
434 436
     	Value* offs_val = this->builder.CreateAdd(
435
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
437
+    	    this->gen_ext(
438
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
439
+    	        64, true),
436 440
     	    this->gen_const(64U, fld_imm_val));
437 441
     	if(fld_rd_val != 0){
438 442
     	    Value* Xtmp0_val = this->gen_ext(
@@ -473,7 +477,9 @@ private:
473 477
     	pc=pc+4;
474 478
     	
475 479
     	Value* offs_val = this->builder.CreateAdd(
476
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
480
+    	    this->gen_ext(
481
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
482
+    	        64, true),
477 483
     	    this->gen_const(64U, fld_imm_val));
478 484
     	Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
479 485
     	this->gen_write_mem(
@@ -636,10 +642,12 @@ private:
636 642
     	
637 643
     	if(fld_rd_val != 0){
638 644
     	    Value* res_val = this->builder.CreateAdd(
639
-    	        this->builder.CreateTrunc(
640
-    	            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
641
-    	            this-> get_type(32) 
642
-    	        ),
645
+    	        this->gen_ext(
646
+    	            this->builder.CreateTrunc(
647
+    	                this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
648
+    	                this-> get_type(32) 
649
+    	            ),
650
+    	            32, true),
643 651
     	        this->gen_const(32U, fld_imm_val));
644 652
     	    Value* Xtmp0_val = this->gen_ext(
645 653
     	        res_val,
@@ -855,14 +863,14 @@ private:
855 863
     	
856 864
     	if(fld_rd_val != 0){
857 865
     	    Value* res_val = this->builder.CreateSub(
858
-    	        this->builder.CreateTrunc(
859
-    	            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
860
-    	            this-> get_type(32) 
861
-    	        ),
862
-    	        this->builder.CreateTrunc(
863
-    	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
864
-    	            this-> get_type(32) 
865
-    	        ));
866
+    	         this->builder.CreateTrunc(
867
+    	             this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
868
+    	             this-> get_type(32) 
869
+    	         ),
870
+    	         this->builder.CreateTrunc(
871
+    	             this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
872
+    	             this-> get_type(32) 
873
+    	         ));
866 874
     	    Value* Xtmp0_val = this->gen_ext(
867 875
     	        res_val,
868 876
     	        64,
@@ -901,7 +909,7 @@ private:
901 909
     	pc=pc+4;
902 910
     	
903 911
     	if(fld_rd_val != 0){
904
-    	    int32_t mask_val = 0x1f;
912
+    	    uint32_t mask_val = 0x1f;
905 913
     	    Value* count_val = this->builder.CreateAnd(
906 914
     	        this->builder.CreateTrunc(
907 915
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
@@ -952,7 +960,7 @@ private:
952 960
     	pc=pc+4;
953 961
     	
954 962
     	if(fld_rd_val != 0){
955
-    	    int32_t mask_val = 0x1f;
963
+    	    uint32_t mask_val = 0x1f;
956 964
     	    Value* count_val = this->builder.CreateAnd(
957 965
     	        this->builder.CreateTrunc(
958 966
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
@@ -1003,7 +1011,7 @@ private:
1003 1011
     	pc=pc+4;
1004 1012
     	
1005 1013
     	if(fld_rd_val != 0){
1006
-    	    int32_t mask_val = 0x1f;
1014
+    	    uint32_t mask_val = 0x1f;
1007 1015
     	    Value* count_val = this->builder.CreateAnd(
1008 1016
     	        this->builder.CreateTrunc(
1009 1017
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
@@ -1088,7 +1096,9 @@ private:
1088 1096
     	
1089 1097
     	if(fld_rd_val != 0){
1090 1098
     	    Value* Xtmp0_val = this->builder.CreateAdd(
1091
-    	        cur_pc_val,
1099
+    	        this->gen_ext(
1100
+    	            cur_pc_val,
1101
+    	            64, true),
1092 1102
     	        this->gen_const(64U, fld_imm_val));
1093 1103
     	    this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
1094 1104
     	}
@@ -1129,7 +1139,9 @@ private:
1129 1139
     	    this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
1130 1140
     	}
1131 1141
     	Value* PC_val = this->builder.CreateAdd(
1132
-    	    cur_pc_val,
1142
+    	    this->gen_ext(
1143
+    	        cur_pc_val,
1144
+    	        64, true),
1133 1145
     	    this->gen_const(64U, fld_imm_val));
1134 1146
     	this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
1135 1147
     	this->gen_sync(iss::POST_SYNC, 17);
@@ -1162,7 +1174,9 @@ private:
1162 1174
     	pc=pc+4;
1163 1175
     	
1164 1176
     	Value* new_pc_val = this->builder.CreateAdd(
1165
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1177
+    	    this->gen_ext(
1178
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1179
+    	        64, true),
1166 1180
     	    this->gen_const(64U, fld_imm_val));
1167 1181
     	Value* align_val = this->builder.CreateAnd(
1168 1182
     	    new_pc_val,
@@ -1235,7 +1249,9 @@ private:
1235 1249
     	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1236 1250
     	        this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
1237 1251
     	    this->builder.CreateAdd(
1238
-    	        cur_pc_val,
1252
+    	        this->gen_ext(
1253
+    	            cur_pc_val,
1254
+    	            64, true),
1239 1255
     	        this->gen_const(64U, fld_imm_val)),
1240 1256
     	    this->builder.CreateAdd(
1241 1257
     	        cur_pc_val,
@@ -1277,7 +1293,9 @@ private:
1277 1293
     	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1278 1294
     	        this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
1279 1295
     	    this->builder.CreateAdd(
1280
-    	        cur_pc_val,
1296
+    	        this->gen_ext(
1297
+    	            cur_pc_val,
1298
+    	            64, true),
1281 1299
     	        this->gen_const(64U, fld_imm_val)),
1282 1300
     	    this->builder.CreateAdd(
1283 1301
     	        cur_pc_val,
@@ -1323,7 +1341,9 @@ private:
1323 1341
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
1324 1342
     	            64, true)),
1325 1343
     	    this->builder.CreateAdd(
1326
-    	        cur_pc_val,
1344
+    	        this->gen_ext(
1345
+    	            cur_pc_val,
1346
+    	            64, true),
1327 1347
     	        this->gen_const(64U, fld_imm_val)),
1328 1348
     	    this->builder.CreateAdd(
1329 1349
     	        cur_pc_val,
@@ -1369,7 +1389,9 @@ private:
1369 1389
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
1370 1390
     	            64, true)),
1371 1391
     	    this->builder.CreateAdd(
1372
-    	        cur_pc_val,
1392
+    	        this->gen_ext(
1393
+    	            cur_pc_val,
1394
+    	            64, true),
1373 1395
     	        this->gen_const(64U, fld_imm_val)),
1374 1396
     	    this->builder.CreateAdd(
1375 1397
     	        cur_pc_val,
@@ -1411,7 +1433,9 @@ private:
1411 1433
     	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1412 1434
     	        this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
1413 1435
     	    this->builder.CreateAdd(
1414
-    	        cur_pc_val,
1436
+    	        this->gen_ext(
1437
+    	            cur_pc_val,
1438
+    	            64, true),
1415 1439
     	        this->gen_const(64U, fld_imm_val)),
1416 1440
     	    this->builder.CreateAdd(
1417 1441
     	        cur_pc_val,
@@ -1453,7 +1477,9 @@ private:
1453 1477
     	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1454 1478
     	        this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)),
1455 1479
     	    this->builder.CreateAdd(
1456
-    	        cur_pc_val,
1480
+    	        this->gen_ext(
1481
+    	            cur_pc_val,
1482
+    	            64, true),
1457 1483
     	        this->gen_const(64U, fld_imm_val)),
1458 1484
     	    this->builder.CreateAdd(
1459 1485
     	        cur_pc_val,
@@ -1490,7 +1516,9 @@ private:
1490 1516
     	pc=pc+4;
1491 1517
     	
1492 1518
     	Value* offs_val = this->builder.CreateAdd(
1493
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1519
+    	    this->gen_ext(
1520
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1521
+    	        64, true),
1494 1522
     	    this->gen_const(64U, fld_imm_val));
1495 1523
     	if(fld_rd_val != 0){
1496 1524
     	    Value* Xtmp0_val = this->gen_ext(
@@ -1531,7 +1559,9 @@ private:
1531 1559
     	pc=pc+4;
1532 1560
     	
1533 1561
     	Value* offs_val = this->builder.CreateAdd(
1534
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1562
+    	    this->gen_ext(
1563
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1564
+    	        64, true),
1535 1565
     	    this->gen_const(64U, fld_imm_val));
1536 1566
     	if(fld_rd_val != 0){
1537 1567
     	    Value* Xtmp0_val = this->gen_ext(
@@ -1572,7 +1602,9 @@ private:
1572 1602
     	pc=pc+4;
1573 1603
     	
1574 1604
     	Value* offs_val = this->builder.CreateAdd(
1575
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1605
+    	    this->gen_ext(
1606
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1607
+    	        64, true),
1576 1608
     	    this->gen_const(64U, fld_imm_val));
1577 1609
     	if(fld_rd_val != 0){
1578 1610
     	    Value* Xtmp0_val = this->gen_ext(
@@ -1613,7 +1645,9 @@ private:
1613 1645
     	pc=pc+4;
1614 1646
     	
1615 1647
     	Value* offs_val = this->builder.CreateAdd(
1616
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1648
+    	    this->gen_ext(
1649
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1650
+    	        64, true),
1617 1651
     	    this->gen_const(64U, fld_imm_val));
1618 1652
     	if(fld_rd_val != 0){
1619 1653
     	    Value* Xtmp0_val = this->gen_ext(
@@ -1654,7 +1688,9 @@ private:
1654 1688
     	pc=pc+4;
1655 1689
     	
1656 1690
     	Value* offs_val = this->builder.CreateAdd(
1657
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1691
+    	    this->gen_ext(
1692
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1693
+    	        64, true),
1658 1694
     	    this->gen_const(64U, fld_imm_val));
1659 1695
     	if(fld_rd_val != 0){
1660 1696
     	    Value* Xtmp0_val = this->gen_ext(
@@ -1695,7 +1731,9 @@ private:
1695 1731
     	pc=pc+4;
1696 1732
     	
1697 1733
     	Value* offs_val = this->builder.CreateAdd(
1698
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1734
+    	    this->gen_ext(
1735
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1736
+    	        64, true),
1699 1737
     	    this->gen_const(64U, fld_imm_val));
1700 1738
     	Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
1701 1739
     	this->gen_write_mem(
@@ -1734,7 +1772,9 @@ private:
1734 1772
     	pc=pc+4;
1735 1773
     	
1736 1774
     	Value* offs_val = this->builder.CreateAdd(
1737
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1775
+    	    this->gen_ext(
1776
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1777
+    	        64, true),
1738 1778
     	    this->gen_const(64U, fld_imm_val));
1739 1779
     	Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
1740 1780
     	this->gen_write_mem(
@@ -1773,7 +1813,9 @@ private:
1773 1813
     	pc=pc+4;
1774 1814
     	
1775 1815
     	Value* offs_val = this->builder.CreateAdd(
1776
-    	    this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1816
+    	    this->gen_ext(
1817
+    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1818
+    	        64, true),
1777 1819
     	    this->gen_const(64U, fld_imm_val));
1778 1820
     	Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0);
1779 1821
     	this->gen_write_mem(
@@ -1813,7 +1855,9 @@ private:
1813 1855
     	
1814 1856
     	if(fld_rd_val != 0){
1815 1857
     	    Value* Xtmp0_val = this->builder.CreateAdd(
1816
-    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1858
+    	        this->gen_ext(
1859
+    	            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
1860
+    	            64, true),
1817 1861
     	        this->gen_const(64U, fld_imm_val));
1818 1862
     	    this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
1819 1863
     	}
@@ -1919,11 +1963,11 @@ private:
1919 1963
     	
1920 1964
     	uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
1921 1965
     	uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
1922
-    	int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
1966
+    	uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
1923 1967
     	if(this->disass_enabled){
1924 1968
     	    /* generate console output when executing the command */
1925 1969
     	    boost::format ins_fmter("XORI x%1$d, x%2$d, %3%");
1926
-    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
1970
+    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
1927 1971
     	    std::vector<llvm::Value*> args {
1928 1972
     	        this->core_ptr,
1929 1973
     	        this->gen_const(64, pc.val),
@@ -1956,11 +2000,11 @@ private:
1956 2000
     	
1957 2001
     	uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
1958 2002
     	uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
1959
-    	int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
2003
+    	uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
1960 2004
     	if(this->disass_enabled){
1961 2005
     	    /* generate console output when executing the command */
1962 2006
     	    boost::format ins_fmter("ORI x%1$d, x%2$d, %3%");
1963
-    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
2007
+    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
1964 2008
     	    std::vector<llvm::Value*> args {
1965 2009
     	        this->core_ptr,
1966 2010
     	        this->gen_const(64, pc.val),
@@ -1993,11 +2037,11 @@ private:
1993 2037
     	
1994 2038
     	uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
1995 2039
     	uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
1996
-    	int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr));
2040
+    	uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr));
1997 2041
     	if(this->disass_enabled){
1998 2042
     	    /* generate console output when executing the command */
1999 2043
     	    boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%");
2000
-    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
2044
+    	    ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val;
2001 2045
     	    std::vector<llvm::Value*> args {
2002 2046
     	        this->core_ptr,
2003 2047
     	        this->gen_const(64, pc.val),
@@ -2085,8 +2129,8 @@ private:
2085 2129
     	
2086 2130
     	if(fld_rd_val != 0){
2087 2131
     	    Value* Xtmp0_val = this->builder.CreateSub(
2088
-    	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2089
-    	        this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
2132
+    	         this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2133
+    	         this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0));
2090 2134
     	    this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
2091 2135
     	}
2092 2136
     	this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
@@ -3639,7 +3683,7 @@ private:
3639 3683
     	    this->gen_cond_branch(this->builder.CreateICmp(
3640 3684
     	        ICmpInst::ICMP_NE,
3641 3685
     	        res1_val,
3642
-    	        this->gen_const(32U, 0)),
3686
+    	        this->gen_const(64U, 0)),
3643 3687
     	        bb_then,
3644 3688
     	        bbnext);
3645 3689
     	    this->builder.SetInsertPoint(bb_then);