|
|
@ -451,7 +451,9 @@ private: |
|
|
|
|
|
|
|
if(fld_rd_val != 0){ |
|
|
|
Value* Xtmp0_val = this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_ext( |
|
|
|
cur_pc_val, |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false); |
|
|
|
} |
|
|
@ -492,7 +494,9 @@ private: |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false); |
|
|
|
} |
|
|
|
Value* PC_val = this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_ext( |
|
|
|
cur_pc_val, |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false); |
|
|
|
this->gen_sync(iss::POST_SYNC, 2); |
|
|
@ -524,19 +528,47 @@ private: |
|
|
|
Value* cur_pc_val = this->gen_const(32, pc.val); |
|
|
|
pc=pc+4; |
|
|
|
|
|
|
|
if(fld_rd_val != 0){ |
|
|
|
Value* Xtmp0_val = this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_const(32U, 4)); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false); |
|
|
|
} |
|
|
|
Value* ret_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
Value* new_pc_val = this->builder.CreateAdd( |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
Value* PC_val = this->builder.CreateAnd( |
|
|
|
ret_val, |
|
|
|
this->builder.CreateNot(this->gen_const(32U, 0x1))); |
|
|
|
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false); |
|
|
|
Value* align_val = this->builder.CreateAnd( |
|
|
|
new_pc_val, |
|
|
|
this->gen_const(32U, 0x1)); |
|
|
|
{ |
|
|
|
llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); |
|
|
|
llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); |
|
|
|
llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); |
|
|
|
// this->builder.SetInsertPoint(bb);
|
|
|
|
this->gen_cond_branch(this->builder.CreateICmp( |
|
|
|
ICmpInst::ICMP_NE, |
|
|
|
align_val, |
|
|
|
this->gen_const(64U, 0)), |
|
|
|
bb_then, |
|
|
|
bb_else); |
|
|
|
this->builder.SetInsertPoint(bb_then); |
|
|
|
{ |
|
|
|
this->gen_raise_trap(0, 0); |
|
|
|
} |
|
|
|
this->builder.CreateBr(bbnext); |
|
|
|
this->builder.SetInsertPoint(bb_else); |
|
|
|
{ |
|
|
|
if(fld_rd_val != 0){ |
|
|
|
Value* Xtmp0_val = this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_const(32U, 4)); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false); |
|
|
|
} |
|
|
|
Value* PC_val = this->builder.CreateAnd( |
|
|
|
new_pc_val, |
|
|
|
this->builder.CreateNot(this->gen_const(32U, 0x1))); |
|
|
|
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false); |
|
|
|
} |
|
|
|
this->builder.CreateBr(bbnext); |
|
|
|
bb=bbnext; |
|
|
|
} |
|
|
|
this->builder.SetInsertPoint(bb); |
|
|
|
this->gen_sync(iss::POST_SYNC, 3); |
|
|
|
this->gen_trap_check(this->leave_blk); |
|
|
|
return std::make_tuple(iss::vm::BRANCH, nullptr); |
|
|
@ -572,7 +604,9 @@ private: |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_ext( |
|
|
|
cur_pc_val, |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
@ -614,7 +648,9 @@ private: |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_ext( |
|
|
|
cur_pc_val, |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
@ -660,7 +696,9 @@ private: |
|
|
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0), |
|
|
|
32, true)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_ext( |
|
|
|
cur_pc_val, |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
@ -706,7 +744,9 @@ private: |
|
|
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0), |
|
|
|
32, true)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_ext( |
|
|
|
cur_pc_val, |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
@ -748,7 +788,9 @@ private: |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_ext( |
|
|
|
cur_pc_val, |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
@ -790,7 +832,9 @@ private: |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_ext( |
|
|
|
cur_pc_val, |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
@ -827,7 +871,9 @@ private: |
|
|
|
pc=pc+4; |
|
|
|
|
|
|
|
Value* offs_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
if(fld_rd_val != 0){ |
|
|
|
Value* Xtmp0_val = this->gen_ext( |
|
|
@ -868,7 +914,9 @@ private: |
|
|
|
pc=pc+4; |
|
|
|
|
|
|
|
Value* offs_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
if(fld_rd_val != 0){ |
|
|
|
Value* Xtmp0_val = this->gen_ext( |
|
|
@ -909,7 +957,9 @@ private: |
|
|
|
pc=pc+4; |
|
|
|
|
|
|
|
Value* offs_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
if(fld_rd_val != 0){ |
|
|
|
Value* Xtmp0_val = this->gen_ext( |
|
|
@ -950,7 +1000,9 @@ private: |
|
|
|
pc=pc+4; |
|
|
|
|
|
|
|
Value* offs_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
if(fld_rd_val != 0){ |
|
|
|
Value* Xtmp0_val = this->gen_ext( |
|
|
@ -991,7 +1043,9 @@ private: |
|
|
|
pc=pc+4; |
|
|
|
|
|
|
|
Value* offs_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
if(fld_rd_val != 0){ |
|
|
|
Value* Xtmp0_val = this->gen_ext( |
|
|
@ -1032,7 +1086,9 @@ private: |
|
|
|
pc=pc+4; |
|
|
|
|
|
|
|
Value* offs_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0); |
|
|
|
this->gen_write_mem( |
|
|
@ -1071,7 +1127,9 @@ private: |
|
|
|
pc=pc+4; |
|
|
|
|
|
|
|
Value* offs_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0); |
|
|
|
this->gen_write_mem( |
|
|
@ -1110,7 +1168,9 @@ private: |
|
|
|
pc=pc+4; |
|
|
|
|
|
|
|
Value* offs_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0); |
|
|
|
this->gen_write_mem( |
|
|
@ -1150,7 +1210,9 @@ private: |
|
|
|
|
|
|
|
if(fld_rd_val != 0){ |
|
|
|
Value* Xtmp0_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false); |
|
|
|
} |
|
|
@ -1256,11 +1318,11 @@ private: |
|
|
|
|
|
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); |
|
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); |
|
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); |
|
|
|
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr)); |
|
|
|
if(this->disass_enabled){ |
|
|
|
/* generate console output when executing the command */ |
|
|
|
boost::format ins_fmter("XORI x%1$d, x%2$d, %3%"); |
|
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; |
|
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val; |
|
|
|
std::vector<llvm::Value*> args { |
|
|
|
this->core_ptr, |
|
|
|
this->gen_const(64, pc.val), |
|
|
@ -1293,11 +1355,11 @@ private: |
|
|
|
|
|
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); |
|
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); |
|
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); |
|
|
|
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr)); |
|
|
|
if(this->disass_enabled){ |
|
|
|
/* generate console output when executing the command */ |
|
|
|
boost::format ins_fmter("ORI x%1$d, x%2$d, %3%"); |
|
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; |
|
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val; |
|
|
|
std::vector<llvm::Value*> args { |
|
|
|
this->core_ptr, |
|
|
|
this->gen_const(64, pc.val), |
|
|
@ -1330,11 +1392,11 @@ private: |
|
|
|
|
|
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); |
|
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr)); |
|
|
|
int16_t fld_imm_val = 0 | (signed_bit_sub<20,12>(instr)); |
|
|
|
uint16_t fld_imm_val = 0 | (bit_sub<20,12>(instr)); |
|
|
|
if(this->disass_enabled){ |
|
|
|
/* generate console output when executing the command */ |
|
|
|
boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%"); |
|
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; |
|
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val; |
|
|
|
std::vector<llvm::Value*> args { |
|
|
|
this->core_ptr, |
|
|
|
this->gen_const(64, pc.val), |
|
|
@ -1545,8 +1607,8 @@ private: |
|
|
|
|
|
|
|
if(fld_rd_val != 0){ |
|
|
|
Value* Xtmp0_val = this->builder.CreateSub( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)); |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0)); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false); |
|
|
|
} |
|
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC); |
|
|
@ -2652,13 +2714,13 @@ private: |
|
|
|
this->gen_cond_branch(this->builder.CreateICmp( |
|
|
|
ICmpInst::ICMP_NE, |
|
|
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_const(32U, 0)), |
|
|
|
this->gen_const(64U, 0)), |
|
|
|
bb_then, |
|
|
|
bb_else); |
|
|
|
this->builder.SetInsertPoint(bb_then); |
|
|
|
{ |
|
|
|
int32_t M1_val = (-1); |
|
|
|
uint32_t MMIN_val = (-1) << (32 - 1); |
|
|
|
uint32_t M1_val = - 1; |
|
|
|
uint32_t MMIN_val = - 1 << 32 - 1; |
|
|
|
{ |
|
|
|
llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); |
|
|
|
llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); |
|
|
@ -2781,7 +2843,7 @@ private: |
|
|
|
this->gen_cond_branch(this->builder.CreateICmp( |
|
|
|
ICmpInst::ICMP_NE, |
|
|
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_const(32U, 0)), |
|
|
|
this->gen_const(64U, 0)), |
|
|
|
bb_then, |
|
|
|
bb_else); |
|
|
|
this->builder.SetInsertPoint(bb_then); |
|
|
@ -2848,13 +2910,13 @@ private: |
|
|
|
this->gen_cond_branch(this->builder.CreateICmp( |
|
|
|
ICmpInst::ICMP_NE, |
|
|
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_const(32U, 0)), |
|
|
|
this->gen_const(64U, 0)), |
|
|
|
bb_then, |
|
|
|
bb_else); |
|
|
|
this->builder.SetInsertPoint(bb_then); |
|
|
|
{ |
|
|
|
int32_t M1_val = (-1); |
|
|
|
uint32_t MMIN_val = (-1) << (32 - 1); |
|
|
|
uint32_t M1_val = - 1; |
|
|
|
uint32_t MMIN_val = - 1 << 32 - 1; |
|
|
|
{ |
|
|
|
llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); |
|
|
|
llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); |
|
|
@ -2895,7 +2957,7 @@ private: |
|
|
|
this->builder.CreateBr(bbnext); |
|
|
|
this->builder.SetInsertPoint(bb_else); |
|
|
|
{ |
|
|
|
Value* Xtmp1_val = this->builder.CreateSRem( |
|
|
|
Value* Xtmp1_val = this->builder.CreateURem( |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 3), |
|
|
|
32, |
|
|
@ -2914,7 +2976,7 @@ private: |
|
|
|
this->builder.CreateBr(bbnext); |
|
|
|
this->builder.SetInsertPoint(bb_else); |
|
|
|
{ |
|
|
|
Value* Xtmp2_val = this->builder.CreateSRem( |
|
|
|
Value* Xtmp2_val = this->builder.CreateURem( |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 2), |
|
|
|
32, |
|
|
@ -2981,7 +3043,7 @@ private: |
|
|
|
this->gen_cond_branch(this->builder.CreateICmp( |
|
|
|
ICmpInst::ICMP_NE, |
|
|
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_const(32U, 0)), |
|
|
|
this->gen_const(64U, 0)), |
|
|
|
bb_then, |
|
|
|
bb_else); |
|
|
|
this->builder.SetInsertPoint(bb_then); |
|
|
@ -3098,7 +3160,7 @@ private: |
|
|
|
this->gen_cond_branch(this->builder.CreateICmp( |
|
|
|
ICmpInst::ICMP_NE, |
|
|
|
res1_val, |
|
|
|
this->gen_const(32U, 0)), |
|
|
|
this->gen_const(64U, 0)), |
|
|
|
bb_then, |
|
|
|
bbnext); |
|
|
|
this->builder.SetInsertPoint(bb_then); |
|
|
@ -3634,7 +3696,7 @@ private: |
|
|
|
Value* Xtmp0_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load(2 + traits<ARCH>::X0, 0), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr((fld_rd_val + 8) + traits<ARCH>::X0), false); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + 8 + traits<ARCH>::X0), false); |
|
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC); |
|
|
|
this->gen_sync(iss::POST_SYNC, 71); |
|
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ |
|
|
@ -3667,10 +3729,10 @@ private: |
|
|
|
pc=pc+2; |
|
|
|
|
|
|
|
Value* offs_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load((fld_rs1_val + 8) + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load(fld_rs1_val + 8 + traits<ARCH>::X0, 0), |
|
|
|
this->gen_const(32U, fld_uimm_val)); |
|
|
|
Value* Xtmp0_val = this->gen_read_mem(traits<ARCH>::MEM, offs_val, 32/8); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr((fld_rd_val + 8) + traits<ARCH>::X0), false); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + 8 + traits<ARCH>::X0), false); |
|
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC); |
|
|
|
this->gen_sync(iss::POST_SYNC, 72); |
|
|
|
bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ |
|
|
@ -3703,9 +3765,9 @@ private: |
|
|
|
pc=pc+2; |
|
|
|
|
|
|
|
Value* offs_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load((fld_rs1_val + 8) + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load(fld_rs1_val + 8 + traits<ARCH>::X0, 0), |
|
|
|
this->gen_const(32U, fld_uimm_val)); |
|
|
|
Value* MEMtmp0_val = this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0); |
|
|
|
Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0); |
|
|
|
this->gen_write_mem( |
|
|
|
traits<ARCH>::MEM, |
|
|
|
offs_val, |
|
|
@ -3741,7 +3803,9 @@ private: |
|
|
|
pc=pc+2; |
|
|
|
|
|
|
|
Value* Xtmp0_val = this->builder.CreateAdd( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_ext( |
|
|
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0), |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rs1_val + traits<ARCH>::X0), false); |
|
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC); |
|
|
@ -3806,7 +3870,9 @@ private: |
|
|
|
this->gen_const(32U, 2)); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(1 + traits<ARCH>::X0), false); |
|
|
|
Value* PC_val = this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_ext( |
|
|
|
cur_pc_val, |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false); |
|
|
|
this->gen_sync(iss::POST_SYNC, 76); |
|
|
@ -3855,12 +3921,12 @@ private: |
|
|
|
|
|
|
|
this->gen_sync(iss::PRE_SYNC, 78); |
|
|
|
|
|
|
|
int32_t fld_imm_val = 0 | (bit_sub<2,5>(instr) << 12) | (signed_bit_sub<12,1>(instr) << 17); |
|
|
|
int32_t fld_imm_val = 0 | (bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17); |
|
|
|
uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr)); |
|
|
|
if(this->disass_enabled){ |
|
|
|
/* generate console output when executing the command */ |
|
|
|
boost::format ins_fmter("C.LUI x%1$d, 0x%2$05x"); |
|
|
|
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val; |
|
|
|
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_imm_val; |
|
|
|
std::vector<llvm::Value*> args { |
|
|
|
this->core_ptr, |
|
|
|
this->gen_const(64, pc.val), |
|
|
@ -3945,7 +4011,7 @@ private: |
|
|
|
Value* cur_pc_val = this->gen_const(32, pc.val); |
|
|
|
pc=pc+2; |
|
|
|
|
|
|
|
uint8_t rs1_idx_val = (fld_rs1_val + 8); |
|
|
|
uint8_t rs1_idx_val = fld_rs1_val + 8; |
|
|
|
Value* Xtmp0_val = this->builder.CreateLShr( |
|
|
|
this->gen_reg_load(rs1_idx_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_const(32U, fld_shamt_val)); |
|
|
@ -3980,7 +4046,7 @@ private: |
|
|
|
Value* cur_pc_val = this->gen_const(32, pc.val); |
|
|
|
pc=pc+2; |
|
|
|
|
|
|
|
uint8_t rs1_idx_val = (fld_rs1_val + 8); |
|
|
|
uint8_t rs1_idx_val = fld_rs1_val + 8; |
|
|
|
Value* Xtmp0_val = this->builder.CreateAShr( |
|
|
|
this->gen_reg_load(rs1_idx_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_const(32U, fld_shamt_val)); |
|
|
@ -3998,12 +4064,12 @@ private: |
|
|
|
|
|
|
|
this->gen_sync(iss::PRE_SYNC, 82); |
|
|
|
|
|
|
|
int8_t fld_imm_val = 0 | (bit_sub<2,5>(instr)) | (signed_bit_sub<12,1>(instr) << 5); |
|
|
|
uint8_t fld_imm_val = 0 | (bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5); |
|
|
|
uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr)); |
|
|
|
if(this->disass_enabled){ |
|
|
|
/* generate console output when executing the command */ |
|
|
|
boost::format ins_fmter("C.ANDI x(8+%1$d), 0x%2$05x"); |
|
|
|
ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val; |
|
|
|
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_imm_val; |
|
|
|
std::vector<llvm::Value*> args { |
|
|
|
this->core_ptr, |
|
|
|
this->gen_const(64, pc.val), |
|
|
@ -4015,7 +4081,7 @@ private: |
|
|
|
Value* cur_pc_val = this->gen_const(32, pc.val); |
|
|
|
pc=pc+2; |
|
|
|
|
|
|
|
uint8_t rs1_idx_val = (fld_rs1_val + 8); |
|
|
|
uint8_t rs1_idx_val = fld_rs1_val + 8; |
|
|
|
Value* Xtmp0_val = this->builder.CreateAnd( |
|
|
|
this->gen_reg_load(rs1_idx_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
@ -4050,10 +4116,10 @@ private: |
|
|
|
Value* cur_pc_val = this->gen_const(32, pc.val); |
|
|
|
pc=pc+2; |
|
|
|
|
|
|
|
uint8_t rd_idx_val = (fld_rd_val + 8); |
|
|
|
uint8_t rd_idx_val = fld_rd_val + 8; |
|
|
|
Value* Xtmp0_val = this->builder.CreateSub( |
|
|
|
this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0)); |
|
|
|
this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0)); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits<ARCH>::X0), false); |
|
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC); |
|
|
|
this->gen_sync(iss::POST_SYNC, 83); |
|
|
@ -4085,10 +4151,10 @@ private: |
|
|
|
Value* cur_pc_val = this->gen_const(32, pc.val); |
|
|
|
pc=pc+2; |
|
|
|
|
|
|
|
uint8_t rd_idx_val = (fld_rd_val + 8); |
|
|
|
uint8_t rd_idx_val = fld_rd_val + 8; |
|
|
|
Value* Xtmp0_val = this->builder.CreateXor( |
|
|
|
this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0)); |
|
|
|
this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0)); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits<ARCH>::X0), false); |
|
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC); |
|
|
|
this->gen_sync(iss::POST_SYNC, 84); |
|
|
@ -4120,10 +4186,10 @@ private: |
|
|
|
Value* cur_pc_val = this->gen_const(32, pc.val); |
|
|
|
pc=pc+2; |
|
|
|
|
|
|
|
uint8_t rd_idx_val = (fld_rd_val + 8); |
|
|
|
uint8_t rd_idx_val = fld_rd_val + 8; |
|
|
|
Value* Xtmp0_val = this->builder.CreateOr( |
|
|
|
this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0)); |
|
|
|
this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0)); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits<ARCH>::X0), false); |
|
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC); |
|
|
|
this->gen_sync(iss::POST_SYNC, 85); |
|
|
@ -4155,10 +4221,10 @@ private: |
|
|
|
Value* cur_pc_val = this->gen_const(32, pc.val); |
|
|
|
pc=pc+2; |
|
|
|
|
|
|
|
uint8_t rd_idx_val = (fld_rd_val + 8); |
|
|
|
uint8_t rd_idx_val = fld_rd_val + 8; |
|
|
|
Value* Xtmp0_val = this->builder.CreateAnd( |
|
|
|
this->gen_reg_load(rd_idx_val + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load((fld_rs2_val + 8) + traits<ARCH>::X0, 0)); |
|
|
|
this->gen_reg_load(fld_rs2_val + 8 + traits<ARCH>::X0, 0)); |
|
|
|
this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits<ARCH>::X0), false); |
|
|
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC); |
|
|
|
this->gen_sync(iss::POST_SYNC, 86); |
|
|
@ -4190,7 +4256,9 @@ private: |
|
|
|
pc=pc+2; |
|
|
|
|
|
|
|
Value* PC_val = this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_ext( |
|
|
|
cur_pc_val, |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)); |
|
|
|
this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false); |
|
|
|
this->gen_sync(iss::POST_SYNC, 87); |
|
|
@ -4224,10 +4292,12 @@ private: |
|
|
|
Value* PC_val = this->gen_choose( |
|
|
|
this->builder.CreateICmp( |
|
|
|
ICmpInst::ICMP_EQ, |
|
|
|
this->gen_reg_load((fld_rs1_val + 8) + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load(fld_rs1_val + 8 + traits<ARCH>::X0, 0), |
|
|
|
this->gen_const(32U, 0)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_ext( |
|
|
|
cur_pc_val, |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
@ -4265,10 +4335,12 @@ private: |
|
|
|
Value* PC_val = this->gen_choose( |
|
|
|
this->builder.CreateICmp( |
|
|
|
ICmpInst::ICMP_NE, |
|
|
|
this->gen_reg_load((fld_rs1_val + 8) + traits<ARCH>::X0, 0), |
|
|
|
this->gen_reg_load(fld_rs1_val + 8 + traits<ARCH>::X0, 0), |
|
|
|
this->gen_const(32U, 0)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|
this->gen_ext( |
|
|
|
cur_pc_val, |
|
|
|
32, true), |
|
|
|
this->gen_const(32U, fld_imm_val)), |
|
|
|
this->builder.CreateAdd( |
|
|
|
cur_pc_val, |
|
|
|