Browse Source

Added RV32F extension, fixed RV32M bugs

Eyck Jentzsch 1 year ago
parent
commit
48ad30dcae

+ 9
- 1
.cproject View File

@@ -13,7 +13,7 @@
13 13
 				</extensions>
14 14
 			</storageModule>
15 15
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
16
-				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="cdt.managedbuild.config.gnu.exe.debug.1751741082" name="Debug" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=" parent="cdt.managedbuild.config.gnu.exe.debug">
16
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="cdt.managedbuild.config.gnu.exe.debug.1751741082" name="Debug" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=" parent="cdt.managedbuild.config.gnu.exe.debug">
17 17
 					<folderInfo id="cdt.managedbuild.config.gnu.exe.debug.1751741082." name="/" resourcePath="">
18 18
 						<toolChain id="cdt.managedbuild.toolchain.gnu.exe.debug.1289745146" name="Linux GCC" superClass="cdt.managedbuild.toolchain.gnu.exe.debug">
19 19
 							<targetPlatform binaryParser="org.eclipse.cdt.core.GNU_ELF;org.eclipse.cdt.core.ELF" id="cdt.managedbuild.target.gnu.platform.exe.debug.1460698591" name="Debug Platform" superClass="cdt.managedbuild.target.gnu.platform.exe.debug"/>
@@ -46,6 +46,13 @@
46 46
 			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
47 47
 			<storageModule buildDir="build/${ConfigName}" moduleId="de.marw.cdt.cmake.core.settings">
48 48
 				<options/>
49
+				<linux command="cmake" generator="UnixMakefiles" use-default="true">
50
+					<defs>
51
+						<def name="CMAKE_VERBOSE_MAKEFILE" type="BOOL" val="OFF"/>
52
+					</defs>
53
+				</linux>
54
+				<win32 command="cmake" generator="MinGWMakefiles" use-default="true">
55
+				</win32>
49 56
 			</storageModule>
50 57
 		</cconfiguration>
51 58
 		<cconfiguration id="cdt.managedbuild.config.gnu.exe.release.1745230171">
@@ -177,4 +184,5 @@
177 184
 		</configuration>
178 185
 	</storageModule>
179 186
 	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
187
+	<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
180 188
 </cproject>

+ 11
- 0
.settings/org.eclipse.cdt.core.prefs View File

@@ -0,0 +1,11 @@
1
+eclipse.preferences.version=1
2
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/LLVM_HOME/delimiter=\:
3
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/LLVM_HOME/operation=replace
4
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/LLVM_HOME/value=/usr/lib/llvm-4.0
5
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/append=true
6
+environment/project/cdt.managedbuild.config.gnu.exe.debug.1751741082/appendContributed=true
7
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/delimiter=\:
8
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/operation=append
9
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/LLVM_HOME/value=/usr/lib/llvm-6.0
10
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/append=true
11
+environment/project/cdt.managedbuild.config.gnu.exe.release.1745230171/appendContributed=true

+ 1
- 1
dbt-core

@@ -1 +1 @@
1
-Subproject commit bc05d40184ccb8871afa61620fe2c67ce2951fa4
1
+Subproject commit d9512853b22e869938013c8dc0c6678a92d52c0e

+ 3
- 3
etc/CoreDSL generator.launch View File

@@ -2,7 +2,7 @@
2 2
 <launchConfiguration type="org.eclipse.ui.externaltools.ProgramLaunchConfigurationType">
3 3
 <stringAttribute key="org.eclipse.debug.core.ATTR_REFRESH_SCOPE" value="${working_set:&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;resources&gt;&#10;&lt;item path=&quot;/dbt-riscv/riscv&quot; type=&quot;2&quot;/&gt;&#10;&lt;/resources&gt;}"/>
4 4
 <stringAttribute key="org.eclipse.ui.externaltools.ATTR_LAUNCH_CONFIGURATION_BUILD_SCOPE" value="${none}"/>
5
-<stringAttribute key="org.eclipse.ui.externaltools.ATTR_LOCATION" value="/usr/lib/jvm/java-8-oracle/bin/java"/>
6
-<stringAttribute key="org.eclipse.ui.externaltools.ATTR_TOOL_ARGUMENTS" value="-jar ${env_var:HOME}/git/JIT-ISS-CoreDsl/com.minres.coredsl.standalone/target/com.minres.coredsl.standalone-1.0.0-SNAPSHOT.jar&#10;-i=${project_loc:dbt-riscv}/riscv/incl/iss/arch&#10;-s=${project_loc:dbt-riscv}/riscv/src/iss&#10;-v=${project_loc:dbt-riscv}/riscv/src/internal&#10;-t=${project_loc:dbt-riscv}/riscv/gen_input/templates&#10;${project_loc:dbt-riscv}/riscv/gen_input/minres_rv.core_desc"/>
7
-<stringAttribute key="org.eclipse.ui.externaltools.ATTR_WORKING_DIRECTORY" value="${workspace_loc:/dbt-riscv}/riscv/gen_input"/>
5
+<stringAttribute key="org.eclipse.ui.externaltools.ATTR_LOCATION" value="/usr/bin/java"/>
6
+<stringAttribute key="org.eclipse.ui.externaltools.ATTR_TOOL_ARGUMENTS" value="-Xmx1G -jar ${env_var:HOME}/git/JIT-ISS-CoreDsl/com.minres.coredsl.standalone/target/com.minres.coredsl.standalone-1.0.0-SNAPSHOT.jar&#10;-i=${project_loc:DBT-RISE-RISCV}/riscv/incl/iss/arch&#10;-s=${project_loc:DBT-RISE-RISCV}/riscv/src/iss&#10;-v=${project_loc:DBT-RISE-RISCV}/riscv/src/internal&#10;-t=${project_loc:DBT-RISE-RISCV}/riscv/gen_input/templates&#10;${project_loc:DBT-RISE-RISCV}/riscv/gen_input/minres_rv.core_desc"/>
7
+<stringAttribute key="org.eclipse.ui.externaltools.ATTR_WORKING_DIRECTORY" value="${workspace_loc:/DBT-RISE-RISCV}/riscv/gen_input"/>
8 8
 </launchConfiguration>

+ 61
- 16
riscv/gen_input/RV32C.core_desc View File

@@ -1,6 +1,6 @@
1 1
 import "RV32IBase.core_desc"
2 2
 
3
-InsructionSet RV32CI {
3
+InsructionSet RV32IC {
4 4
 	constants {
5 5
 		XLEN
6 6
 	}
@@ -197,7 +197,64 @@ InsructionSet RV32CI {
197 197
 	}
198 198
 }
199 199
 
200
-InsructionSet RV32CF extends RV32CI {
200
+InsructionSet RV32FC extends RV32IC{
201
+	constants {
202
+		XLEN, FLEN
203
+	}
204
+	address_spaces { 
205
+		MEM[8]
206
+	}
207
+	registers { 
208
+		[31:0]   X[XLEN],
209
+		[31:0]   F[FLEN]
210
+	}
211
+	instructions{
212
+		C.FLW {
213
+			encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
214
+			args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))";
215
+			val rs1_idx[5] <= rs1+8;
216
+			val rd_idx[5] <= rd+8;
217
+			val offs[XLEN] <= X[rs1_idx]+uimm;
218
+			val res[32] <= MEM[offs]{32};
219
+			if(FLEN==32)
220
+				F[rd_idx] <= res;
221
+			else {
222
+				val upper[FLEN] <= (-1<<31);
223
+				F[rd_idx] <= upper*2 | res;
224
+			}
225
+		} 
226
+		C.FSW {
227
+			encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
228
+			args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))";
229
+			val rs1_idx[5] <= rs1+8;
230
+			val rs2_idx[5] <= rs2+8;
231
+			val offs[XLEN] <= X[rs1_idx]+uimm;
232
+			MEM[offs]{32}<=F[rs2_idx]{32};
233
+		}
234
+		C.FLWSP {
235
+			encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
236
+			args_disass:"f%rd$d, %uimm%(x2)";
237
+			val x2_idx[5] <= 2;
238
+			val offs[XLEN] <= X[x2_idx]+uimm;
239
+			val res[32] <= MEM[offs]{32};
240
+			if(FLEN==32)
241
+				F[rd] <= res;
242
+			else {
243
+				val upper[FLEN] <= (-1<<31);
244
+				F[rd] <= upper*2 | res;
245
+			}
246
+		}
247
+		C.FSWSP {
248
+			encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
249
+			args_disass:"f%rs2$d, %uimm%(x2), ";
250
+			val x2_idx[5] <= 2;
251
+			val offs[XLEN] <= X[x2_idx]+uimm;
252
+			MEM[offs]{32}<=F[rs2];
253
+		}		
254
+	}
255
+}
256
+
257
+InsructionSet RV32DC extends RV32IC{
201 258
 	constants {
202 259
 		XLEN, FLEN
203 260
 	}
@@ -212,31 +269,19 @@ InsructionSet RV32CF extends RV32CI {
212 269
 		C.FLD { //(RV32/64)
213 270
 			encoding: b001 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
214 271
 	 	}
215
-		C.FLW {//(RV32)
216
-			encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
217
-		} 
218 272
 		C.FSD { //(RV32/64)
219 273
 			encoding: b101 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
220 274
 		} 
221
-		C.FSW {//(RV32)
222
-			encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
223
-		}
224 275
 		C.FLDSP {//(RV32/64)
225 276
 			encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
226 277
 		}
227
-		C.FLWSP {//RV32
228
-			encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
229
-		}
230 278
 		C.FSDSP {//(RV32/64)
231 279
 			encoding:b101 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
232 280
 		}
233
-		C.FSWSP {//(RV32)
234
-			encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
235
-		}		
236 281
 	}
237 282
 }
238 283
 
239
-InsructionSet RV64CI extends RV32CI {
284
+InsructionSet RV64IC extends RV32IC {
240 285
 	constants {
241 286
 		XLEN
242 287
 	}
@@ -284,7 +329,7 @@ InsructionSet RV64CI extends RV32CI {
284 329
 	}
285 330
 }
286 331
 
287
-InsructionSet RV128CI extends RV64CI {
332
+InsructionSet RV128IC extends RV64IC {
288 333
 	constants {
289 334
 		XLEN
290 335
 	}

+ 210
- 21
riscv/gen_input/RV32F.core_desc View File

@@ -2,104 +2,293 @@ import "RV32IBase.core_desc"
2 2
 
3 3
 InsructionSet RV32F extends RV32IBase{
4 4
 	constants {
5
-		FLEN, fcsr
5
+		FLEN, FFLAG_MASK
6 6
 	} 
7 7
 	registers {
8
-		[31:0]    F[FLEN]
8
+		[31:0]    F[FLEN],  FCSR[32]
9 9
     }	
10 10
 	instructions{
11 11
 		FLW {
12 12
 			encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
13
+			args_disass:"f%rd$d, %imm%(x%rs1$d)";
13 14
 			val offs[XLEN] <= X[rs1]+imm;
14
-			F[rd]<=MEM[offs];
15
+			val res[32] <= MEM[offs]{32};
16
+			if(FLEN==32)
17
+				F[rd] <= res;
18
+			else {
19
+				val upper[FLEN] <= (-1<<31);
20
+				F[rd] <= upper*2 | res;
21
+			}
15 22
 		}
16 23
 		FSW {
17 24
 			encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
25
+			args_disass:"f%rs2$d, %imm%(x%rs1$d)";
18 26
 			val offs[XLEN] <= X[rs1]+imm;
19
-			MEM[offs]<=F[rs2];
27
+			MEM[offs]{32}<=F[rs2]{32};
20 28
 		}
21 29
 		FMADD.S {
22 30
 			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
23
-			F[rd]f<= F[rs1]f * F[rs2]f * F[rs3]f;
31
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
32
+			//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
33
+			val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
34
+			if(FLEN==32)
35
+				F[rd] <= res;
36
+			else {
37
+				val upper[FLEN] <= (-1<<31);
38
+				F[rd] <= upper*2 | res;
39
+			}
40
+			val flags[32] <= fdispatch_fget_flags();
41
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
24 42
 		}
25 43
 		FMSUB.S {
26 44
 			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
27
-			F[rd]f<=F[rs1]f * F[rs2]f -F[rs3]f;
28
-		}
29
-		FNMSUB.S {
30
-			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
31
-			F[rd]f<=-F[rs1]f * F[rs2]f- F[rs3]f;
45
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
46
+			//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
47
+			val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
48
+			if(FLEN==32)
49
+				F[rd] <= res;
50
+			else {
51
+				val upper[FLEN] <= (-1<<31);
52
+				F[rd] <= upper*2 | res;
53
+			}
54
+			val flags[32] <= fdispatch_fget_flags();
55
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};	
32 56
 		}
33 57
 		FNMADD.S {
34 58
 			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
35
-			F[rd]f<=-F[rs1]f*F[rs2]f+F[rs3]f;
59
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
60
+			//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
61
+			val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
62
+			if(FLEN==32)
63
+				F[rd] <= res;
64
+			else {
65
+				val upper[FLEN] <= (-1<<31);
66
+				F[rd] <= upper*2 | res;
67
+			}
68
+			val flags[32] <= fdispatch_fget_flags();
69
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
70
+		}
71
+		FNMSUB.S {
72
+			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
73
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
74
+			//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
75
+			val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
76
+			if(FLEN==32)
77
+				F[rd] <= res;
78
+			else {
79
+				val upper[FLEN] <= (-1<<31);
80
+				F[rd] <= upper*2 | res;
81
+			}
82
+			val flags[32] <= fdispatch_fget_flags();
83
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
36 84
 		}
37 85
 		FADD.S {
38 86
 			encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
39
-			F[rd]f <= F[rs1]f + F[rs2]f;
87
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
88
+			// F[rd]f <= F[rs1]f + F[rs2]f;
89
+			val res[32] <= fdispatch_fadd_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
90
+			if(FLEN==32)
91
+				F[rd] <= res;
92
+			else {
93
+				val upper[FLEN] <= (-1<<31);
94
+				F[rd] <= upper*2 | res;
95
+			}
96
+			val flags[32] <= fdispatch_fget_flags();
97
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
40 98
 		}
41 99
 		FSUB.S {
42 100
 			encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
43
-			F[rd]f <= F[rs1]f - F[rs2]f;
101
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
102
+			// F[rd]f <= F[rs1]f - F[rs2]f;
103
+			val res[32] <= fdispatch_fsub_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
104
+			if(FLEN==32)
105
+				F[rd] <= res;
106
+			else {
107
+				val upper[FLEN] <= -1<<31;
108
+				F[rd] <= upper*2 | res;
109
+			}
110
+			val flags[32] <= fdispatch_fget_flags();
111
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
44 112
 		}
45 113
 		FMUL.S {
46 114
 			encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
47
-			F[rd]f <= F[rs1]f * F[rs2];
115
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
116
+			// F[rd]f <= F[rs1]f * F[rs2]f;
117
+			val res[32] <= fdispatch_fmul_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
118
+			if(FLEN==32)
119
+				F[rd] <= res;
120
+			else {
121
+				val upper[FLEN] <= -1<<31;
122
+				F[rd] <= upper*2 | res;
123
+			}
124
+			val flags[32] <= fdispatch_fget_flags();
125
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
48 126
 		}
49 127
 		FDIV.S {
50 128
 			encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
51
-			F[rd]f <= F[rs1]f / F[rs2]f;
129
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
130
+			// F[rd]f <= F[rs1]f / F[rs2]f;
131
+			val res[32] <= fdispatch_fdiv_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
132
+			if(FLEN==32)
133
+				F[rd] <= res;
134
+			else {
135
+				val upper[FLEN] <= -1<<31;
136
+				F[rd] <= upper*2 | res;
137
+			}
138
+			val flags[32] <= fdispatch_fget_flags();
139
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
52 140
 		}
53 141
 		FSQRT.S {
54 142
 			encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
55
-			F[rd]f<=sqrt(F[rs1]f);
143
+			args_disass:"x%rd$d, f%rs1$d";
144
+			//F[rd]f<=sqrt(F[rs1]f);
145
+			val res[32] <= fdispatch_fsqrt_s(F[rs1]{32}, choose(rm<7, rm{8}, FCSR{8}));
146
+			if(FLEN==32)
147
+				F[rd] <= res;
148
+			else {
149
+				val upper[FLEN] <= -1<<31;
150
+				F[rd] <= upper*2 | res;
151
+			}
152
+			val flags[32] <= fdispatch_fget_flags();
153
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
56 154
 		}
57 155
 		FSGNJ.S {
58 156
 			encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
157
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
158
+			val res[32] <= (F[rs1]{32} & 0x7fffffff) | (F[rs2]{32} & 0x80000000);
159
+			if(FLEN==32)
160
+				F[rd] <= res;
161
+			else {
162
+				val upper[FLEN] <= -1<<31;
163
+				F[rd] <= upper*2 | res;
164
+			}
59 165
 		}
60 166
 		FSGNJN.S {
61 167
 			encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
168
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
169
+			val res[32] <= (F[rs1]{32} & 0x7fffffff) | (~F[rs2]{32} & 0x80000000);
170
+			if(FLEN==32)
171
+				F[rd] <= res;
172
+			else {
173
+				val upper[FLEN] <= -1<<31;
174
+				F[rd] <= upper*2 | res;
175
+			}
62 176
 		}
63 177
 		FSGNJX.S {
64 178
 			encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
179
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
180
+			val res[32] <= F[rs1]{32} ^ (F[rs2]{32} & 0x80000000);
181
+			if(FLEN==32)
182
+				F[rd] <= res;
183
+			else {
184
+				val upper[FLEN] <= -1<<31;
185
+				F[rd] <= upper*2 | res;
186
+			}
65 187
 		}
66 188
 		FMIN.S  {
67 189
 			encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
68
-			F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
190
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
191
+			//F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
192
+			val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
193
+			if(FLEN==32)
194
+				F[rd] <= res;
195
+			else {
196
+				val upper[FLEN] <= -1<<31;
197
+				F[rd] <= upper*2 | res;
198
+			}
199
+			val flags[32] <= fdispatch_fget_flags();
200
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
69 201
 		}
70 202
 		FMAX.S {
71 203
 			encoding: b0010100 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
72
-			F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
204
+			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
205
+			//F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
206
+			val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
207
+			if(FLEN==32)
208
+				F[rd] <= res;
209
+			else {
210
+				val upper[FLEN] <= -1<<31;
211
+				F[rd] <= upper*2 | res;
212
+			}
213
+			val flags[32] <= fdispatch_fget_flags();
214
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
73 215
 		}
74 216
 		FCVT.W.S {
75 217
 			encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
218
+			args_disass:"x%rd$d, f%rs1$d";
219
+			X[rd]<= sext(fdispatch_fcvt_s(F[rs1]{32}, zext(0, 32), rm{8}), XLEN);
220
+			val flags[32] <= fdispatch_fget_flags();
221
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
76 222
 		}
77 223
 		FCVT.WU.S {
78 224
 			encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
79
-		}
80
-		FMV.X.W {
81
-			encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
225
+			args_disass:"x%rd$d, f%rs1$d";
226
+			X[rd]<= zext(fdispatch_fcvt_s(F[rs1]{32}, zext(1, 32), rm{8}), XLEN);
227
+			val flags[32] <= fdispatch_fget_flags();
228
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
82 229
 		}
83 230
 		FEQ.S {
84 231
 			encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
232
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
233
+			X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
234
+			val flags[32] <= fdispatch_fget_flags();
235
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
85 236
 		}
86 237
 		FLT.S {
87 238
 			encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
239
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
240
+			X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32));
241
+			val flags[32] <= fdispatch_fget_flags();
242
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
88 243
 		}
89 244
 		FLE.S {
90 245
 			encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
246
+			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
247
+			X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
248
+			val flags[32] <= fdispatch_fget_flags();
249
+			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
91 250
 		}
92 251
 		FCLASS.S {
93 252
 			encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
253
+			args_disass:"x%rd$d, f%rs1$d";
254
+			X[rd]<=fdispatch_fclass_s(F[rs1]{32});
94 255
 		}
95 256
 		FCVT.S.W {
96 257
 			encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
258
+			args_disass:"f%rd$d, x%rs1$d";
259
+			val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
260
+			if(FLEN==32)
261
+				F[rd] <= res;
262
+			else {
263
+				val upper[FLEN] <= -1<<31;
264
+				F[rd] <= upper*2 | res;
265
+			}
97 266
 		}
98 267
 		FCVT.S.WU {
99 268
 			encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
269
+			args_disass:"f%rd$d, x%rs1$d";
270
+			val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
271
+			if(FLEN==32)
272
+				F[rd] <= res;
273
+			else {
274
+				val upper[FLEN] <= -1<<31;
275
+				F[rd] <= upper*2 | res;
276
+			}
277
+		}
278
+		FMV.X.W {
279
+			encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
280
+			args_disass:"x%rd$d, f%rs1$d";
281
+			X[rd]<=sext(F[rs1]{32});
100 282
 		}
101 283
 		FMV.W.X {
102 284
 			encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
285
+			args_disass:"f%rd$d, x%rs1$d";
286
+			if(FLEN==32)
287
+				F[rd] <= X[rs1];
288
+			else {
289
+				val upper[FLEN] <= -1<<31;
290
+				F[rd] <= upper*2 | X[rs1];
291
+			}
103 292
 		}
104 293
 	}
105 294
 }

+ 22
- 6
riscv/gen_input/RV32M.core_desc View File

@@ -41,9 +41,17 @@ InsructionSet RV32M extends RV32IBase {
41 41
 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011;
42 42
 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
43 43
 		    if(rd != 0){
44
-		    	if(X[rs2]!=0)
45
-		    		X[rd] <= sext(X[rs1], 32) / sext(X[rs2], 32);
46
-		    	else 
44
+		    	if(X[rs2]!=0){
45
+		    		val M1[XLEN] <= -1;
46
+		    		val MMIN[XLEN] <= -1<<(XLEN-1);
47
+		    		if(X[rs1]s==MMIN's)
48
+			    		if(X[rs2]s==M1's)
49
+			    			X[rd]<=MMIN;
50
+		    			else
51
+			    			X[rd] <= X[rs1]s / X[rs2]s;
52
+	    			else
53
+		    			X[rd] <= X[rs1]s / X[rs2]s;
54
+		    	}else 
47 55
 		    		X[rd] <= -1;
48 56
 		    }
49 57
 		}
@@ -61,9 +69,17 @@ InsructionSet RV32M extends RV32IBase {
61 69
 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011;
62 70
 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
63 71
 		    if(rd != 0){
64
-		    	if(X[rs2]!=0)
65
-		    		X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
66
-		    	else 
72
+		    	if(X[rs2]!=0) {
73
+		    		val M1[XLEN] <= -1;
74
+		    		val MMIN[XLEN] <= -1<<(XLEN-1);
75
+		    		if(X[rs1]s==MMIN's)
76
+			    		if(X[rs2]s==M1's)
77
+			    			X[rd] <= 0;
78
+			    		else
79
+			    			X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
80
+	    			else
81
+		    			X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32);
82
+		    	} else 
67 83
 		    		X[rd] <= X[rs1];
68 84
 		    }
69 85
 		}

+ 21
- 1
riscv/gen_input/minres_rv.core_desc View File

@@ -2,12 +2,13 @@ import "RV32IBase.core_desc"
2 2
 import "RV32M.core_desc"
3 3
 import "RV32A.core_desc"
4 4
 import "RV32C.core_desc"
5
+import "RV32F.core_desc"
5 6
 import "RV64IBase.core_desc"
6 7
 //import "RV64M.core_desc"
7 8
 import "RV64A.core_desc"
8 9
 
9 10
 
10
-Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32CI {
11
+Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
11 12
     template:"vm_riscv.in.cpp";
12 13
     constants {
13 14
         XLEN:=32;
@@ -25,6 +26,25 @@ Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32CI {
25 26
     }
26 27
 }
27 28
 
29
+Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC {
30
+    constants {
31
+        XLEN:=32;
32
+        FLEN:=32;
33
+        XLEN2:=64;
34
+        XLEN_BIT_MASK:=0x1f;
35
+        PCLEN:=32;
36
+        fence:=0;
37
+        fencei:=1;
38
+        fencevmal:=2;
39
+        fencevmau:=3;
40
+        //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
41
+        MISA_VAL:=0b01000000000101000001000100000001;
42
+        PGSIZE := 4096; //1 << 12;
43
+        PGMASK := 4095; //PGSIZE-1
44
+        FFLAG_MASK:=0x1f;
45
+    }
46
+}
47
+
28 48
 
29 49
 Core RV64IA provides RV64IBase, RV64A, RV32A {
30 50
     template:"vm_riscv.in.cpp";

+ 12
- 5
riscv/gen_input/templates/incl-CORENAME.h.gtl View File

@@ -100,6 +100,8 @@ struct traits<${coreDef.name.toLowerCase()}> {
100 100
 
101 101
     enum mem_type_e {${allSpaces.collect{s -> s.name}.join(', ')}};
102 102
 
103
+	constexpr static bool has_fp_regs = ${allRegs.find {it.name=='FCSR'}!= null ?'true':'false'};
104
+    
103 105
 };
104 106
 
105 107
 struct ${coreDef.name.toLowerCase()}: public arch_if {
@@ -112,8 +114,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
112 114
     ${coreDef.name.toLowerCase()}();
113 115
     ~${coreDef.name.toLowerCase()}();
114 116
 
115
-	const std::string core_type_name() const override {return traits<${coreDef.name.toLowerCase()}>::core_type;}
116
-	
117 117
     void reset(uint64_t address=0) override;
118 118
 
119 119
     uint8_t* get_regs_base_ptr() override;
@@ -158,9 +158,16 @@ protected:
158 158
     } reg;
159 159
 
160 160
     std::array<address_type, 4> addr_mode;
161
-
162
-    uint64_t cycles = 0;
163
-
161
+    
162
+<%
163
+def fcsr = allRegs.find {it.name=='FCSR'}
164
+if(fcsr != null) {%>
165
+	uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
166
+	void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}		
167
+<%} else { %>
168
+	uint32_t get_fcsr(){return 0;}
169
+	void set_fcsr(uint32_t val){}
170
+<%}%>
164 171
 };
165 172
 
166 173
 }

+ 3
- 2
riscv/gen_input/templates/src-CORENAME.cpp.gtl View File

@@ -68,6 +68,7 @@ uint8_t* ${coreDef.name.toLowerCase()}::get_regs_base_ptr(){
68 68
     return reinterpret_cast<uint8_t*>(&reg);
69 69
 }
70 70
 
71
-${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::v2p(const iss::addr_t& pc) {
72
-    return phys_addr_t(pc); //change logical address to physical address
71
+${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) {
72
+    return phys_addr_t(pc); // change logical address to physical address
73 73
 }
74
+

+ 25
- 1
riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl View File

@@ -48,6 +48,12 @@
48 48
 #include <array>
49 49
 
50 50
 namespace iss {
51
+namespace vm {
52
+namespace fp_impl{
53
+void add_fp_functions_2_module(llvm::Module *mod);
54
+}
55
+}
56
+
51 57
 namespace ${coreDef.name.toLowerCase()} {
52 58
 using namespace iss::arch;
53 59
 using namespace llvm;
@@ -81,6 +87,11 @@ protected:
81 87
         return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
82 88
     }
83 89
 
90
+    void setup_module(llvm::Module* m) override {
91
+        super::setup_module(m);
92
+        vm::fp_impl::add_fp_functions_2_module(m);
93
+    }
94
+
84 95
     inline llvm::Value *gen_choose(llvm::Value *cond, llvm::Value *trueVal, llvm::Value *falseVal,
85 96
                                    unsigned size) const {
86 97
         return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
@@ -106,6 +117,10 @@ protected:
106 117
         return this->builder.CreateLoad(get_reg_ptr(i), false);
107 118
     }
108 119
 
120
+    llvm::Value* gen_fdispatch(std::string fname, const std::vector<llvm::Value*>& args);
121
+
122
+    llvm::Value* gen_dispatch(std::string name, llvm::Value*, llvm::Value*, llvm::Value*);
123
+
109 124
     inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
110 125
         llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val),
111 126
                                                                   this->get_type(traits<ARCH>::XLEN));
@@ -310,7 +325,16 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBl
310 325
                           bb, this->trap_blk, 1);
311 326
 }
312 327
 
313
-} // namespace ${coreDef.name.toLowerCase()}
328
+template<typename ARCH>
329
+inline llvm::Value* vm_impl<ARCH>::gen_fdispatch(std::string fname, const std::vector<llvm::Value*>& args) {
330
+        return this->builder.CreateCall(this->mod->getFunction(fname), args);
331
+}
332
+
333
+template<typename ARCH>
334
+inline llvm::Value* vm_impl<ARCH>::gen_dispatch(std::string name, llvm::Value* val1, llvm::Value* val2, llvm::Value* val3) {
335
+}
336
+
337
+} // namespace rv32imacf
314 338
 
315 339
 template <>
316 340
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {

+ 44
- 0
riscv/incl/iss/arch/riscv_hart_msu_vp.h View File

@@ -48,6 +48,7 @@
48 48
 #include <util/sparse_array.h>
49 49
 #include <util/bit_field.h>
50 50
 #include <array>
51
+#include <type_traits>
51 52
 
52 53
 namespace iss {
53 54
 namespace arch {
@@ -537,6 +538,8 @@ private:
537 538
     iss::status write_ip(unsigned addr, reg_t val);
538 539
     iss::status read_satp(unsigned addr, reg_t &val);
539 540
     iss::status write_satp(unsigned addr, reg_t val);
541
+    iss::status read_fcsr(unsigned addr, reg_t& val);
542
+    iss::status write_fcsr(unsigned addr, reg_t val);
540 543
 protected:
541 544
     void check_interrupt();
542 545
 };
@@ -579,6 +582,13 @@ riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
579 582
     csr_wr_cb[uie] = &riscv_hart_msu_vp<BASE>::write_ie;
580 583
     csr_rd_cb[satp] = &riscv_hart_msu_vp<BASE>::read_satp;
581 584
     csr_wr_cb[satp] = &riscv_hart_msu_vp<BASE>::write_satp;
585
+    csr_rd_cb[fcsr] = &riscv_hart_msu_vp<BASE>::read_fcsr;
586
+    csr_wr_cb[fcsr] = &riscv_hart_msu_vp<BASE>::write_fcsr;
587
+    csr_rd_cb[fflags] = &riscv_hart_msu_vp<BASE>::read_fcsr;
588
+    csr_wr_cb[fflags] = &riscv_hart_msu_vp<BASE>::write_fcsr;
589
+    csr_rd_cb[frm] = &riscv_hart_msu_vp<BASE>::read_fcsr;
590
+    csr_wr_cb[frm] = &riscv_hart_msu_vp<BASE>::write_fcsr;
591
+
582 592
 }
583 593
 
584 594
 template <typename BASE> std::pair<uint64_t,bool> riscv_hart_msu_vp<BASE>::load_file(std::string name, int type) {
@@ -940,6 +950,39 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_satp(unsigne
940 950
     update_vm_info();
941 951
     return iss::Ok;
942 952
 }
953
+template<typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_fcsr(unsigned addr, reg_t& val) {
954
+    switch(addr){
955
+    case 1: //fflags, 4:0
956
+        val = bit_sub<0, 5>(this->get_fcsr());
957
+        break;
958
+    case 2: // frm, 7:5
959
+        val = bit_sub<5, 3>(this->get_fcsr());
960
+       break;
961
+    case 3: // fcsr
962
+        val=this->get_fcsr();
963
+        break;
964
+    default:
965
+        return iss::Err;
966
+    }
967
+    return iss::Ok;
968
+}
969
+
970
+template<typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_fcsr(unsigned addr, reg_t val) {
971
+    switch(addr){
972
+    case 1: //fflags, 4:0
973
+        this->set_fcsr( (this->get_fcsr() & 0xffffffe0) | (val&0x1f));
974
+        break;
975
+    case 2: // frm, 7:5
976
+        this->set_fcsr( (this->get_fcsr() & 0xffffff1f) | ((val&0x7)<<5));
977
+       break;
978
+    case 3: // fcsr
979
+        this->set_fcsr(val&0xff);
980
+        break;
981
+    default:
982
+        return iss::Err;
983
+    }
984
+    return iss::Ok;
985
+}
943 986
 
944 987
 template <typename BASE>
945 988
 iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
@@ -1299,4 +1342,5 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::wait_until(uint64_t flags
1299 1342
 }
1300 1343
 }
1301 1344
 
1345
+
1302 1346
 #endif /* _RISCV_CORE_H_ */

+ 278
- 0
riscv/incl/iss/arch/rv32gc.h View File

@@ -0,0 +1,278 @@
1
+////////////////////////////////////////////////////////////////////////////////
2
+// Copyright (C) 2017, MINRES Technologies GmbH
3
+// All rights reserved.
4
+// 
5
+// Redistribution and use in source and binary forms, with or without
6
+// modification, are permitted provided that the following conditions are met:
7
+// 
8
+// 1. Redistributions of source code must retain the above copyright notice,
9
+//    this list of conditions and the following disclaimer.
10
+// 
11
+// 2. Redistributions in binary form must reproduce the above copyright notice,
12
+//    this list of conditions and the following disclaimer in the documentation
13
+//    and/or other materials provided with the distribution.
14
+// 
15
+// 3. Neither the name of the copyright holder nor the names of its contributors
16
+//    may be used to endorse or promote products derived from this software
17
+//    without specific prior written permission.
18
+// 
19
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+// POSSIBILITY OF SUCH DAMAGE.
30
+// 
31
+////////////////////////////////////////////////////////////////////////////////
32
+
33
+#ifndef _RV32GC_H_
34
+#define _RV32GC_H_
35
+
36
+#include <iss/arch_if.h>
37
+#include <iss/vm_if.h>
38
+#include <iss/arch/traits.h>
39
+#include <array>
40
+
41
+namespace iss {
42
+namespace arch {
43
+
44
+struct rv32gc;
45
+
46
+template<>
47
+struct traits<rv32gc> {
48
+
49
+	constexpr static char const* const core_type = "RV32GC";
50
+    
51
+    enum constants {XLEN=32, FLEN=32, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095, FFLAG_MASK=31};
52
+
53
+    enum reg_e {
54
+        X0,
55
+        X1,
56
+        X2,
57
+        X3,
58
+        X4,
59
+        X5,
60
+        X6,
61
+        X7,
62
+        X8,
63
+        X9,
64
+        X10,
65
+        X11,
66
+        X12,
67
+        X13,
68
+        X14,
69
+        X15,
70
+        X16,
71
+        X17,
72
+        X18,
73
+        X19,
74
+        X20,
75
+        X21,
76
+        X22,
77
+        X23,
78
+        X24,
79
+        X25,
80
+        X26,
81
+        X27,
82
+        X28,
83
+        X29,
84
+        X30,
85
+        X31,
86
+        PC,
87
+        F0,
88
+        F1,
89
+        F2,
90
+        F3,
91
+        F4,
92
+        F5,
93
+        F6,
94
+        F7,
95
+        F8,
96
+        F9,
97
+        F10,
98
+        F11,
99
+        F12,
100
+        F13,
101
+        F14,
102
+        F15,
103
+        F16,
104
+        F17,
105
+        F18,
106
+        F19,
107
+        F20,
108
+        F21,
109
+        F22,
110
+        F23,
111
+        F24,
112
+        F25,
113
+        F26,
114
+        F27,
115
+        F28,
116
+        F29,
117
+        F30,
118
+        F31,
119
+        FCSR,
120
+        NUM_REGS,
121
+        NEXT_PC=NUM_REGS,
122
+        TRAP_STATE,
123
+        PENDING_TRAP,
124
+        MACHINE_STATE,
125
+        ICOUNT
126
+    };
127
+
128
+    using reg_t = uint32_t;
129
+
130
+    using addr_t = uint32_t;
131
+
132
+    using code_word_t = uint32_t; //TODO: check removal
133
+
134
+    using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
135
+
136
+    using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
137
+
138
+    constexpr static unsigned reg_bit_width(unsigned r) {
139
+        constexpr std::array<const uint32_t, 71> RV32GC_reg_size{{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64}};
140
+        return RV32GC_reg_size[r];
141
+    }
142
+
143
+    constexpr static unsigned reg_byte_offset(unsigned r) {
144
+    	constexpr std::array<const uint32_t, 72> RV32GC_reg_byte_offset{{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148,152,156,160,164,168,172,176,180,184,188,192,196,200,204,208,212,216,220,224,228,232,236,240,244,248,252,256,260,264,268,272,276,280,288}};
145
+        return RV32GC_reg_byte_offset[r];
146
+    }
147
+
148
+    static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
149
+
150
+    enum sreg_flag_e {FLAGS};
151
+
152
+    enum mem_type_e {MEM, CSR, FENCE, RES};
153
+
154
+	constexpr static bool has_fp_regs = true;
155
+    
156
+};
157
+
158
+struct rv32gc: public arch_if {
159
+
160
+    using virt_addr_t = typename traits<rv32gc>::virt_addr_t;
161
+    using phys_addr_t = typename traits<rv32gc>::phys_addr_t;
162
+    using reg_t =  typename traits<rv32gc>::reg_t;
163
+    using addr_t = typename traits<rv32gc>::addr_t;
164
+
165
+    rv32gc();
166
+    ~rv32gc();
167
+
168
+    void reset(uint64_t address=0) override;
169
+
170
+    uint8_t* get_regs_base_ptr() override;
171
+    /// deprecated
172
+    void get_reg(short idx, std::vector<uint8_t>& value) override {}
173
+    void set_reg(short idx, const std::vector<uint8_t>& value) override {}
174
+    /// deprecated
175
+    bool get_flag(int flag) override {return false;}
176
+    void set_flag(int, bool value) override {};
177
+    /// deprecated
178
+    void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
179
+
180
+    uint64_t get_icount() { return reg.icount;}
181
+
182
+    inline phys_addr_t v2p(const iss::addr_t& addr){
183
+        if(addr.space != traits<rv32gc>::MEM ||
184
+                addr.type == iss::address_type::PHYSICAL ||
185
+                addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL){
186
+            return phys_addr_t(addr.access, addr.space, addr.val&traits<rv32gc>::addr_mask);
187
+        } else
188
+            return virt2phys(addr);
189
+    }
190
+
191
+    virtual phys_addr_t virt2phys(const iss::addr_t& addr);
192
+
193
+    virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
194
+
195
+protected:
196
+    struct RV32GC_regs {
197
+        uint32_t X0 = 0;
198
+        uint32_t X1 = 0;
199
+        uint32_t X2 = 0;
200
+        uint32_t X3 = 0;
201
+        uint32_t X4 = 0;
202
+        uint32_t X5 = 0;
203
+        uint32_t X6 = 0;
204
+        uint32_t X7 = 0;
205
+        uint32_t X8 = 0;
206
+        uint32_t X9 = 0;
207
+        uint32_t X10 = 0;
208
+        uint32_t X11 = 0;
209
+        uint32_t X12 = 0;
210
+        uint32_t X13 = 0;
211
+        uint32_t X14 = 0;
212
+        uint32_t X15 = 0;
213
+        uint32_t X16 = 0;
214
+        uint32_t X17 = 0;
215
+        uint32_t X18 = 0;
216
+        uint32_t X19 = 0;
217
+        uint32_t X20 = 0;
218
+        uint32_t X21 = 0;
219
+        uint32_t X22 = 0;
220
+        uint32_t X23 = 0;
221
+        uint32_t X24 = 0;
222
+        uint32_t X25 = 0;
223
+        uint32_t X26 = 0;
224
+        uint32_t X27 = 0;
225
+        uint32_t X28 = 0;
226
+        uint32_t X29 = 0;
227
+        uint32_t X30 = 0;
228
+        uint32_t X31 = 0;
229
+        uint32_t PC = 0;
230
+        uint32_t F0 = 0;
231
+        uint32_t F1 = 0;
232
+        uint32_t F2 = 0;
233
+        uint32_t F3 = 0;
234
+        uint32_t F4 = 0;
235
+        uint32_t F5 = 0;
236
+        uint32_t F6 = 0;
237
+        uint32_t F7 = 0;
238
+        uint32_t F8 = 0;
239
+        uint32_t F9 = 0;
240
+        uint32_t F10 = 0;
241
+        uint32_t F11 = 0;
242
+        uint32_t F12 = 0;
243
+        uint32_t F13 = 0;
244
+        uint32_t F14 = 0;
245
+        uint32_t F15 = 0;
246
+        uint32_t F16 = 0;
247
+        uint32_t F17 = 0;
248
+        uint32_t F18 = 0;
249
+        uint32_t F19 = 0;
250
+        uint32_t F20 = 0;
251
+        uint32_t F21 = 0;
252
+        uint32_t F22 = 0;
253
+        uint32_t F23 = 0;
254
+        uint32_t F24 = 0;
255
+        uint32_t F25 = 0;
256
+        uint32_t F26 = 0;
257
+        uint32_t F27 = 0;
258
+        uint32_t F28 = 0;
259
+        uint32_t F29 = 0;
260
+        uint32_t F30 = 0;
261
+        uint32_t F31 = 0;
262
+        uint32_t FCSR = 0;
263
+        uint32_t NEXT_PC = 0;
264
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0;
265
+        uint64_t icount = 0;
266
+    } reg;
267
+
268
+    std::array<address_type, 4> addr_mode;
269
+    
270
+
271
+	uint32_t get_fcsr(){return reg.FCSR;}
272
+	void set_fcsr(uint32_t val){reg.FCSR = val;}		
273
+
274
+};
275
+
276
+}
277
+}            
278
+#endif /* _RV32GC_H_ */

+ 6
- 0
riscv/incl/iss/arch/rv32imac.h View File

@@ -118,6 +118,8 @@ struct traits<rv32imac> {
118 118
 
119 119
     enum mem_type_e {MEM, CSR, FENCE, RES};
120 120
 
121
+	constexpr static bool has_fp_regs = false;
122
+    
121 123
 };
122 124
 
123 125
 struct rv32imac: public arch_if {
@@ -198,6 +200,10 @@ protected:
198 200
     } reg;
199 201
 
200 202
     std::array<address_type, 4> addr_mode;
203
+    
204
+
205
+	uint32_t get_fcsr(){return 0;}
206
+	void set_fcsr(uint32_t val){}
201 207
 
202 208
 };
203 209
 

+ 6
- 0
riscv/incl/iss/arch/rv64ia.h View File

@@ -118,6 +118,8 @@ struct traits<rv64ia> {
118 118
 
119 119
     enum mem_type_e {MEM, CSR, FENCE, RES};
120 120
 
121
+	constexpr static bool has_fp_regs = false;
122
+    
121 123
 };
122 124
 
123 125
 struct rv64ia: public arch_if {
@@ -198,6 +200,10 @@ protected:
198 200
     } reg;
199 201
 
200 202
     std::array<address_type, 4> addr_mode;
203
+    
204
+
205
+	uint32_t get_fcsr(){return 0;}
206
+	void set_fcsr(uint32_t val){}
201 207
 
202 208
 };
203 209
 

+ 290
- 0
riscv/src/internal/fp_functions.cpp View File

@@ -0,0 +1,290 @@
1
+////////////////////////////////////////////////////////////////////////////////
2
+// Copyright (C) 2017, MINRES Technologies GmbH
3
+// All rights reserved.
4
+//
5
+// Redistribution and use in source and binary forms, with or without
6
+// modification, are permitted provided that the following conditions are met:
7
+//
8
+// 1. Redistributions of source code must retain the above copyright notice,
9
+//    this list of conditions and the following disclaimer.
10
+//
11
+// 2. Redistributions in binary form must reproduce the above copyright notice,
12
+//    this list of conditions and the following disclaimer in the documentation
13
+//    and/or other materials provided with the distribution.
14
+//
15
+// 3. Neither the name of the copyright holder nor the names of its contributors
16
+//    may be used to endorse or promote products derived from this software
17
+//    without specific prior written permission.
18
+//
19
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+// POSSIBILITY OF SUCH DAMAGE.
30
+//
31
+// Contributors:
32
+//       eyck@minres.com - initial API and implementation
33
+////////////////////////////////////////////////////////////////////////////////
34
+
35
+#include <iss/iss.h>
36
+#include <iss/vm_base.h>
37
+
38
+extern "C" {
39
+#include <softfloat.h>
40
+#include "internals.h"
41
+#include "specialize.h"
42
+}
43
+
44
+namespace iss {
45
+namespace vm {
46
+namespace fp_impl {
47
+
48
+using namespace std;
49
+
50
+#define INT_TYPE(L)   Type::getIntNTy(mod->getContext(), L)
51
+#define FLOAT_TYPE    Type::getFloatTy(mod->getContext())
52
+#define DOUBLE_TYPE   Type::getDoubleTy(mod->getContext())
53
+#define VOID_TYPE     Type::getVoidTy(mod->getContext())
54
+#define THIS_PTR_TYPE Type::getIntNPtrTy(mod->getContext(), 8)
55
+#define FDECLL(NAME, RET, ...)                                                                                         \
56
+    Function *NAME##_func = CurrentModule->getFunction(#NAME);                                                         \
57
+    if (!NAME##_func) {                                                                                                \
58
+        std::vector<Type *> NAME##_args{__VA_ARGS__};                                                                  \
59
+        FunctionType *NAME##_type = FunctionType::get(RET, NAME##_args, false);                                        \
60
+        NAME##_func = Function::Create(NAME##_type, GlobalValue::ExternalLinkage, #NAME, CurrentModule);               \
61
+        NAME##_func->setCallingConv(CallingConv::C);                                                                   \
62
+    }
63
+
64
+#define FDECL(NAME, RET, ...)                                                                                          \
65
+    std::vector<Type *> NAME##_args{__VA_ARGS__};                                                                      \
66
+    FunctionType *NAME##_type = llvm::FunctionType::get(RET, NAME##_args, false);                                      \
67
+    mod->getOrInsertFunction(#NAME, NAME##_type);
68
+
69
+using namespace llvm;
70
+
71
+void add_fp_functions_2_module(Module *mod) {
72
+    FDECL(fget_flags, INT_TYPE(32));
73
+    FDECL(fadd_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
74
+    FDECL(fsub_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
75
+    FDECL(fmul_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
76
+    FDECL(fdiv_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
77
+    FDECL(fsqrt_s,    INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
78
+    FDECL(fcmp_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
79
+    FDECL(fcvt_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
80
+    FDECL(fmadd_s,    INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(8));
81
+    FDECL(fsel_s,     INT_TYPE(32), INT_TYPE(32), INT_TYPE(32), INT_TYPE(32));
82
+    FDECL(fclass_s,   INT_TYPE(32), INT_TYPE(32));
83
+}
84
+
85
+}
86
+}
87
+}
88
+
89
+using this_t = uint8_t *;
90
+const uint8_t rmm_map[] = {
91
+        softfloat_round_near_even /*RNE*/,
92
+        softfloat_round_minMag/*RTZ*/,
93
+        softfloat_round_min/*RDN*/,
94
+        softfloat_round_max/*RUP?*/,
95
+        softfloat_round_near_maxMag /*RMM*/,
96
+        softfloat_round_max/*RTZ*/,
97
+        softfloat_round_max/*RTZ*/,
98
+        softfloat_round_max/*RTZ*/,
99
+};
100
+
101
+const uint32_t quiet_nan32=0x7fC00000;
102
+
103
+extern "C" {
104
+
105
+uint32_t fget_flags(){
106
+    return softfloat_exceptionFlags&0x1f;
107
+}
108
+
109
+uint32_t fadd_s(uint32_t v1, uint32_t v2, uint8_t mode) {
110
+    float32_t v1f{v1},v2f{v2};
111
+    softfloat_roundingMode=rmm_map[mode&0x7];
112
+    softfloat_exceptionFlags=0;
113
+    float32_t r =f32_add(v1f, v2f);
114
+    return r.v;
115
+}
116
+
117
+uint32_t fsub_s(uint32_t v1, uint32_t v2, uint8_t mode) {
118
+    float32_t v1f{v1},v2f{v2};
119
+    softfloat_roundingMode=rmm_map[mode&0x7];
120
+    softfloat_exceptionFlags=0;
121
+    float32_t r=f32_sub(v1f, v2f);
122
+    return r.v;
123
+}
124
+
125
+uint32_t fmul_s(uint32_t v1, uint32_t v2, uint8_t mode) {
126
+    float32_t v1f{v1},v2f{v2};
127
+    softfloat_roundingMode=rmm_map[mode&0x7];
128
+    softfloat_exceptionFlags=0;
129
+    float32_t r=f32_mul(v1f, v2f);
130
+    return r.v;
131
+}
132
+
133
+uint32_t fdiv_s(uint32_t v1, uint32_t v2, uint8_t mode) {
134
+    float32_t v1f{v1},v2f{v2};
135
+    softfloat_roundingMode=rmm_map[mode&0x7];
136
+    softfloat_exceptionFlags=0;
137
+    float32_t r=f32_div(v1f, v2f);
138
+    return r.v;
139
+}
140
+
141
+uint32_t fsqrt_s(uint32_t v1, uint8_t mode) {
142
+    float32_t v1f{v1};
143
+    softfloat_roundingMode=rmm_map[mode&0x7];
144
+    softfloat_exceptionFlags=0;
145
+    float32_t r=f32_sqrt(v1f);
146
+    return r.v;
147
+}
148
+
149
+uint32_t fcmp_s(uint32_t v1, uint32_t v2, uint32_t op) {
150
+    float32_t v1f{v1},v2f{v2};
151
+    softfloat_exceptionFlags=0;
152
+    bool nan = (v1&defaultNaNF32UI)==quiet_nan32 || (v2&defaultNaNF32UI)==quiet_nan32;
153
+    bool snan = softfloat_isSigNaNF32UI(v1) || softfloat_isSigNaNF32UI(v2);
154
+    switch(op){
155
+    case 0:
156
+        if(nan | snan){
157
+            if(snan) softfloat_raiseFlags(softfloat_flag_invalid);
158
+            return 0;
159
+        } else
160
+            return f32_eq(v1f,v2f )?1:0;
161
+    case 1:
162
+        if(nan | snan){
163
+            softfloat_raiseFlags(softfloat_flag_invalid);
164
+            return 0;
165
+        } else
166
+            return f32_le(v1f,v2f )?1:0;
167
+    case 2:
168
+        if(nan | snan){
169
+            softfloat_raiseFlags(softfloat_flag_invalid);
170
+            return 0;
171
+        } else
172
+            return f32_lt(v1f,v2f )?1:0;
173
+    default:
174
+        break;
175
+    }
176
+    return -1;
177
+}
178
+
179
+uint32_t fcvt_s(uint32_t v1, uint32_t op, uint8_t mode) {
180
+    float32_t v1f{v1};
181
+    softfloat_exceptionFlags=0;
182
+    float32_t r;
183
+    int32_t res;
184
+    switch(op){
185
+    case 0: //w->s, fp to int32
186
+        res = f32_to_i32(v1f,rmm_map[mode&0x7],true);
187
+        return (uint32_t)res;
188
+    case 1: //wu->s
189
+        return f32_to_ui32(v1f,rmm_map[mode&0x7],true);
190
+    case 2: //s->w
191
+        r=i32_to_f32(v1);
192
+        return r.v;
193
+    case 3: //s->wu
194
+        r=ui32_to_f32(v1);
195
+        return r.v;
196
+    }
197
+    return 0;
198
+}
199
+
200
+uint32_t fmadd_s(uint32_t v1, uint32_t v2, uint32_t v3, uint32_t op, uint8_t mode) {
201
+    // op should be {softfloat_mulAdd_subProd(2), softfloat_mulAdd_subC(1)}
202
+    softfloat_roundingMode=rmm_map[mode&0x7];
203
+    softfloat_exceptionFlags=0;
204
+    float32_t res = softfloat_mulAddF32(v1, v2, v3, op&0x1);
205
+    if(op>1) res.v ^= 0x80000000UL;
206
+    return res.v;
207
+}
208
+
209
+uint32_t fsel_s(uint32_t v1, uint32_t v2, uint32_t op) {
210
+    softfloat_exceptionFlags = 0;
211
+    bool v1_nan = (v1 & defaultNaNF32UI) == quiet_nan32;
212
+    bool v2_nan = (v2 & defaultNaNF32UI) == quiet_nan32;
213
+    bool v1_snan = softfloat_isSigNaNF32UI(v1);
214
+    bool v2_snan = softfloat_isSigNaNF32UI(v2);
215
+    if (v1_snan || v2_snan) softfloat_raiseFlags(softfloat_flag_invalid);
216
+    if (v1_nan || v1_snan)
217
+        return (v2_nan || v2_snan) ? defaultNaNF32UI : v2;
218
+    else
219
+        if (v2_nan || v2_snan)
220
+            return v1;
221
+        else {
222
+            if ((v1 & 0x7fffffff) == 0 && (v2 & 0x7fffffff) == 0) {
223
+                return op == 0 ? ((v1 & 0x80000000) ? v1 : v2) : ((v1 & 0x80000000) ? v2 : v1);
224
+            } else {
225
+                float32_t v1f{ v1 }, v2f{ v2 };
226
+                return op == 0 ? (f32_lt(v1f, v2f) ? v1 : v2) : (f32_lt(v1f, v2f) ? v2 : v1);
227
+            }
228
+        }
229
+}
230
+
231
+uint32_t fclass_s( uint32_t v1 ){
232
+
233
+    float32_t a{v1};
234
+    union ui32_f32 uA;
235
+    uint_fast32_t uiA;
236
+
237
+    uA.f = a;
238
+    uiA = uA.ui;
239
+
240
+    uint_fast16_t infOrNaN = expF32UI( uiA ) == 0xFF;
241
+    uint_fast16_t subnormalOrZero = expF32UI( uiA ) == 0;
242
+    bool sign = signF32UI( uiA );
243
+    bool fracZero = fracF32UI( uiA ) == 0;
244
+    bool isNaN = isNaNF32UI( uiA );
245
+    bool isSNaN = softfloat_isSigNaNF32UI( uiA );
246
+
247
+    return
248
+        (  sign && infOrNaN && fracZero )          << 0 |
249
+        (  sign && !infOrNaN && !subnormalOrZero ) << 1 |
250
+        (  sign && subnormalOrZero && !fracZero )  << 2 |
251
+        (  sign && subnormalOrZero && fracZero )   << 3 |
252
+        ( !sign && infOrNaN && fracZero )          << 7 |
253
+        ( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
254
+        ( !sign && subnormalOrZero && !fracZero )  << 5 |
255
+        ( !sign && subnormalOrZero && fracZero )   << 4 |
256
+        ( isNaN &&  isSNaN )                       << 8 |
257
+        ( isNaN && !isSNaN )                       << 9;
258
+}
259
+
260
+uint64_t fclass_d(uint64_t v1  ){
261
+
262
+    float64_t a{v1};
263
+    union ui64_f64 uA;
264
+    uint_fast64_t uiA;
265
+
266
+    uA.f = a;
267
+    uiA = uA.ui;
268
+
269
+    uint_fast16_t infOrNaN = expF64UI( uiA ) == 0x7FF;
270
+    uint_fast16_t subnormalOrZero = expF64UI( uiA ) == 0;
271
+    bool sign = signF64UI( uiA );
272
+    bool fracZero = fracF64UI( uiA ) == 0;
273
+    bool isNaN = isNaNF64UI( uiA );
274
+    bool isSNaN = softfloat_isSigNaNF64UI( uiA );
275
+
276
+    return
277
+        (  sign && infOrNaN && fracZero )          << 0 |
278
+        (  sign && !infOrNaN && !subnormalOrZero ) << 1 |
279
+        (  sign && subnormalOrZero && !fracZero )  << 2 |
280
+        (  sign && subnormalOrZero && fracZero )   << 3 |
281
+        ( !sign && infOrNaN && fracZero )          << 7 |
282
+        ( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
283
+        ( !sign && subnormalOrZero && !fracZero )  << 5 |
284
+        ( !sign && subnormalOrZero && fracZero )   << 4 |
285
+        ( isNaN &&  isSNaN )                       << 8 |
286
+        ( isNaN && !isSNaN )                       << 9;
287
+}
288
+
289
+}
290
+

+ 6524
- 0
riscv/src/internal/vm_rv32gc.cpp
File diff suppressed because it is too large
View File


+ 371
- 237
riscv/src/internal/vm_rv32imac.cpp
File diff suppressed because it is too large
View File


+ 229
- 215
riscv/src/internal/vm_rv64ia.cpp
File diff suppressed because it is too large
View File


+ 74
- 0
riscv/src/iss/rv32gc.cpp View File

@@ -0,0 +1,74 @@
1
+////////////////////////////////////////////////////////////////////////////////
2
+// Copyright (C) 2017, MINRES Technologies GmbH
3
+// All rights reserved.
4
+// 
5
+// Redistribution and use in source and binary forms, with or without
6
+// modification, are permitted provided that the following conditions are met:
7
+// 
8
+// 1. Redistributions of source code must retain the above copyright notice,
9
+//    this list of conditions and the following disclaimer.
10
+// 
11
+// 2. Redistributions in binary form must reproduce the above copyright notice,
12
+//    this list of conditions and the following disclaimer in the documentation
13
+//    and/or other materials provided with the distribution.
14
+// 
15
+// 3. Neither the name of the copyright holder nor the names of its contributors
16
+//    may be used to endorse or promote products derived from this software
17
+//    without specific prior written permission.
18
+// 
19
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29
+// POSSIBILITY OF SUCH DAMAGE.
30
+//
31
+////////////////////////////////////////////////////////////////////////////////
32
+
33
+#include "util/ities.h"
34
+#include <util/logging.h>
35
+
36
+#include <elfio/elfio.hpp>
37
+#include <iss/arch/rv32gc.h>
38
+
39
+#ifdef __cplusplus
40
+extern "C" {
41
+#endif
42
+#include <ihex.h>
43
+#ifdef __cplusplus
44
+}
45
+#endif
46
+#include <fstream>
47
+#include <cstdio>
48
+#include <cstring>
49
+
50
+using namespace iss::arch;
51
+
52
+rv32gc::rv32gc() {
53
+    reg.icount=0;
54
+}
55
+
56
+rv32gc::~rv32gc(){
57
+}
58
+
59
+void rv32gc::reset(uint64_t address) {
60
+    for(size_t i=0; i<traits<rv32gc>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32gc>::reg_t),0));
61
+    reg.PC=address;
62
+    reg.NEXT_PC=reg.PC;
63
+    reg.trap_state=0;
64
+    reg.machine_state=0x0;
65
+}
66
+
67
+uint8_t* rv32gc::get_regs_base_ptr(){
68
+    return reinterpret_cast<uint8_t*>(&reg);
69
+}
70
+
71
+rv32gc::phys_addr_t rv32gc::virt2phys(const iss::addr_t &pc) {
72
+    return phys_addr_t(pc); // change logical address to physical address
73
+}
74
+

+ 8
- 3
riscv/src/main.cpp View File

@@ -39,6 +39,7 @@
39 39
 #include <boost/program_options.hpp>
40 40
 #include <iss/arch/riscv_hart_msu_vp.h>
41 41
 #include <iss/arch/rv32imac.h>
42
+#include <iss/arch/rv32gc.h>
42 43
 #include <iss/arch/rv64ia.h>
43 44
 #include <iss/jit/MCJIThelper.h>
44 45
 #include <iss/log_categories.h>
@@ -103,15 +104,19 @@ int main(int argc, char *argv[]) {
103 104
         // instantiate the simulator
104 105
         std::unique_ptr<iss::vm_if> vm{nullptr};
105 106
         std::string isa_opt(clim["isa"].as<std::string>());
106
-        iss::plugin::instruction_count ic_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
107
-        iss::plugin::cycle_estimate ce_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
107
+//        iss::plugin::instruction_count ic_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
108
+//        iss::plugin::cycle_estimate ce_plugin("riscv/gen_input/src-gen/rv32imac_cyles.txt");
108 109
         if (isa_opt.substr(0, 4)=="rv64") {
109 110
             iss::arch::rv64ia* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64ia>();
110 111
             vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
111
-        } else if (isa_opt.substr(0, 4)=="rv32") {
112
+        } else if (isa_opt.substr(0, 5)=="rv32i") {
112 113
             iss::arch::rv32imac* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>();
113 114
             vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
114 115
             //vm->register_plugin(ce_plugin);
116
+        } else if (isa_opt.substr(0, 5)=="rv32g") {
117
+            iss::arch::rv32gc* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32gc>();
118
+            vm = iss::create(cpu, clim["gdb-port"].as<unsigned>());
119
+            //vm->register_plugin(ce_plugin);
115 120
         } else {
116 121
             LOG(ERROR) << "Illegal argument value for '--isa': " << clim["isa"].as<std::string>() << std::endl;
117 122
             return 127;