Browse Source

Refactored core descriptions

eyck 4 months ago
parent
commit
3e8583977a

+ 50
- 0
riscv/gen_input/RISCVBase.core_desc View File

@@ -0,0 +1,50 @@
1
+InsructionSet RISCVBase {
2
+    constants {
3
+        XLEN,
4
+        fence:=0,
5
+        fencei:=1,
6
+        fencevmal:=2,
7
+        fencevmau:=3
8
+    }
9
+    
10
+    address_spaces { 
11
+        MEM[8], CSR[XLEN], FENCE[XLEN], RES[8]
12
+    }
13
+                
14
+    registers { 
15
+        [31:0]   X[XLEN],
16
+                PC[XLEN](is_pc),
17
+                alias ZERO[XLEN] is X[0],
18
+                alias RA[XLEN] is X[1],
19
+                alias SP[XLEN] is X[2],
20
+                alias GP[XLEN] is X[3],
21
+                alias TP[XLEN] is X[4],
22
+                alias T0[XLEN] is X[5],
23
+                alias T1[XLEN] is X[6],
24
+                alias T2[XLEN] is X[7],
25
+                alias S0[XLEN] is X[8],
26
+                alias S1[XLEN] is X[9],
27
+                alias A0[XLEN] is X[10],
28
+                alias A1[XLEN] is X[11],
29
+                alias A2[XLEN] is X[12],
30
+                alias A3[XLEN] is X[13],
31
+                alias A4[XLEN] is X[14],
32
+                alias A5[XLEN] is X[15],
33
+                alias A6[XLEN] is X[16],
34
+                alias A7[XLEN] is X[17],
35
+                alias S2[XLEN] is X[18],
36
+                alias S3[XLEN] is X[19],
37
+                alias S4[XLEN] is X[20],
38
+                alias S5[XLEN] is X[21],
39
+                alias S6[XLEN] is X[22],
40
+                alias S7[XLEN] is X[23],
41
+                alias S8[XLEN] is X[24],
42
+                alias S9[XLEN] is X[25],
43
+                alias S10[XLEN] is X[26],
44
+                alias S11[XLEN] is X[27],
45
+                alias T3[XLEN] is X[28],
46
+                alias T4[XLEN] is X[29],
47
+                alias T5[XLEN] is X[30],
48
+                alias T6[XLEN] is X[31]
49
+    }
50
+}

+ 0
- 104
riscv/gen_input/RV32A.core_desc View File

@@ -1,104 +0,0 @@
1
-import "RV32IBase.core_desc"
2
-
3
-InsructionSet RV32A extends RV32IBase{
4
-     
5
-    instructions{
6
-        LR.W {
7
-            encoding: b00010 | aq[0:0] | rl[0:0]  | b00000 | rs1[4:0] | b010 | rd[4:0] | b0101111;
8
-            args_disass: "{name(rd)}, {name(rs1)}";
9
-            if(rd!=0){
10
-                val offs[XLEN] <= X[rs1];
11
-                X[rd]<= sext(MEM[offs]{32}, XLEN);
12
-                RES[offs]{32}<=sext(-1, 32);
13
-            }
14
-        }
15
-        SC.W {
16
-            encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
17
-            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)}";
18
-            val offs[XLEN] <= X[rs1];
19
-            val res1[32] <= RES[offs]{32};
20
-            if(res1!=0)
21
-                MEM[offs]{32} <= X[rs2];
22
-            if(rd!=0) X[rd]<= choose(res1!=zext(0, 32), 0, 1);
23
-        }
24
-        AMOSWAP.W{
25
-            encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
26
-            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
27
-            val offs[XLEN]<=X[rs1];
28
-            if(rd!=0) X[rd]<=sext(MEM[offs]{32});
29
-            MEM[offs]{32}<=X[rs2];
30
-        }
31
-        AMOADD.W{
32
-            encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
33
-            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
34
-            val offs[XLEN]<=X[rs1];
35
-            val res1[XLEN] <= sext(MEM[offs]{32});
36
-            if(rd!=0) X[rd]<=res1;
37
-            val res2[XLEN]<=res1 + X[rs2];
38
-            MEM[offs]{32}<=res2;
39
-        }
40
-        AMOXOR.W{
41
-            encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
42
-            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
43
-            val offs[XLEN]<=X[rs1];
44
-            val res1[XLEN] <= sext(MEM[offs]{32});
45
-            if(rd!=0) X[rd]<=res1;
46
-            val res2[XLEN]<=res1 ^ X[rs2];
47
-            MEM[offs]{32}<=res2;
48
-        }
49
-        AMOAND.W{
50
-            encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
51
-            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
52
-            val offs[XLEN]<=X[rs1];
53
-            val res1[XLEN] <= sext(MEM[offs]{32});
54
-            if(rd!=0) X[rd]<=res1;
55
-            val res2[XLEN] <=res1 & X[rs2];
56
-            MEM[offs]{32}<=res2;
57
-        }
58
-        AMOOR.W {
59
-            encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
60
-            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
61
-            val offs[XLEN]<=X[rs1];
62
-            val res1[XLEN] <= sext(MEM[offs]{32});
63
-            if(rd!=0) X[rd]<=res1;
64
-            val res2[XLEN]<=res1 | X[rs2];
65
-            MEM[offs]{32}<=res2;
66
-        }
67
-        AMOMIN.W{
68
-            encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
69
-            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
70
-            val offs[XLEN]<=X[rs1];
71
-            val res1[XLEN] <= sext(MEM[offs]{32});
72
-            if(rd!=0) X[rd] <= res1;
73
-            val res2[XLEN] <= choose(res1's > X[rs2]s, X[rs2], res1);
74
-            MEM[offs]{32} <= res2;
75
-        }
76
-        AMOMAX.W{
77
-            encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
78
-            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
79
-            val offs[XLEN]<=X[rs1];
80
-            val res1[XLEN] <= sext(MEM[offs]{32});
81
-            if(rd!=0) X[rd]<=res1;
82
-            val res2[XLEN]<= choose(res1's<X[rs2]s, X[rs2], res1);
83
-            MEM[offs]{32}<=res2;
84
-        }
85
-        AMOMINU.W{
86
-            encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
87
-            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
88
-            val offs[XLEN]<=X[rs1];
89
-            val res1[XLEN] <= sext(MEM[offs]{32});
90
-            if(rd!=0) X[rd]<=res1;
91
-            val res2[XLEN]<= choose(res1>X[rs2], X[rs2], res1);
92
-            MEM[offs]{32}<=res2;
93
-        }
94
-        AMOMAXU.W{
95
-            encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
96
-            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
97
-            val offs[XLEN]<=X[rs1];
98
-            val res1[XLEN] <= sext(MEM[offs]{32});
99
-            if(rd!=0) X[rd] <= res1;
100
-            val res2[XLEN] <= choose(res1 < X[rs2], X[rs2], res1);
101
-            MEM[offs]{32} <= res2;
102
-        }
103
-    }
104
-}

riscv/gen_input/RV32IBase.core_desc → riscv/gen_input/RV32I.core_desc View File

@@ -1,52 +1,6 @@
1
-InsructionSet RV32IBase {
2
-    constants {
3
-        XLEN,
4
-        fence:=0,
5
-        fencei:=1,
6
-        fencevmal:=2,
7
-        fencevmau:=3
8
-    }
9
-    
10
-    address_spaces { 
11
-        MEM[8], CSR[XLEN], FENCE[XLEN], RES[8]
12
-    }
13
-                
14
-    registers { 
15
-        [31:0]   X[XLEN],
16
-                PC[XLEN](is_pc),
17
-                alias ZERO[XLEN] is X[0],
18
-                alias RA[XLEN] is X[1],
19
-                alias SP[XLEN] is X[2],
20
-                alias GP[XLEN] is X[3],
21
-                alias TP[XLEN] is X[4],
22
-                alias T0[XLEN] is X[5],
23
-                alias T1[XLEN] is X[6],
24
-                alias T2[XLEN] is X[7],
25
-                alias S0[XLEN] is X[8],
26
-                alias S1[XLEN] is X[9],
27
-                alias A0[XLEN] is X[10],
28
-                alias A1[XLEN] is X[11],
29
-                alias A2[XLEN] is X[12],
30
-                alias A3[XLEN] is X[13],
31
-                alias A4[XLEN] is X[14],
32
-                alias A5[XLEN] is X[15],
33
-                alias A6[XLEN] is X[16],
34
-                alias A7[XLEN] is X[17],
35
-                alias S2[XLEN] is X[18],
36
-                alias S3[XLEN] is X[19],
37
-                alias S4[XLEN] is X[20],
38
-                alias S5[XLEN] is X[21],
39
-                alias S6[XLEN] is X[22],
40
-                alias S7[XLEN] is X[23],
41
-                alias S8[XLEN] is X[24],
42
-                alias S9[XLEN] is X[25],
43
-                alias S10[XLEN] is X[26],
44
-                alias S11[XLEN] is X[27],
45
-                alias T3[XLEN] is X[28],
46
-                alias T4[XLEN] is X[29],
47
-                alias T5[XLEN] is X[30],
48
-                alias T6[XLEN] is X[31]
49
-    }
1
+import "RISCVBase.core_desc"
2
+
3
+InsructionSet RV32I extends RISCVBase{
50 4
      
51 5
     instructions { 
52 6
         LUI{

riscv/gen_input/RV64IBase.core_desc → riscv/gen_input/RV64I.core_desc View File

@@ -1,6 +1,6 @@
1
-import "RV32IBase.core_desc"
1
+import "RV32I.core_desc"
2 2
 
3
-InsructionSet RV64IBase extends RV32IBase {
3
+InsructionSet RV64I extends RV32I {
4 4
     instructions{
5 5
         LWU { //    80000104: 0000ef03            lwu t5,0(ra)
6 6
             encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0000011;

+ 0
- 65
riscv/gen_input/RV64M.core_desc View File

@@ -1,65 +0,0 @@
1
-import "RV64IBase.core_desc"
2
-
3
-InsructionSet RV64M extends RV64IBase {
4
-    instructions{       
5
-        MULW{
6
-            encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
7
-            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
8
-            if(rd != 0){
9
-                X[rd]<= sext(X[rs1]{32} * X[rs2]{32});
10
-            }
11
-        }
12
-        DIVW {
13
-            encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0111011;
14
-            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
15
-            if(rd != 0){
16
-                if(X[rs2]!=0){
17
-                    val M1[32] <= -1;
18
-                    val ONE[32] <= 1;
19
-                    val MMIN[32] <= ONE<<31;
20
-                    if(X[rs1]{32}==MMIN && X[rs2]{32}==M1)
21
-                        X[rd] <= -1<<31;
22
-                    else
23
-                        X[rd] <= sext(X[rs1]{32}s / X[rs2]{32}s);
24
-                }else 
25
-                    X[rd] <= -1;
26
-            }
27
-        }
28
-        DIVUW {
29
-            encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
30
-            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
31
-            if(rd != 0){
32
-	            if(X[rs2]{32}!=0)
33
-	                X[rd] <= sext(X[rs1]{32} / X[rs2]{32});
34
-	            else 
35
-	                X[rd] <= -1;
36
-	        }
37
-        }
38
-        REMW {
39
-            encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0111011;
40
-            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
41
-            if(rd != 0){
42
-                if(X[rs2]!=0) {
43
-                    val M1[32] <= -1; // constant -1 
44
-                    val ONE[32] <= 1;
45
-                    val MMIN[32] <= ONE<<31; // -2^(XLEN-1)
46
-                    if(X[rs1]{32}==MMIN && X[rs2]==M1)
47
-                        X[rd] <= 0;
48
-                    else
49
-                        X[rd] <= sext(X[rs1]{32}s % X[rs2]{32}s);
50
-                } else 
51
-                    X[rd] <= sext(X[rs1]{32});
52
-            }
53
-        }
54
-        REMUW {
55
-            encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0111011;
56
-            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
57
-            if(rd != 0){
58
-                if(X[rs2]{32}!=0)
59
-                    X[rd] <= sext(X[rs1]{32} % X[rs2]{32});
60
-                else 
61
-                    X[rd] <= sext(X[rs1]{32});
62
-            }
63
-        }
64
-    }
65
-}

riscv/gen_input/RV64A.core_desc → riscv/gen_input/RVA.core_desc View File

@@ -1,6 +1,109 @@
1
-import "RV64IBase.core_desc"
1
+import "RISCVBase.core_desc"
2 2
 
3
-InsructionSet RV64A extends RV64IBase {
3
+InsructionSet RV32A extends RISCVBase{
4
+     
5
+    instructions{
6
+        LR.W {
7
+            encoding: b00010 | aq[0:0] | rl[0:0]  | b00000 | rs1[4:0] | b010 | rd[4:0] | b0101111;
8
+            args_disass: "{name(rd)}, {name(rs1)}";
9
+            if(rd!=0){
10
+                val offs[XLEN] <= X[rs1];
11
+                X[rd]<= sext(MEM[offs]{32}, XLEN);
12
+                RES[offs]{32}<=sext(-1, 32);
13
+            }
14
+        }
15
+        SC.W {
16
+            encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
17
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)}";
18
+            val offs[XLEN] <= X[rs1];
19
+            val res1[32] <= RES[offs]{32};
20
+            if(res1!=0)
21
+                MEM[offs]{32} <= X[rs2];
22
+            if(rd!=0) X[rd]<= choose(res1!=zext(0, 32), 0, 1);
23
+        }
24
+        AMOSWAP.W{
25
+            encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
26
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
27
+            val offs[XLEN]<=X[rs1];
28
+            if(rd!=0) X[rd]<=sext(MEM[offs]{32});
29
+            MEM[offs]{32}<=X[rs2];
30
+        }
31
+        AMOADD.W{
32
+            encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
33
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
34
+            val offs[XLEN]<=X[rs1];
35
+            val res1[XLEN] <= sext(MEM[offs]{32});
36
+            if(rd!=0) X[rd]<=res1;
37
+            val res2[XLEN]<=res1 + X[rs2];
38
+            MEM[offs]{32}<=res2;
39
+        }
40
+        AMOXOR.W{
41
+            encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
42
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
43
+            val offs[XLEN]<=X[rs1];
44
+            val res1[XLEN] <= sext(MEM[offs]{32});
45
+            if(rd!=0) X[rd]<=res1;
46
+            val res2[XLEN]<=res1 ^ X[rs2];
47
+            MEM[offs]{32}<=res2;
48
+        }
49
+        AMOAND.W{
50
+            encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
51
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
52
+            val offs[XLEN]<=X[rs1];
53
+            val res1[XLEN] <= sext(MEM[offs]{32});
54
+            if(rd!=0) X[rd]<=res1;
55
+            val res2[XLEN] <=res1 & X[rs2];
56
+            MEM[offs]{32}<=res2;
57
+        }
58
+        AMOOR.W {
59
+            encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
60
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
61
+            val offs[XLEN]<=X[rs1];
62
+            val res1[XLEN] <= sext(MEM[offs]{32});
63
+            if(rd!=0) X[rd]<=res1;
64
+            val res2[XLEN]<=res1 | X[rs2];
65
+            MEM[offs]{32}<=res2;
66
+        }
67
+        AMOMIN.W{
68
+            encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
69
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
70
+            val offs[XLEN]<=X[rs1];
71
+            val res1[XLEN] <= sext(MEM[offs]{32});
72
+            if(rd!=0) X[rd] <= res1;
73
+            val res2[XLEN] <= choose(res1's > X[rs2]s, X[rs2], res1);
74
+            MEM[offs]{32} <= res2;
75
+        }
76
+        AMOMAX.W{
77
+            encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
78
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
79
+            val offs[XLEN]<=X[rs1];
80
+            val res1[XLEN] <= sext(MEM[offs]{32});
81
+            if(rd!=0) X[rd]<=res1;
82
+            val res2[XLEN]<= choose(res1's<X[rs2]s, X[rs2], res1);
83
+            MEM[offs]{32}<=res2;
84
+        }
85
+        AMOMINU.W{
86
+            encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
87
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
88
+            val offs[XLEN]<=X[rs1];
89
+            val res1[XLEN] <= sext(MEM[offs]{32});
90
+            if(rd!=0) X[rd]<=res1;
91
+            val res2[XLEN]<= choose(res1>X[rs2], X[rs2], res1);
92
+            MEM[offs]{32}<=res2;
93
+        }
94
+        AMOMAXU.W{
95
+            encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
96
+            args_disass: "{name(rd)}, {name(rs1)}, {name(rs2)} (aqu={aq},rel={rl})";
97
+            val offs[XLEN]<=X[rs1];
98
+            val res1[XLEN] <= sext(MEM[offs]{32});
99
+            if(rd!=0) X[rd] <= res1;
100
+            val res2[XLEN] <= choose(res1 < X[rs2], X[rs2], res1);
101
+            MEM[offs]{32} <= res2;
102
+        }
103
+    }
104
+}
105
+
106
+InsructionSet RV64A extends RV32A {
4 107
      
5 108
     instructions{
6 109
         LR.D {
@@ -104,4 +207,4 @@ InsructionSet RV64A extends RV64IBase {
104 207
             MEM[offs]{64} <= res2;
105 208
         }
106 209
     }
107
-}
210
+}

riscv/gen_input/RV32C.core_desc → riscv/gen_input/RVC.core_desc View File

@@ -1,16 +1,7 @@
1
-import "RV32IBase.core_desc"
1
+import "RISCVBase.core_desc"
2
+
3
+InsructionSet RV32IC extends RISCVBase{
2 4
 
3
-InsructionSet RV32IC {
4
-    constants {
5
-        XLEN
6
-    }
7
-    address_spaces { 
8
-        MEM[8]
9
-    }
10
-    registers { 
11
-        [31:0]   X[XLEN],
12
-                PC[XLEN](is_pc)
13
-    }
14 5
     instructions{
15 6
         JALR(no_cont){ // overwriting the implementation if rv32i, alignment does not need to be word
16 7
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
@@ -182,13 +173,9 @@ InsructionSet RV32IC {
182 173
 
183 174
 InsructionSet RV32FC extends RV32IC{
184 175
     constants {
185
-        XLEN, FLEN
186
-    }
187
-    address_spaces { 
188
-        MEM[8]
176
+        FLEN
189 177
     }
190 178
     registers { 
191
-        [31:0]   X[XLEN],
192 179
         [31:0]   F[FLEN]
193 180
     }
194 181
     instructions{
@@ -233,13 +220,9 @@ InsructionSet RV32FC extends RV32IC{
233 220
 
234 221
 InsructionSet RV32DC extends RV32IC{
235 222
     constants {
236
-        XLEN, FLEN
237
-    }
238
-    address_spaces { 
239
-        MEM[8]
223
+        FLEN
240 224
     }
241 225
     registers { 
242
-        [31:0]   X[XLEN],
243 226
         [31:0]   F[FLEN]
244 227
     }
245 228
     instructions{
@@ -283,16 +266,7 @@ InsructionSet RV32DC extends RV32IC{
283 266
 }
284 267
 
285 268
 InsructionSet RV64IC extends RV32IC {
286
-    constants {
287
-        XLEN
288
-    }
289
-    address_spaces { 
290
-        MEM[8]
291
-    }
292
-    registers { 
293
-        [31:0]   X[XLEN],
294
-                PC[XLEN](is_pc)
295
-    }
269
+
296 270
     instructions{
297 271
         C.LD {//(RV64/128) 
298 272
             encoding:b011 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
@@ -360,16 +334,7 @@ InsructionSet RV64IC extends RV32IC {
360 334
 }
361 335
 
362 336
 InsructionSet RV128IC extends RV64IC {
363
-    constants {
364
-        XLEN
365
-    }
366
-    address_spaces { 
367
-        MEM[8]
368
-    }
369
-    registers { 
370
-        [31:0]   X[XLEN],
371
-                PC[XLEN](is_pc)
372
-    }
337
+
373 338
     instructions{
374 339
         C.SRLI {//(RV128)
375 340
             encoding:b100 | shamt[5:5] | b00 | rs1[2:0] | shamt[4:0] | b01;

riscv/gen_input/RV32D.core_desc → riscv/gen_input/RVD.core_desc View File

@@ -1,6 +1,6 @@
1
-import "RV32IBase.core_desc"
1
+import "RISCVBase.core_desc"
2 2
 
3
-InsructionSet RV32D extends RV32IBase{
3
+InsructionSet RV32D extends RISCVBase{
4 4
     constants {
5 5
         FLEN, FFLAG_MASK := 0x1f
6 6
     } 
@@ -306,12 +306,7 @@ InsructionSet RV32D extends RV32IBase{
306 306
     }
307 307
 }
308 308
 InsructionSet RV64D extends RV32D{
309
-    constants {
310
-        FLEN, FFLAG_MASK := 0x1f
311
-    } 
312
-    registers {
313
-        [31:0]    F[FLEN],  FCSR[32]
314
-    }    
309
+
315 310
     instructions{
316 311
         FCVT.L.D {
317 312
             encoding: b1100001 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
@@ -359,7 +354,6 @@ InsructionSet RV64D extends RV32D{
359 354
             args_disass:"f{rd}, {name(rs1)}";
360 355
             F[rd] <= zext(X[rs1]);
361 356
         }
362
-
363 357
     }
364 358
 }
365 359
     

riscv/gen_input/RV32F.core_desc → riscv/gen_input/RVF.core_desc View File

@@ -1,6 +1,6 @@
1
-import "RV32IBase.core_desc"
1
+import "RV32I.core_desc"
2 2
 
3
-InsructionSet RV32F extends RV32IBase{
3
+InsructionSet RV32F extends RV32I{
4 4
     constants {
5 5
         FLEN, FFLAG_MASK := 0x1f
6 6
     } 
@@ -355,12 +355,7 @@ InsructionSet RV32F extends RV32IBase{
355 355
 }
356 356
 
357 357
 InsructionSet RV64F extends RV32F{
358
-    constants {
359
-        FLEN, FFLAG_MASK := 0x1f
360
-    } 
361
-    registers {
362
-        [31:0]    F[FLEN],  FCSR[32]
363
-    }    
358
+
364 359
     instructions{
365 360
         FCVT.L.S { // fp to 64bit signed integer
366 361
             encoding: b1100000 | b00010 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;

riscv/gen_input/RV32M.core_desc → riscv/gen_input/RVM.core_desc View File

@@ -1,6 +1,6 @@
1
-import "RV32IBase.core_desc"
1
+import "RISCVBase.core_desc"
2 2
 
3
-InsructionSet RV32M extends RV32IBase {
3
+InsructionSet RV32M extends RISCVBase {
4 4
     constants {
5 5
         MAXLEN:=128
6 6
     }
@@ -92,4 +92,69 @@ InsructionSet RV32M extends RV32IBase {
92 92
             }
93 93
         }
94 94
     }
95
-}
95
+}
96
+
97
+InsructionSet RV64M extends RV32M {
98
+    instructions{       
99
+        MULW{
100
+            encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011;
101
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
102
+            if(rd != 0){
103
+                X[rd]<= sext(X[rs1]{32} * X[rs2]{32});
104
+            }
105
+        }
106
+        DIVW {
107
+            encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0111011;
108
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
109
+            if(rd != 0){
110
+                if(X[rs2]!=0){
111
+                    val M1[32] <= -1;
112
+                    val ONE[32] <= 1;
113
+                    val MMIN[32] <= ONE<<31;
114
+                    if(X[rs1]{32}==MMIN && X[rs2]{32}==M1)
115
+                        X[rd] <= -1<<31;
116
+                    else
117
+                        X[rd] <= sext(X[rs1]{32}s / X[rs2]{32}s);
118
+                }else 
119
+                    X[rd] <= -1;
120
+            }
121
+        }
122
+        DIVUW {
123
+            encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011;
124
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
125
+            if(rd != 0){
126
+	            if(X[rs2]{32}!=0)
127
+	                X[rd] <= sext(X[rs1]{32} / X[rs2]{32});
128
+	            else 
129
+	                X[rd] <= -1;
130
+	        }
131
+        }
132
+        REMW {
133
+            encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0111011;
134
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
135
+            if(rd != 0){
136
+                if(X[rs2]!=0) {
137
+                    val M1[32] <= -1; // constant -1 
138
+                    val ONE[32] <= 1;
139
+                    val MMIN[32] <= ONE<<31; // -2^(XLEN-1)
140
+                    if(X[rs1]{32}==MMIN && X[rs2]==M1)
141
+                        X[rd] <= 0;
142
+                    else
143
+                        X[rd] <= sext(X[rs1]{32}s % X[rs2]{32}s);
144
+                } else 
145
+                    X[rd] <= sext(X[rs1]{32});
146
+            }
147
+        }
148
+        REMUW {
149
+            encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0111011;
150
+            args_disass:"{name(rd)}, {name(rs1)}, {name(rs2)}";
151
+            if(rd != 0){
152
+                if(X[rs2]{32}!=0)
153
+                    X[rd] <= sext(X[rs1]{32} % X[rs2]{32});
154
+                else 
155
+                    X[rd] <= sext(X[rs1]{32});
156
+            }
157
+        }
158
+    }
159
+}
160
+

+ 11
- 13
riscv/gen_input/minres_rv.core_desc View File

@@ -1,14 +1,12 @@
1
-import "RV32IBase.core_desc"
2
-import "RV32M.core_desc"
3
-import "RV32A.core_desc"
4
-import "RV32C.core_desc"
5
-import "RV32F.core_desc"
6
-import "RV32D.core_desc"
7
-import "RV64IBase.core_desc"
8
-import "RV64M.core_desc"
9
-import "RV64A.core_desc"
1
+import "RV32I.core_desc"
2
+import "RV64I.core_desc"
3
+import "RVM.core_desc"
4
+import "RVA.core_desc"
5
+import "RVC.core_desc"
6
+import "RVF.core_desc"
7
+import "RVD.core_desc"
10 8
 
11
-Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
9
+Core RV32IMAC provides RV32I, RV32M, RV32A, RV32IC {
12 10
     constants {
13 11
         XLEN:=32;
14 12
         PCLEN:=32;
@@ -20,7 +18,7 @@ Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
20 18
     }
21 19
 }
22 20
 
23
-Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32DC {
21
+Core RV32GC provides RV32I, RV32M, RV32A, RV32F, RV32D, RV32IC, RV32FC, RV32DC {
24 22
     constants {
25 23
         XLEN:=32;
26 24
         FLEN:=64;
@@ -33,7 +31,7 @@ Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32
33 31
     }
34 32
 }
35 33
 
36
-Core RV64I provides RV64IBase {
34
+Core RV64I provides RV64I {
37 35
     constants {
38 36
         XLEN:=64;
39 37
         PCLEN:=64;
@@ -45,7 +43,7 @@ Core RV64I provides RV64IBase {
45 43
     }
46 44
 }
47 45
 
48
-Core RV64GC provides RV64IC, RV64A, RV64M, RV32A, RV32M, RV64F, RV64D, RV32FC, RV32DC {
46
+Core RV64GC provides RV64I, RV64M, RV64A, RV64F, RV64D, RV64IC, RV32FC, RV32DC {
49 47
     constants {
50 48
         XLEN:=64;
51 49
         FLEN:=64;

+ 2150
- 2150
riscv/src/internal/vm_rv32gc.cpp
File diff suppressed because it is too large
View File


+ 1691
- 1691
riscv/src/internal/vm_rv32imac.cpp
File diff suppressed because it is too large
View File


+ 3915
- 3889
riscv/src/internal/vm_rv64gc.cpp
File diff suppressed because it is too large
View File