Browse Source

Adapted descriptions to improved Core DSL and regenerated code

Eyck Jentzsch 1 year ago
parent
commit
19b660962b

+ 3
- 4
.cproject View File

@@ -10,15 +10,14 @@
10 10
 					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
11 11
 					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
12 12
 					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
13
-					<extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
14 13
 				</extensions>
15 14
 			</storageModule>
16 15
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
17
-				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="cdt.managedbuild.config.gnu.exe.debug.1751741082" name="Debug" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=" parent="cdt.managedbuild.config.gnu.exe.debug">
16
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="cdt.managedbuild.config.gnu.exe.debug.1751741082" name="Debug" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=" parent="cdt.managedbuild.config.gnu.exe.debug">
18 17
 					<folderInfo id="cdt.managedbuild.config.gnu.exe.debug.1751741082." name="/" resourcePath="">
19 18
 						<toolChain id="cdt.managedbuild.toolchain.gnu.exe.debug.1289745146" name="Linux GCC" superClass="cdt.managedbuild.toolchain.gnu.exe.debug">
20 19
 							<targetPlatform binaryParser="org.eclipse.cdt.core.GNU_ELF;org.eclipse.cdt.core.ELF" id="cdt.managedbuild.target.gnu.platform.exe.debug.1460698591" name="Debug Platform" superClass="cdt.managedbuild.target.gnu.platform.exe.debug"/>
21
-							<builder buildPath="/DBT-RISE-RISCV/build/{ConfigName}" id="de.marw.cdt.cmake.core.genmakebuilder.2061143699" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CMake Builder (GNU Make)" parallelBuildOn="true" parallelizationNumber="optimal" superClass="de.marw.cdt.cmake.core.genmakebuilder"/>
20
+							<builder buildPath="/DBT-RISE-RISCV/build/Debug" id="de.marw.cdt.cmake.core.genscriptbuilder.2135578907" keepEnvironmentInBuildfile="false" name="CMake Builder (portable)" parallelBuildOn="false" superClass="de.marw.cdt.cmake.core.genscriptbuilder"/>
22 21
 							<tool id="cdt.managedbuild.tool.gnu.archiver.base.366643800" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
23 22
 							<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.1510612390" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug">
24 23
 								<option id="gnu.cpp.compiler.exe.debug.option.optimization.level.1768317780" name="Optimization Level" superClass="gnu.cpp.compiler.exe.debug.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
@@ -46,7 +45,7 @@
46 45
 			</storageModule>
47 46
 			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
48 47
 			<storageModule buildDir="build/${ConfigName}" moduleId="de.marw.cdt.cmake.core.settings">
49
-				<options clearCache="true"/>
48
+				<options/>
50 49
 				<linux command="cmake" generator="UnixMakefiles" use-default="true">
51 50
 					<defs>
52 51
 						<def name="CMAKE_VERBOSE_MAKEFILE" type="BOOL" val="OFF"/>

+ 1
- 1
dbt-core

@@ -1 +1 @@
1
-Subproject commit 393c374cac4950e629036dda1615abedf866961f
1
+Subproject commit 23dbab0b768d122c492110d1db34408e9ae787f3

+ 104
- 104
riscv/gen_input/RV32A.core_desc View File

@@ -1,108 +1,108 @@
1 1
 import "RV32IBase.core_desc"
2 2
 
3 3
 InsructionSet RV32A extends RV32IBase{
4
-	 
5
-	address_spaces { 
6
-		RES[8]
7
-	}
8
-	
9
-	instructions{
10
-		LR.W {
11
-			encoding: b00010 | aq[0:0] | rl[0:0]  | b00000 | rs1[4:0] | b010 | rd[4:0] | b0101111;
12
-			args_disass: "x%rd$d, x%rs1$d";
13
-			if(rd!=0){
14
-				val offs[XLEN] <= X[rs1];
15
-				X[rd]<= sext(MEM[offs]{32}, XLEN);
16
-				RES[offs]{32}<=sext(-1, 32);
17
-			}
18
-		}
19
-		SC.W {
20
-			encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
21
-			args_disass: "x%rd$d, x%rs1$d, x%rs2$d";
22
-			val offs[XLEN] <= X[rs1];
23
-			val res1[32] <= RES[offs]{32};
24
-			if(res1!=0)
25
-				MEM[offs]{32} <= X[rs2];
26
-			if(rd!=0) X[rd]<= choose(res1!=0, 0, 1);
27
-		}
28
-		AMOSWAP.W{
29
-			encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
30
-			args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
31
-			val offs[XLEN]<=X[rs1];
32
-			if(rd!=0) X[rd]<=sext(MEM[offs]{32});
33
-			MEM[offs]{32}<=X[rs2];
34
-		}
35
-		AMOADD.W{
36
-			encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
37
-			args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
38
-			val offs[XLEN]<=X[rs1];
39
-			val res1[XLEN] <= sext(MEM[offs]{32});
40
-			if(rd!=0) X[rd]<=res1;
41
-			val res2[XLEN]<=res1 + X[rs2];
42
-			MEM[offs]{32}<=res2;
43
-		}
44
-		AMOXOR.W{
45
-			encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
46
-			args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
47
-			val offs[XLEN]<=X[rs1];
48
-			val res1[XLEN] <= sext(MEM[offs]{32});
49
-			if(rd!=0) X[rd]<=res1;
50
-			val res2[XLEN]<=res1 ^ X[rs2];
51
-			MEM[offs]{32}<=res2;
52
-		}
53
-		AMOAND.W{
54
-			encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
55
-			args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
56
-			val offs[XLEN]<=X[rs1];
57
-			val res1[XLEN] <= sext(MEM[offs]{32});
58
-			if(rd!=0) X[rd]<=res1;
59
-			val res2[XLEN] <=res1 & X[rs2];
60
-			MEM[offs]{32}<=res2;
61
-		}
62
-		AMOOR.W {
63
-			encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
64
-			args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
65
-			val offs[XLEN]<=X[rs1];
66
-			val res1[XLEN] <= sext(MEM[offs]{32});
67
-			if(rd!=0) X[rd]<=res1;
68
-			val res2[XLEN]<=res1 | X[rs2];
69
-			MEM[offs]{32}<=res2;
70
-		}
71
-		AMOMIN.W{
72
-			encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
73
-			args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
74
-			val offs[XLEN]<=X[rs1];
75
-			val res1[XLEN] <= sext(MEM[offs]{32});
76
-			if(rd!=0) X[rd]<=res1;
77
-			val res2[XLEN]<= choose(res1's>X[rs2]s, X[rs2], res1);
78
-			MEM[offs]{32}<=res2;
79
-		}
80
-		AMOMAX.W{
81
-			encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
82
-			args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
83
-			val offs[XLEN]<=X[rs1];
84
-			val res1[XLEN] <= sext(MEM[offs]{32});
85
-			if(rd!=0) X[rd]<=res1;
86
-			val res2[XLEN]<= choose(res1's<X[rs2]s, X[rs2], res1);
87
-			MEM[offs]{32}<=res2;
88
-		}
89
-		AMOMINU.W{
90
-			encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
91
-			args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
92
-			val offs[XLEN]<=X[rs1];
93
-			val res1[XLEN] <= zext(MEM[offs]{32});
94
-			if(rd!=0) X[rd]<=res1;
95
-			val res2[XLEN]<= choose(res1>X[rs2], X[rs2], res1);
96
-			MEM[offs]{32}<=res2;
97
-		}
98
-		AMOMAXU.W{
99
-			encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
100
-			args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
101
-			val offs[XLEN]<=X[rs1];
102
-			val res1[XLEN] <= zext(MEM[offs]{32});
103
-			if(rd!=0) X[rd]<=res1;
104
-			val res2[XLEN]<= choose(res1'u<X[rs2]'u, X[rs2], res1);
105
-			MEM[offs]{32}<=res2;
106
-		}
107
-	}
4
+     
5
+    address_spaces { 
6
+        RES[8]
7
+    }
8
+    
9
+    instructions{
10
+        LR.W {
11
+            encoding: b00010 | aq[0:0] | rl[0:0]  | b00000 | rs1[4:0] | b010 | rd[4:0] | b0101111;
12
+            args_disass: "x%rd$d, x%rs1$d";
13
+            if(rd!=0){
14
+                val offs[XLEN] <= X[rs1];
15
+                X[rd]<= sext(MEM[offs]{32}, XLEN);
16
+                RES[offs]{32}<=sext(-1, 32);
17
+            }
18
+        }
19
+        SC.W {
20
+            encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
21
+            args_disass: "x%rd$d, x%rs1$d, x%rs2$d";
22
+            val offs[XLEN] <= X[rs1];
23
+            val res1[32] <= RES[offs]{32};
24
+            if(res1!=0)
25
+                MEM[offs]{32} <= X[rs2];
26
+            if(rd!=0) X[rd]<= choose(res1!=0, 0, 1);
27
+        }
28
+        AMOSWAP.W{
29
+            encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
30
+            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
31
+            val offs[XLEN]<=X[rs1];
32
+            if(rd!=0) X[rd]<=sext(MEM[offs]{32});
33
+            MEM[offs]{32}<=X[rs2];
34
+        }
35
+        AMOADD.W{
36
+            encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
37
+            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
38
+            val offs[XLEN]<=X[rs1];
39
+            val res1[XLEN] <= sext(MEM[offs]{32});
40
+            if(rd!=0) X[rd]<=res1;
41
+            val res2[XLEN]<=res1 + X[rs2];
42
+            MEM[offs]{32}<=res2;
43
+        }
44
+        AMOXOR.W{
45
+            encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
46
+            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
47
+            val offs[XLEN]<=X[rs1];
48
+            val res1[XLEN] <= sext(MEM[offs]{32});
49
+            if(rd!=0) X[rd]<=res1;
50
+            val res2[XLEN]<=res1 ^ X[rs2];
51
+            MEM[offs]{32}<=res2;
52
+        }
53
+        AMOAND.W{
54
+            encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
55
+            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
56
+            val offs[XLEN]<=X[rs1];
57
+            val res1[XLEN] <= sext(MEM[offs]{32});
58
+            if(rd!=0) X[rd]<=res1;
59
+            val res2[XLEN] <=res1 & X[rs2];
60
+            MEM[offs]{32}<=res2;
61
+        }
62
+        AMOOR.W {
63
+            encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
64
+            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
65
+            val offs[XLEN]<=X[rs1];
66
+            val res1[XLEN] <= sext(MEM[offs]{32});
67
+            if(rd!=0) X[rd]<=res1;
68
+            val res2[XLEN]<=res1 | X[rs2];
69
+            MEM[offs]{32}<=res2;
70
+        }
71
+        AMOMIN.W{
72
+            encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
73
+            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
74
+            val offs[XLEN]<=X[rs1];
75
+            val res1[XLEN] <= sext(MEM[offs]{32});
76
+            if(rd!=0) X[rd]<=res1;
77
+            val res2[XLEN]<= choose(res1's>X[rs2]s, X[rs2], res1);
78
+            MEM[offs]{32}<=res2;
79
+        }
80
+        AMOMAX.W{
81
+            encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
82
+            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
83
+            val offs[XLEN]<=X[rs1];
84
+            val res1[XLEN] <= sext(MEM[offs]{32});
85
+            if(rd!=0) X[rd]<=res1;
86
+            val res2[XLEN]<= choose(res1's<X[rs2]s, X[rs2], res1);
87
+            MEM[offs]{32}<=res2;
88
+        }
89
+        AMOMINU.W{
90
+            encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
91
+            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
92
+            val offs[XLEN]<=X[rs1];
93
+            val res1[XLEN] <= zext(MEM[offs]{32});
94
+            if(rd!=0) X[rd]<=res1;
95
+            val res2[XLEN]<= choose(res1>X[rs2], X[rs2], res1);
96
+            MEM[offs]{32}<=res2;
97
+        }
98
+        AMOMAXU.W{
99
+            encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111;
100
+            args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)";
101
+            val offs[XLEN]<=X[rs1];
102
+            val res1[XLEN] <= zext(MEM[offs]{32});
103
+            if(rd!=0) X[rd]<=res1;
104
+            val res2[XLEN]<= choose(res1'u<X[rs2]'u, X[rs2], res1);
105
+            MEM[offs]{32}<=res2;
106
+        }
107
+    }
108 108
 }

+ 316
- 345
riscv/gen_input/RV32C.core_desc View File

@@ -1,17 +1,17 @@
1 1
 import "RV32IBase.core_desc"
2 2
 
3 3
 InsructionSet RV32IC {
4
-	constants {
5
-		XLEN
6
-	}
7
-	address_spaces { 
8
-		MEM[8]
9
-	}
10
-	registers { 
11
-		[31:0]   X[XLEN],
12
-				PC[XLEN](is_pc)
13
-	}
14
-	instructions{
4
+    constants {
5
+        XLEN
6
+    }
7
+    address_spaces { 
8
+        MEM[8]
9
+    }
10
+    registers { 
11
+        [31:0]   X[XLEN],
12
+                PC[XLEN](is_pc)
13
+    }
14
+    instructions{
15 15
         JALR(no_cont){ // overwriting the implementation if rv32i, alignment does not need to be word
16 16
             encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
17 17
             args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
@@ -19,366 +19,337 @@ InsructionSet RV32IC {
19 19
             val ret[XLEN] <= X[rs1]+ imm;
20 20
             PC<=ret& ~0x1;
21 21
         }
22
-		C.ADDI4SPN { //(RES, imm=0)
23
-			encoding: b000 | imm[5:4] | imm[9:6] | imm[2:2] | imm[3:3] | rd[2:0] | b00;
24
-			args_disass: "x%rd$d, 0x%imm$05x";
25
-			if(imm == 0) raise(0, 2);
26
-			val rd_idx[5] <= rd+8;
27
-			val x2_idx[5] <= 2;
28
-			X[rd_idx] <= X[x2_idx] + imm;
29
-		}
30
-		C.LW { // (RV32)
31
-			encoding: b010 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
32
-			args_disass: "x(8+%rd$d), x(8+%rs1$d), 0x%uimm$05x";
33
-			val rs1_idx[5] <= rs1+8;
34
-			val rd_idx[5] <= rd+8;
35
-			val offs[XLEN] <= X[rs1_idx]+uimm;
36
-			X[rd_idx] <= MEM[offs]{32};
37
-		}
38
-		C.SW {//(RV32)
39
-			encoding: b110 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
40
-			args_disass: "x(8+%rs1$d), x(8+%rs2$d), 0x%uimm$05x";
41
-			val rs1_idx[5] <= rs1+8;
42
-			val rs2_idx[5] <= rs2+8;
43
-			val offs[XLEN] <= X[rs1_idx]+uimm;
44
-			MEM[offs]{32} <= X[rs2_idx];
45
-		}
46
-		C.ADDI {//(RV32)
47
-			encoding:b000 | imm[5:5]s | rs1[4:0] | imm[4:0]s | b01;
48
-			args_disass: "x%rs1$d, 0x%imm$05x";
49
-			X[rs1] <= X[rs1] + imm;
50
-		}
51
-		C.NOP {
52
-			encoding:b000 | b0 | b00000 | b00000 | b01;
53
-		}
22
+        C.ADDI4SPN { //(RES, imm=0)
23
+            encoding: b000 | imm[5:4] | imm[9:6] | imm[2:2] | imm[3:3] | rd[2:0] | b00;
24
+            args_disass: "x%rd$d, 0x%imm$05x";
25
+            if(imm == 0) raise(0, 2);
26
+            X[rd+8] <= X[2] + imm;
27
+        }
28
+        C.LW { // (RV32)
29
+            encoding: b010 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
30
+            args_disass: "x(8+%rd$d), x(8+%rs1$d), 0x%uimm$05x";
31
+            val offs[XLEN] <= X[rs1+8]+uimm;
32
+            X[rd+8] <= MEM[offs]{32};
33
+        }
34
+        C.SW {//(RV32)
35
+            encoding: b110 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
36
+            args_disass: "x(8+%rs1$d), x(8+%rs2$d), 0x%uimm$05x";
37
+            val offs[XLEN] <= X[rs1+8]+uimm;
38
+            MEM[offs]{32} <= X[rs2+8];
39
+        }
40
+        C.ADDI {//(RV32)
41
+            encoding:b000 | imm[5:5]s | rs1[4:0] | imm[4:0]s | b01;
42
+            args_disass: "x%rs1$d, 0x%imm$05x";
43
+            X[rs1] <= X[rs1] + imm;
44
+        }
45
+        C.NOP {
46
+            encoding:b000 | b0 | b00000 | b00000 | b01;
47
+        }
54 48
         // C.JAL will be overwritten by C.ADDIW for RV64/128
55
-		C.JAL(no_cont) {//(RV32)
56
-			encoding: b001 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
57
-			args_disass: "0x%imm$05x";
58
-			val rd[5] <= 1;
59
-			X[rd] <= PC+2;
60
-			PC<=PC+imm;
61
-		}
62
-		C.LI {//(RV32)
63
-			encoding:b010 | imm[5:5]s | rd[4:0] | imm[4:0]s | b01;
64
-			args_disass: "x%rd$d, 0x%imm$05x";
65
-			if(rd == 0)	raise(0, 2);   //TODO: should it be handled as trap?
66
-			X[rd] <= imm;
67
-		}
68
-		// order matters here as C.ADDI16SP overwrites C.LUI vor rd==2
69
-		C.LUI {//(RV32)
70
-			encoding:b011 | imm[17:17]s | rd[4:0] | imm[16:12]s | b01;
71
-			args_disass: "x%rd$d, 0x%imm$05x";
72
-			if(rd == 0) raise(0, 2);   //TODO: should it be handled as trap?
73
-			if(imm == 0) raise(0, 2);   //TODO: should it be handled as trap?
74
-			X[rd] <= imm;
75
-		}
76
-		C.ADDI16SP {//(RV32)
77
-			encoding:b011 | imm[9:9]s | b00010 | imm[4:4]s | imm[6:6]s | imm[8:7]s | imm[5:5]s | b01;
78
-			args_disass: "0x%imm$05x";
79
-			val x2_idx[5] <= 2;
80
-			X[x2_idx] <= X[x2_idx]s + imm;
81
-		}
82
-		C.SRLI {//(RV32 nse)
83
-			encoding:b100 | b0 | b00 | rs1[2:0] | shamt[4:0] | b01;
84
-			args_disass: "x(8+%rs1$d), %shamt$d";
85
-			val rs1_idx[5] <= rs1+8;
86
-			X[rs1_idx] <= shrl(X[rs1_idx], shamt);
87
-		}
88
-		C.SRAI {//(RV32)
89
-			encoding:b100 | b0 | b01 | rs1[2:0] | shamt[4:0] | b01;
90
-			args_disass: "x(8+%rs1$d), %shamt$d";
91
-			val rs1_idx[5] <= rs1+8;
92
-			X[rs1_idx] <= shra(X[rs1_idx], shamt);
93
-		}
94
-		C.ANDI {//(RV32)
95
-			encoding:b100 | imm[5:5]s | b10 | rs1[2:0] | imm[4:0]s | b01;
96
-			args_disass: "x(8+%rs1$d), 0x%imm$05x";
97
-			val rs1_idx[5] <= rs1 + 8;
98
-			X[rs1_idx] <= X[rs1_idx] & imm;
99
-		}
100
-		C.SUB {//(RV32)
101
-			encoding:b100 | b0 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
102
-			args_disass: "x(8+%rd$d), x(8+%rs2$d)";
103
-			val rd_idx[5] <= rd + 8;
104
-			val rs2_idx[5] <= rs2 + 8;
105
-			X[rd_idx] <= X[rd_idx] - X[rs2_idx];
106
-		}
107
-		C.XOR {//(RV32)
108
-			encoding:b100 | b0 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
109
-			args_disass: "x(8+%rd$d), x(8+%rs2$d)";
110
-			val rd_idx[5] <= rd + 8;
111
-			val rs2_idx[5] <= rs2 + 8;
112
-			X[rd_idx] <= X[rd_idx] ^ X[rs2_idx];
113
-		}
114
-		C.OR {//(RV32)
115
-			encoding:b100 | b0 | b11 | rd[2:0] | b10 | rs2[2:0] | b01;
116
-			args_disass: "x(8+%rd$d), x(8+%rs2$d)";
117
-			val rd_idx[5] <= rd + 8;
118
-			val rs2_idx[5] <= rs2 + 8;
119
-			X[rd_idx] <= X[rd_idx] | X[rs2_idx];
120
-		}
121
-		C.AND {//(RV32)
122
-			encoding:b100 | b0 | b11 | rd[2:0] | b11 | rs2[2:0] | b01;
123
-			args_disass: "x(8+%rd$d), x(8+%rs2$d)";
124
-			val rd_idx[5] <= rd + 8;
125
-			val rs2_idx[5] <= rs2 + 8;
126
-			X[rd_idx] <= X[rd_idx] & X[rs2_idx];
127
-		}
128
-		C.J(no_cont) {//(RV32)
129
-			encoding:b101 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
130
-			args_disass: "0x%imm$05x";
131
-			PC<=PC+imm;
132
-		}
133
-		C.BEQZ(no_cont,cond) {//(RV32)
134
-			encoding:b110 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s |imm[2:1]s | imm[5:5]s | b01;
135
-			args_disass: "x(8+%rs1$d), 0x%imm$05x";
136
-			val rs1_idx[5] <= rs1+8;
137
-			PC<=choose(X[rs1_idx]==0, PC+imm, PC+2);
138
-		}
139
-		C.BNEZ(no_cont,cond) {//(RV32)
140
-			encoding:b111 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s | imm[2:1]s | imm[5:5]s | b01;
141
-			args_disass: "x(8+%rs1$d), 0x%imm$05x";
49
+        C.JAL(no_cont) {//(RV32)
50
+            encoding: b001 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
51
+            args_disass: "0x%imm$05x";
52
+            X[1] <= PC+2;
53
+            PC<=PC+imm;
54
+        }
55
+        C.LI {//(RV32)
56
+            encoding:b010 | imm[5:5]s | rd[4:0] | imm[4:0]s | b01;
57
+            args_disass: "x%rd$d, 0x%imm$05x";
58
+            if(rd == 0)    raise(0, 2);   //TODO: should it be handled as trap?
59
+            X[rd] <= imm;
60
+        }
61
+        // order matters here as C.ADDI16SP overwrites C.LUI vor rd==2
62
+        C.LUI {//(RV32)
63
+            encoding:b011 | imm[17:17]s | rd[4:0] | imm[16:12]s | b01;
64
+            args_disass: "x%rd$d, 0x%imm$05x";
65
+            if(rd == 0) raise(0, 2);   //TODO: should it be handled as trap?
66
+            if(imm == 0) raise(0, 2);   //TODO: should it be handled as trap?
67
+            X[rd] <= imm;
68
+        }
69
+        C.ADDI16SP {//(RV32)
70
+            encoding:b011 | imm[9:9]s | b00010 | imm[4:4]s | imm[6:6]s | imm[8:7]s | imm[5:5]s | b01;
71
+            args_disass: "0x%imm$05x";
72
+            X[2] <= X[2]s + imm;
73
+        }
74
+        C.SRLI {//(RV32 nse)
75
+            encoding:b100 | b0 | b00 | rs1[2:0] | shamt[4:0] | b01;
76
+            args_disass: "x(8+%rs1$d), %shamt$d";
77
+            val rs1_idx[5] <= rs1+8;
78
+            X[rs1_idx] <= shrl(X[rs1_idx], shamt);
79
+        }
80
+        C.SRAI {//(RV32)
81
+            encoding:b100 | b0 | b01 | rs1[2:0] | shamt[4:0] | b01;
82
+            args_disass: "x(8+%rs1$d), %shamt$d";
142 83
             val rs1_idx[5] <= rs1+8;
143
-			PC<=choose(X[rs1_idx]!=0, PC+imm, PC+2);
144
-		}
145
-		C.SLLI {//(RV32)
146
-			encoding:b000 | b0 | rs1[4:0] | shamt[4:0] | b10;
147
-			args_disass: "x%rs1$d, %shamt$d";
148
-			if(rs1 == 0) raise(0, 2);
149
-			X[rs1] <= shll(X[rs1], shamt);
150
-		}
151
-		C.LWSP {//
152
-			encoding:b010 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
153
-			args_disass: "x%rd$d, sp, 0x%uimm$05x";
154
-			val x2_idx[5] <= 2;
155
-			val offs[XLEN] <= X[x2_idx] + uimm;
156
-			X[rd] <= MEM[offs]{32};
157
-		}
158
-		// order matters as C.JR is a special case of C.MV
84
+            X[rs1_idx] <= shra(X[rs1_idx], shamt);
85
+        }
86
+        C.ANDI {//(RV32)
87
+            encoding:b100 | imm[5:5]s | b10 | rs1[2:0] | imm[4:0]s | b01;
88
+            args_disass: "x(8+%rs1$d), 0x%imm$05x";
89
+            val rs1_idx[5] <= rs1 + 8;
90
+            X[rs1_idx] <= X[rs1_idx] & imm;
91
+        }
92
+        C.SUB {//(RV32)
93
+            encoding:b100 | b0 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
94
+            args_disass: "x(8+%rd$d), x(8+%rs2$d)";
95
+            val rd_idx[5] <= rd + 8;
96
+            X[rd_idx] <= X[rd_idx] - X[rs2 + 8];
97
+        }
98
+        C.XOR {//(RV32)
99
+            encoding:b100 | b0 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
100
+            args_disass: "x(8+%rd$d), x(8+%rs2$d)";
101
+            val rd_idx[5] <= rd + 8;
102
+            X[rd_idx] <= X[rd_idx] ^ X[rs2 + 8];
103
+        }
104
+        C.OR {//(RV32)
105
+            encoding:b100 | b0 | b11 | rd[2:0] | b10 | rs2[2:0] | b01;
106
+            args_disass: "x(8+%rd$d), x(8+%rs2$d)";
107
+            val rd_idx[5] <= rd + 8;
108
+            X[rd_idx] <= X[rd_idx] | X[rs2 + 8];
109
+        }
110
+        C.AND {//(RV32)
111
+            encoding:b100 | b0 | b11 | rd[2:0] | b11 | rs2[2:0] | b01;
112
+            args_disass: "x(8+%rd$d), x(8+%rs2$d)";
113
+            val rd_idx[5] <= rd + 8;
114
+            X[rd_idx] <= X[rd_idx] & X[rs2 + 8];
115
+        }
116
+        C.J(no_cont) {//(RV32)
117
+            encoding:b101 | imm[11:11]s | imm[4:4]s | imm[9:8]s | imm[10:10]s | imm[6:6]s | imm[7:7]s | imm[3:1]s | imm[5:5]s | b01;
118
+            args_disass: "0x%imm$05x";
119
+            PC<=PC+imm;
120
+        }
121
+        C.BEQZ(no_cont,cond) {//(RV32)
122
+            encoding:b110 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s |imm[2:1]s | imm[5:5]s | b01;
123
+            args_disass: "x(8+%rs1$d), 0x%imm$05x";
124
+            PC<=choose(X[rs1+8]==0, PC+imm, PC+2);
125
+        }
126
+        C.BNEZ(no_cont,cond) {//(RV32)
127
+            encoding:b111 | imm[8:8]s | imm[4:3]s | rs1[2:0] | imm[7:6]s | imm[2:1]s | imm[5:5]s | b01;
128
+            args_disass: "x(8+%rs1$d), 0x%imm$05x";
129
+            PC<=choose(X[rs1+8]!=0, PC+imm, PC+2);
130
+        }
131
+        C.SLLI {//(RV32)
132
+            encoding:b000 | b0 | rs1[4:0] | shamt[4:0] | b10;
133
+            args_disass: "x%rs1$d, %shamt$d";
134
+            if(rs1 == 0) raise(0, 2);
135
+            X[rs1] <= shll(X[rs1], shamt);
136
+        }
137
+        C.LWSP {//
138
+            encoding:b010 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
139
+            args_disass: "x%rd$d, sp, 0x%uimm$05x";
140
+            val offs[XLEN] <= X[2] + uimm;
141
+            X[rd] <= MEM[offs]{32};
142
+        }
143
+        // order matters as C.JR is a special case of C.MV
159 144
         C.MV {//(RV32)
160 145
             encoding:b100 | b0 | rd[4:0] | rs2[4:0] | b10;
161 146
             args_disass: "x%rd$d, x%rs2$d";
162 147
             X[rd] <= X[rs2];
163 148
         }
164
-		C.JR(no_cont) {//(RV32)
165
-			encoding:b100 | b0 | rs1[4:0] | b00000 | b10;
166
-			args_disass: "x%rs1$d";
167
-			PC <= X[rs1];
168
-		}
149
+        C.JR(no_cont) {//(RV32)
150
+            encoding:b100 | b0 | rs1[4:0] | b00000 | b10;
151
+            args_disass: "x%rs1$d";
152
+            PC <= X[rs1];
153
+        }
169 154
         // order matters as C.EBREAK is a special case of C.JALR which is a special case of C.ADD
170 155
         C.ADD {//(RV32)
171 156
             encoding:b100 | b1 | rd[4:0] | rs2[4:0] | b10;
172 157
             args_disass: "x%rd$d, x%rs2$d";
173
-        	X[rd] <= X[rd] + X[rs2];
174
-        }
175
-		C.JALR(no_cont) {//(RV32)
176
-			encoding:b100 | b1 | rs1[4:0] | b00000 | b10;
177
-			args_disass: "x%rs1$d";
178
-			val r_idx[5] <= 1;
179
-			X[r_idx] <= PC+2;
180
-			PC<=X[rs1];
181
-		}
182
-		C.EBREAK(no_cont) {//(RV32)
183
-			encoding:b100 | b1 | b00000 | b00000 | b10;
184
-			raise(0, 3);
185
-		}
186
-		C.SWSP {//
187
-			encoding:b110 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
158
+            X[rd] <= X[rd] + X[rs2];
159
+        }
160
+        C.JALR(no_cont) {//(RV32)
161
+            encoding:b100 | b1 | rs1[4:0] | b00000 | b10;
162
+            args_disass: "x%rs1$d";
163
+            X[1] <= PC+2;
164
+            PC<=X[rs1];
165
+        }
166
+        C.EBREAK(no_cont) {//(RV32)
167
+            encoding:b100 | b1 | b00000 | b00000 | b10;
168
+            raise(0, 3);
169
+        }
170
+        C.SWSP {//
171
+            encoding:b110 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
188 172
             args_disass: "x2+0x%uimm$05x, x%rs2$d";
189
-            val x2_idx[5] <= 2;
190
-            val offs[XLEN] <= X[x2_idx] + uimm;
173
+            val offs[XLEN] <= X[2] + uimm;
191 174
             MEM[offs]{32} <= X[rs2];
192
-		}
193
-		DII {
194
-			encoding:b000 | b0 | b00000 | b00000 | b00;
195
-			raise(0, 2);
196
-		}
197
-	}
175
+        }
176
+        DII {
177
+            encoding:b000 | b0 | b00000 | b00000 | b00;
178
+            raise(0, 2);
179
+        }
180
+    }
198 181
 }
199 182
 
200 183
 InsructionSet RV32FC extends RV32IC{
201
-	constants {
202
-		XLEN, FLEN
203
-	}
204
-	address_spaces { 
205
-		MEM[8]
206
-	}
207
-	registers { 
208
-		[31:0]   X[XLEN],
209
-		[31:0]   F[FLEN]
210
-	}
211
-	instructions{
212
-		C.FLW {
213
-			encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
214
-			args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))";
215
-			val rs1_idx[5] <= rs1+8;
216
-			val rd_idx[5] <= rd+8;
217
-			val offs[XLEN] <= X[rs1_idx]+uimm;
218
-			val res[32] <= MEM[offs]{32};
219
-			if(FLEN==32)
220
-				F[rd_idx] <= res;
221
-			else { // NaN boxing
222
-				val upper[FLEN] <= -1;
223
-				F[rd] <= (upper<<32) | zext(res, FLEN);
224
-			}
225
-		} 
226
-		C.FSW {
227
-			encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
228
-			args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))";
229
-			val rs1_idx[5] <= rs1+8;
230
-			val rs2_idx[5] <= rs2+8;
231
-			val offs[XLEN] <= X[rs1_idx]+uimm;
232
-			MEM[offs]{32}<=F[rs2_idx]{32};
233
-		}
234
-		C.FLWSP {
235
-			encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
236
-			args_disass:"f%rd$d, %uimm%(x2)";
237
-			val x2_idx[5] <= 2;
238
-			val offs[XLEN] <= X[x2_idx]+uimm;
239
-			val res[32] <= MEM[offs]{32};
240
-			if(FLEN==32)
241
-				F[rd] <= res;
242
-			else { // NaN boxing
243
-				val upper[FLEN] <= -1;
244
-				F[rd] <= (upper<<32) | zext(res, FLEN);
245
-			}
246
-		}
247
-		C.FSWSP {
248
-			encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
249
-			args_disass:"f%rs2$d, %uimm%(x2), ";
250
-			val x2_idx[5] <= 2;
251
-			val offs[XLEN] <= X[x2_idx]+uimm;
252
-			MEM[offs]{32}<=F[rs2]{32};
253
-		}		
254
-	}
184
+    constants {
185
+        XLEN, FLEN
186
+    }
187
+    address_spaces { 
188
+        MEM[8]
189
+    }
190
+    registers { 
191
+        [31:0]   X[XLEN],
192
+        [31:0]   F[FLEN]
193
+    }
194
+    instructions{
195
+        C.FLW {
196
+            encoding: b011 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rd[2:0] | b00;
197
+            args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))";
198
+            val offs[XLEN] <= X[rs1+8]+uimm;
199
+            val res[32] <= MEM[offs]{32};
200
+            if(FLEN==32)
201
+                F[rd+8] <= res;
202
+            else { // NaN boxing
203
+                val upper[FLEN] <= -1;
204
+                F[rd+8] <= (upper<<32) | zext(res, FLEN);
205
+            }
206
+        } 
207
+        C.FSW {
208
+            encoding: b111 | uimm[5:3] | rs1[2:0] | uimm[2:2] | uimm[6:6] | rs2[2:0] | b00;
209
+            args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))";
210
+            val offs[XLEN] <= X[rs1+8]+uimm;
211
+            MEM[offs]{32}<=F[rs2+8]{32};
212
+        }
213
+        C.FLWSP {
214
+            encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:2] | uimm[7:6] | b10;
215
+            args_disass:"f%rd$d, %uimm%(x2)";
216
+            val offs[XLEN] <= X[2]+uimm;
217
+            val res[32] <= MEM[offs]{32};
218
+            if(FLEN==32)
219
+                F[rd] <= res;
220
+            else { // NaN boxing
221
+                val upper[FLEN] <= -1;
222
+                F[rd] <= (upper<<32) | zext(res, FLEN);
223
+            }
224
+        }
225
+        C.FSWSP {
226
+            encoding:b111 | uimm[5:2] | uimm[7:6] | rs2[4:0] | b10;
227
+            args_disass:"f%rs2$d, %uimm%(x2), ";
228
+            val offs[XLEN] <= X[2]+uimm;
229
+            MEM[offs]{32}<=F[rs2]{32};
230
+        }        
231
+    }
255 232
 }
256 233
 
257 234
 InsructionSet RV32DC extends RV32IC{
258
-	constants {
259
-		XLEN, FLEN
260
-	}
261
-	address_spaces { 
262
-		MEM[8]
263
-	}
264
-	registers { 
265
-		[31:0]   X[XLEN],
266
-		[31:0]   F[FLEN]
267
-	}
268
-	instructions{
269
-		C.FLD { //(RV32/64)
270
-			encoding: b001 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
271
-			args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))";
272
-			val rs1_idx[5] <= rs1+8;
273
-			val rd_idx[5] <= rd+8;
274
-			val offs[XLEN] <= X[rs1_idx]+uimm;
275
-			val res[64] <= MEM[offs]{64};
276
-			if(FLEN==64)
277
-				F[rd_idx] <= res;
278
-			else { // NaN boxing
279
-				val upper[FLEN] <= -1;
280
-				F[rd_idx] <= (upper<<64) | res;
281
-			}
282
-	 	}
283
-		C.FSD { //(RV32/64)
284
-			encoding: b101 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
285
-			args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))";
286
-			val rs1_idx[5] <= rs1+8;
287
-			val rs2_idx[5] <= rs2+8;
288
-			val offs[XLEN] <= X[rs1_idx]+uimm;
289
-			MEM[offs]{64}<=F[rs2_idx]{64};
290
-		} 
291
-		C.FLDSP {//(RV32/64)
292
-			encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
293
-			args_disass:"f%rd$d, %uimm%(x2)";
294
-			val x2_idx[5] <= 2;
295
-			val offs[XLEN] <= X[x2_idx]+uimm;
296
-			val res[64] <= MEM[offs]{64};
297
-			if(FLEN==64)
298
-				F[rd] <= res;
299
-			else { // NaN boxing
300
-				val upper[FLEN] <= -1;
301
-				F[rd] <= (upper<<64) | zext(res, FLEN);
302
-			}
303
-		}
304
-		C.FSDSP {//(RV32/64)
305
-			encoding:b101 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
306
-			args_disass:"f%rs2$d, %uimm%(x2), ";
307
-			val x2_idx[5] <= 2;
308
-			val offs[XLEN] <= X[x2_idx]+uimm;
309
-			MEM[offs]{64}<=F[rs2]{64};
310
-		}
311
-	}
235
+    constants {
236
+        XLEN, FLEN
237
+    }
238
+    address_spaces { 
239
+        MEM[8]
240
+    }
241
+    registers { 
242
+        [31:0]   X[XLEN],
243
+        [31:0]   F[FLEN]
244
+    }
245
+    instructions{
246
+        C.FLD { //(RV32/64)
247
+            encoding: b001 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
248
+            args_disass:"f(8+%rd$d), %uimm%(x(8+%rs1$d))";
249
+            val offs[XLEN] <= X[rs1+8]+uimm;
250
+            val res[64] <= MEM[offs]{64};
251
+            if(FLEN==64)
252
+                F[rd+8] <= res;
253
+            else { // NaN boxing
254
+                val upper[FLEN] <= -1;
255
+                F[rd+8] <= (upper<<64) | res;
256
+            }
257
+         }
258
+        C.FSD { //(RV32/64)
259
+            encoding: b101 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
260
+            args_disass:"f(8+%rs2$d), %uimm%(x(8+%rs1$d))";
261
+            val offs[XLEN] <= X[rs1+8]+uimm;
262
+            MEM[offs]{64}<=F[rs2+8]{64};
263
+        } 
264
+        C.FLDSP {//(RV32/64)
265
+            encoding:b001 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
266
+            args_disass:"f%rd$d, %uimm%(x2)";
267
+            val offs[XLEN] <= X[2]+uimm;
268
+            val res[64] <= MEM[offs]{64};
269
+            if(FLEN==64)
270
+                F[rd] <= res;
271
+            else { // NaN boxing
272
+                val upper[FLEN] <= -1;
273
+                F[rd] <= (upper<<64) | zext(res, FLEN);
274
+            }
275
+        }
276
+        C.FSDSP {//(RV32/64)
277
+            encoding:b101 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
278
+            args_disass:"f%rs2$d, %uimm%(x2), ";
279
+            val offs[XLEN] <= X[2]+uimm;
280
+            MEM[offs]{64}<=F[rs2]{64};
281
+        }
282
+    }
312 283
 }
313 284
 
314 285
 InsructionSet RV64IC extends RV32IC {
315
-	constants {
316
-		XLEN
317
-	}
318
-	address_spaces { 
319
-		MEM[8]
320
-	}
321
-	registers { 
322
-		[31:0]   X[XLEN],
323
-				PC[XLEN](is_pc)
324
-	}
325
-	instructions{
326
-		C.LD {//(RV64/128) 
327
-			encoding:b011 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
328
-		}
329
-		C.SD { //(RV64/128) 
330
-			encoding:b111 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
331
-		}
332
-		C.SUBW {//(RV64/128, RV32 res)
333
-			encoding:b100 | b1 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
334
-			args_disass: "x%rd$d, sp, 0x%imm$05x";
335
-		}
336
-		C.ADDW {//(RV64/128 RV32 res)
337
-			encoding:b100 | b1 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
338
-			args_disass: "x%rd$d, sp, 0x%imm$05x";
339
-		}
286
+    constants {
287
+        XLEN
288
+    }
289
+    address_spaces { 
290
+        MEM[8]
291
+    }
292
+    registers { 
293
+        [31:0]   X[XLEN],
294
+                PC[XLEN](is_pc)
295
+    }
296
+    instructions{
297
+        C.LD {//(RV64/128) 
298
+            encoding:b011 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
299
+        }
300
+        C.SD { //(RV64/128) 
301
+            encoding:b111 | uimm[5:3] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
302
+        }
303
+        C.SUBW {//(RV64/128, RV32 res)
304
+            encoding:b100 | b1 | b11 | rd[2:0] | b00 | rs2[2:0] | b01;
305
+            args_disass: "x%rd$d, sp, 0x%imm$05x";
306
+        }
307
+        C.ADDW {//(RV64/128 RV32 res)
308
+            encoding:b100 | b1 | b11 | rd[2:0] | b01 | rs2[2:0] | b01;
309
+            args_disass: "x%rd$d, sp, 0x%imm$05x";
310
+        }
340 311
         C.ADDIW {//(RV64/128)
341 312
             encoding:b001 | imm[5:5] | rs1[4:0] | imm[4:0] | b01;
342 313
         }
343
-       	C.SRLI64 {//(RV32/64/128)
344
-          	encoding:b100 | b0 | b00 | rs1[2:0] | b00000 | b01;
345
-      	}
346
-		C.SRAI64 {//(RV32/64/128)
347
-			encoding:b100 | b0 | b01 | rs1[2:0] | b00000 | b01;
348
-		}
349
-		C.SLLI64 {//(RV128 RV32/64)
350
-			encoding:b000 | b0 | rs1[4:0] | b00000 | b10;
351
-		}
352
-		C.LDSP {//(RV64/128
353
-			encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
354
-			args_disass: "x%rd$d, sp, 0x%imm$05x";
355
-		}
356
-		C.SDSP {//(RV64/128)
357
-			encoding:b111 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
358
-		}
359
-	}
314
+           C.SRLI64 {//(RV32/64/128)
315
+              encoding:b100 | b0 | b00 | rs1[2:0] | b00000 | b01;
316
+          }
317
+        C.SRAI64 {//(RV32/64/128)
318
+            encoding:b100 | b0 | b01 | rs1[2:0] | b00000 | b01;
319
+        }
320
+        C.SLLI64 {//(RV128 RV32/64)
321
+            encoding:b000 | b0 | rs1[4:0] | b00000 | b10;
322
+        }
323
+        C.LDSP {//(RV64/128
324
+            encoding:b011 | uimm[5:5] | rd[4:0] | uimm[4:3] | uimm[8:6] | b10;
325
+            args_disass: "x%rd$d, sp, 0x%imm$05x";
326
+        }
327
+        C.SDSP {//(RV64/128)
328
+            encoding:b111 | uimm[5:3] | uimm[8:6] | rs2[4:0] | b10;
329
+        }
330
+    }
360 331
 }
361 332
 
362 333
 InsructionSet RV128IC extends RV64IC {
363
-	constants {
364
-		XLEN
365
-	}
366
-	address_spaces { 
367
-		MEM[8]
368
-	}
369
-	registers { 
370
-		[31:0]   X[XLEN],
371
-				PC[XLEN](is_pc)
372
-	}
373
-	instructions{
374
-		C.LQ { //(RV128)
375
-			 encoding:b001 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
376
-		}
377
-		C.SQ { //(RV128) 
378
-			encoding:b101 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
379
-		}
380
-		C.SQSP {//(RV128)
381
-			encoding:b101 | uimm[5:4] | uimm[9:6] | rs2[4:0] | b10;
382
-		}
383
-	}
334
+    constants {
335
+        XLEN
336
+    }
337
+    address_spaces { 
338
+        MEM[8]
339
+    }
340
+    registers { 
341
+        [31:0]   X[XLEN],
342
+                PC[XLEN](is_pc)
343
+    }
344
+    instructions{
345
+        C.LQ { //(RV128)
346
+             encoding:b001 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rd[2:0] | b00;
347
+        }
348
+        C.SQ { //(RV128) 
349
+            encoding:b101 | uimm[5:4] | uimm[8:8] | rs1[2:0] | uimm[7:6] | rs2[2:0] | b00;
350
+        }
351
+        C.SQSP {//(RV128)
352
+            encoding:b101 | uimm[5:4] | uimm[9:6] | rs2[4:0] | b10;
353
+        }
354
+    }
384 355
 }

+ 294
- 294
riscv/gen_input/RV32D.core_desc View File

@@ -1,298 +1,298 @@
1 1
 import "RV32IBase.core_desc"
2 2
 
3 3
 InsructionSet RV32D extends RV32IBase{
4
-	constants {
5
-		FLEN, FFLAG_MASK := 0x1f
6
-	} 
7
-	registers {
8
-		[31:0]    F[FLEN],  FCSR[32]
9
-    }	
10
-	instructions{
11
-		FLD {
12
-			encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000111;
13
-			args_disass:"f%rd$d, %imm%(x%rs1$d)";
14
-			val offs[XLEN] <= X[rs1]+imm;
15
-			val res[64] <= MEM[offs]{64};
16
-			if(FLEN==64)
17
-				F[rd] <= res;
18
-			else { // NaN boxing
19
-				val upper[FLEN] <= -1;
20
-				F[rd] <= (upper<<64) | res;
21
-			}
22
-		}
23
-		FSD {
24
-			encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100111;
25
-			args_disass:"f%rs2$d, %imm%(x%rs1$d)";
26
-			val offs[XLEN] <= X[rs1]+imm;
27
-			MEM[offs]{64}<=F[rs2]{64};
28
-		}
29
-		FMADD.D {
30
-			encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
31
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
32
-			//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
33
-			val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(0, 64), choose(rm<7, rm{8}, FCSR{8}));
34
-			if(FLEN==64)
35
-				F[rd] <= res;
36
-			else { // NaN boxing
37
-				val upper[FLEN] <= -1;
38
-				F[rd] <= (upper<<64) | res;
39
-			}
40
-			val flags[32] <= fdispatch_fget_flags();
41
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
42
-		}
43
-		FMSUB.D {
44
-			encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
45
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
46
-			//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
47
-			val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
48
-			if(FLEN==64)
49
-				F[rd] <= res;
50
-			else { // NaN boxing
51
-				val upper[FLEN] <= -1;
52
-				F[rd] <= (upper<<64) | res;
53
-			}
54
-			val flags[32] <= fdispatch_fget_flags();
55
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};	
56
-		}
57
-		FNMADD.D {
58
-			encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
59
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
60
-			//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
61
-			val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
62
-			if(FLEN==64)
63
-				F[rd] <= res;
64
-			else { // NaN boxing
65
-				val upper[FLEN] <= -1;
66
-				F[rd] <= (upper<<64) | res;
67
-			}
68
-			val flags[32] <= fdispatch_fget_flags();
69
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
70
-		}
71
-		FNMSUB.D {
72
-			encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
73
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
74
-			//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
75
-			val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
76
-			if(FLEN==64)
77
-				F[rd] <= res;
78
-			else { // NaN boxing
79
-				val upper[FLEN] <= -1;
80
-				F[rd] <= (upper<<64) | res;
81
-			}
82
-			val flags[32] <= fdispatch_fget_flags();
83
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
84
-		}
85
-		FADD.D {
86
-			encoding: b0000001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
87
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
88
-			// F[rd]f <= F[rs1]f + F[rs2]f;
89
-			val res[64] <= fdispatch_fadd_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
90
-			if(FLEN==64)
91
-				F[rd] <= res;
92
-			else { // NaN boxing
93
-				val upper[FLEN] <= -1;
94
-				F[rd] <= (upper<<64) | res;
95
-			}
96
-			val flags[32] <= fdispatch_fget_flags();
97
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
98
-		}
99
-		FSUB.D {
100
-			encoding: b0000101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
101
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
102
-			// F[rd]f <= F[rs1]f - F[rs2]f;
103
-			val res[64] <= fdispatch_fsub_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
104
-			if(FLEN==64)
105
-				F[rd] <= res;
106
-			else { // NaN boxing
107
-				val upper[FLEN] <= -1;
108
-				F[rd] <= (upper<<64) | res;
109
-			}
110
-			val flags[32] <= fdispatch_fget_flags();
111
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
112
-		}
113
-		FMUL.D {
114
-			encoding: b0001001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
115
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
116
-			// F[rd]f <= F[rs1]f * F[rs2]f;
117
-			val res[64] <= fdispatch_fmul_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
118
-			if(FLEN==64)
119
-				F[rd] <= res;
120
-			else { // NaN boxing
121
-				val upper[FLEN] <= -1;
122
-				F[rd] <= (upper<<64) | res;
123
-			}
124
-			val flags[32] <= fdispatch_fget_flags();
125
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
126
-		}
127
-		FDIV.D {
128
-			encoding: b0001101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
129
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
130
-			// F[rd]f <= F[rs1]f / F[rs2]f;
131
-			val res[64] <= fdispatch_fdiv_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
132
-			if(FLEN==64)
133
-				F[rd] <= res;
134
-			else { // NaN boxing
135
-				val upper[FLEN] <= -1;
136
-				F[rd] <= (upper<<64) | res;
137
-			}
138
-			val flags[32] <= fdispatch_fget_flags();
139
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
140
-		}
141
-		FSQRT.D {
142
-			encoding: b0101101 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
143
-			args_disass:"x%rd$d, f%rs1$d";
144
-			//F[rd]f<=sqrt(F[rs1]f);
145
-			val res[64] <= fdispatch_fsqrt_d(F[rs1]{64}, choose(rm<7, rm{8}, FCSR{8}));
146
-			if(FLEN==64)
147
-				F[rd] <= res;
148
-			else { // NaN boxing
149
-				val upper[FLEN] <= -1;
150
-				F[rd] <= (upper<<64) | res;
151
-			}
152
-			val flags[32] <= fdispatch_fget_flags();
153
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
154
-		}
155
-		FSGNJ.D {
156
-			encoding: b0010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
157
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
158
-			val res[64] <= (F[rs1]{64} & 0x7fffffff) | (F[rs2]{64} & 0x80000000);
159
-			if(FLEN==64)
160
-				F[rd] <= res;
161
-			else { // NaN boxing
162
-				val upper[FLEN] <= -1;
163
-				F[rd] <= (upper<<64) | res;
164
-			}
165
-		}
166
-		FSGNJN.D {
167
-			encoding: b0010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
168
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
169
-			val res[64] <= (F[rs1]{64} & 0x7fffffff) | (~F[rs2]{64} & 0x80000000);
170
-			if(FLEN==64)
171
-				F[rd] <= res;
172
-			else { // NaN boxing
173
-				val upper[FLEN] <= -1;
174
-				F[rd] <= (upper<<64) | res;
175
-			}
176
-		}
177
-		FSGNJX.D {
178
-			encoding: b0010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
179
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
180
-			val res[64] <= F[rs1]{64} ^ (F[rs2]{64} & 0x80000000);
181
-			if(FLEN==64)
182
-				F[rd] <= res;
183
-			else { // NaN boxing
184
-				val upper[FLEN] <= -1;
185
-				F[rd] <= (upper<<64) | res;
186
-			}
187
-		}
188
-		FMIN.D  {
189
-			encoding: b0010101 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
190
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
191
-			//F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
192
-			val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32));
193
-			if(FLEN==64)
194
-				F[rd] <= res;
195
-			else { // NaN boxing
196
-				val upper[FLEN] <= -1;
197
-				F[rd] <= (upper<<64) | res;
198
-			}
199
-			val flags[32] <= fdispatch_fget_flags();
200
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
201
-		}
202
-		FMAX.D {
203
-			encoding: b0010101 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
204
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
205
-			//F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
206
-			val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32));
207
-			if(FLEN==64)
208
-				F[rd] <= res;
209
-			else { // NaN boxing
210
-				val upper[FLEN] <= -1;
211
-				F[rd] <= (upper<<64) | res;
212
-			}
213
-			val flags[32] <= fdispatch_fget_flags();
214
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
215
-		}
216
-		FCVT.S.D {
217
-			encoding: b0100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
218
-			args_disass:"f%rd$d, f%rs1$d";
219
-			val res[32] <= fdispatch_fconv_d2f(F[rs1], rm{8});
220
-			// NaN boxing
221
-			val upper[FLEN] <= -1;
222
-			F[rd] <= upper<<32 | zext(res, FLEN);
223
-		}
224
-		FCVT.D.S {
225
-			encoding: b0100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
226
-			args_disass:"f%rd$d, f%rs1$d";
227
-			val res[64] <= fdispatch_fconv_f2d(F[rs1]{32}, rm{8});
228
-			if(FLEN==64){
229
-				F[rd] <= res;
230
-			} else {
231
-				val upper[FLEN] <= -1;
232
-				F[rd] <= (upper<<64) | res;
233
-			}
234
-		}
235
-		FEQ.D {
236
-			encoding: b1010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
237
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
238
-			X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32));
239
-			val flags[32] <= fdispatch_fget_flags();
240
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
241
-		}
242
-		FLT.D {
243
-			encoding: b1010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
244
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
245
-			X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(2, 32));
246
-			val flags[32] <= fdispatch_fget_flags();
247
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
248
-		}
249
-		FLE.D {
250
-			encoding: b1010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
251
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
252
-			X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32));
253
-			val flags[32] <= fdispatch_fget_flags();
254
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
255
-		}
256
-		FCLASS.D {
257
-			encoding: b1110001 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
258
-			args_disass:"x%rd$d, f%rs1$d";
259
-			X[rd]<=fdispatch_fclass_d(F[rs1]{64});
260
-		}
261
-		FCVT.W.D {
262
-			encoding: b1100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
263
-			args_disass:"x%rd$d, f%rs1$d";
264
-			X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(0, 32), rm{8}), XLEN);
265
-			val flags[32] <= fdispatch_fget_flags();
266
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
267
-		}
268
-		FCVT.WU.D {
269
-			encoding: b1100001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
270
-			args_disass:"x%rd$d, f%rs1$d";
271
-			X[rd]<= zext(fdispatch_fcvt_d(F[rs1]{64}, zext(1, 32), rm{8}), XLEN);
272
-			val flags[32] <= fdispatch_fget_flags();
273
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
274
-		}
275
-		FCVT.D.W {
276
-			encoding: b1101001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
277
-			args_disass:"f%rd$d, x%rs1$d";
278
-			val res[64] <= fdispatch_fcvt_d(sext(X[rs1],64), zext(2, 32), rm{8});
279
-			if(FLEN==64)
280
-				F[rd] <= res;
281
-			else { // NaN boxing
282
-				val upper[FLEN] <= -1;
283
-				F[rd] <= (upper<<64) | res;
284
-			}
285
-		}
286
-		FCVT.D.WU {
287
-			encoding: b1101001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
288
-			args_disass:"f%rd$d, x%rs1$d";
289
-			val res[64] <=fdispatch_fcvt_d(zext(X[rs1],64), zext(3,32), rm{8});
290
-			if(FLEN==64)
291
-				F[rd] <= res;
292
-			else { // NaN boxing
293
-				val upper[FLEN] <= -1;
294
-				F[rd] <= (upper<<64) | res;
295
-			}
296
-		}
297
-	}
4
+    constants {
5
+        FLEN, FFLAG_MASK := 0x1f
6
+    } 
7
+    registers {
8
+        [31:0]    F[FLEN],  FCSR[32]
9
+    }    
10
+    instructions{
11
+        FLD {
12
+            encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000111;
13
+            args_disass:"f%rd$d, %imm%(x%rs1$d)";
14
+            val offs[XLEN] <= X[rs1]+imm;
15
+            val res[64] <= MEM[offs]{64};
16
+            if(FLEN==64)
17
+                F[rd] <= res;
18
+            else { // NaN boxing
19
+                val upper[FLEN] <= -1;
20
+                F[rd] <= (upper<<64) | res;
21
+            }
22
+        }
23
+        FSD {
24
+            encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100111;
25
+            args_disass:"f%rs2$d, %imm%(x%rs1$d)";
26
+            val offs[XLEN] <= X[rs1]+imm;
27
+            MEM[offs]{64}<=F[rs2]{64};
28
+        }
29
+        FMADD.D {
30
+            encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
31
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
32
+            //F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
33
+            val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(0, 64), choose(rm<7, rm{8}, FCSR{8}));
34
+            if(FLEN==64)
35
+                F[rd] <= res;
36
+            else { // NaN boxing
37
+                val upper[FLEN] <= -1;
38
+                F[rd] <= (upper<<64) | res;
39
+            }
40
+            val flags[32] <= fdispatch_fget_flags();
41
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
42
+        }
43
+        FMSUB.D {
44
+            encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
45
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
46
+            //F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
47
+            val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
48
+            if(FLEN==64)
49
+                F[rd] <= res;
50
+            else { // NaN boxing
51
+                val upper[FLEN] <= -1;
52
+                F[rd] <= (upper<<64) | res;
53
+            }
54
+            val flags[32] <= fdispatch_fget_flags();
55
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};    
56
+        }
57
+        FNMADD.D {
58
+            encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
59
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
60
+            //F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
61
+            val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
62
+            if(FLEN==64)
63
+                F[rd] <= res;
64
+            else { // NaN boxing
65
+                val upper[FLEN] <= -1;
66
+                F[rd] <= (upper<<64) | res;
67
+            }
68
+            val flags[32] <= fdispatch_fget_flags();
69
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
70
+        }
71
+        FNMSUB.D {
72
+            encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
73
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
74
+            //F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
75
+            val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
76
+            if(FLEN==64)
77
+                F[rd] <= res;
78
+            else { // NaN boxing
79
+                val upper[FLEN] <= -1;
80
+                F[rd] <= (upper<<64) | res;
81
+            }
82
+            val flags[32] <= fdispatch_fget_flags();
83
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
84
+        }
85
+        FADD.D {
86
+            encoding: b0000001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
87
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
88
+            // F[rd]f <= F[rs1]f + F[rs2]f;
89
+            val res[64] <= fdispatch_fadd_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
90
+            if(FLEN==64)
91
+                F[rd] <= res;
92
+            else { // NaN boxing
93
+                val upper[FLEN] <= -1;
94
+                F[rd] <= (upper<<64) | res;
95
+            }
96
+            val flags[32] <= fdispatch_fget_flags();
97
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
98
+        }
99
+        FSUB.D {
100
+            encoding: b0000101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
101
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
102
+            // F[rd]f <= F[rs1]f - F[rs2]f;
103
+            val res[64] <= fdispatch_fsub_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
104
+            if(FLEN==64)
105
+                F[rd] <= res;
106
+            else { // NaN boxing
107
+                val upper[FLEN] <= -1;
108
+                F[rd] <= (upper<<64) | res;
109
+            }
110
+            val flags[32] <= fdispatch_fget_flags();
111
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
112
+        }
113
+        FMUL.D {
114
+            encoding: b0001001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
115
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
116
+            // F[rd]f <= F[rs1]f * F[rs2]f;
117
+            val res[64] <= fdispatch_fmul_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
118
+            if(FLEN==64)
119
+                F[rd] <= res;
120
+            else { // NaN boxing
121
+                val upper[FLEN] <= -1;
122
+                F[rd] <= (upper<<64) | res;
123
+            }
124
+            val flags[32] <= fdispatch_fget_flags();
125
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
126
+        }
127
+        FDIV.D {
128
+            encoding: b0001101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
129
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
130
+            // F[rd]f <= F[rs1]f / F[rs2]f;
131
+            val res[64] <= fdispatch_fdiv_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8}));
132
+            if(FLEN==64)
133
+                F[rd] <= res;
134
+            else { // NaN boxing
135
+                val upper[FLEN] <= -1;
136
+                F[rd] <= (upper<<64) | res;
137
+            }
138
+            val flags[32] <= fdispatch_fget_flags();
139
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
140
+        }
141
+        FSQRT.D {
142
+            encoding: b0101101 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
143
+            args_disass:"x%rd$d, f%rs1$d";
144
+            //F[rd]f<=sqrt(F[rs1]f);
145
+            val res[64] <= fdispatch_fsqrt_d(F[rs1]{64}, choose(rm<7, rm{8}, FCSR{8}));
146
+            if(FLEN==64)
147
+                F[rd] <= res;
148
+            else { // NaN boxing
149
+                val upper[FLEN] <= -1;
150
+                F[rd] <= (upper<<64) | res;
151
+            }
152
+            val flags[32] <= fdispatch_fget_flags();
153
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
154
+        }
155
+        FSGNJ.D {
156
+            encoding: b0010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
157
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
158
+            val res[64] <= (F[rs1]{64} & 0x7fffffff) | (F[rs2]{64} & 0x80000000);
159
+            if(FLEN==64)
160
+                F[rd] <= res;
161
+            else { // NaN boxing
162
+                val upper[FLEN] <= -1;
163
+                F[rd] <= (upper<<64) | res;
164
+            }
165
+        }
166
+        FSGNJN.D {
167
+            encoding: b0010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
168
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
169
+            val res[64] <= (F[rs1]{64} & 0x7fffffff) | (~F[rs2]{64} & 0x80000000);
170
+            if(FLEN==64)
171
+                F[rd] <= res;
172
+            else { // NaN boxing
173
+                val upper[FLEN] <= -1;
174
+                F[rd] <= (upper<<64) | res;
175
+            }
176
+        }
177
+        FSGNJX.D {
178
+            encoding: b0010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
179
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
180
+            val res[64] <= F[rs1]{64} ^ (F[rs2]{64} & 0x80000000);
181
+            if(FLEN==64)
182
+                F[rd] <= res;
183
+            else { // NaN boxing
184
+                val upper[FLEN] <= -1;
185
+                F[rd] <= (upper<<64) | res;
186
+            }
187
+        }
188
+        FMIN.D  {
189
+            encoding: b0010101 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
190
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
191
+            //F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
192
+            val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32));
193
+            if(FLEN==64)
194
+                F[rd] <= res;
195
+            else { // NaN boxing
196
+                val upper[FLEN] <= -1;
197
+                F[rd] <= (upper<<64) | res;
198
+            }
199
+            val flags[32] <= fdispatch_fget_flags();
200
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
201
+        }
202
+        FMAX.D {
203
+            encoding: b0010101 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
204
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
205
+            //F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
206
+            val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32));
207
+            if(FLEN==64)
208
+                F[rd] <= res;
209
+            else { // NaN boxing
210
+                val upper[FLEN] <= -1;
211
+                F[rd] <= (upper<<64) | res;
212
+            }
213
+            val flags[32] <= fdispatch_fget_flags();
214
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
215
+        }
216
+        FCVT.S.D {
217
+            encoding: b0100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
218
+            args_disass:"f%rd$d, f%rs1$d";
219
+            val res[32] <= fdispatch_fconv_d2f(F[rs1], rm{8});
220
+            // NaN boxing
221
+            val upper[FLEN] <= -1;
222
+            F[rd] <= upper<<32 | zext(res, FLEN);
223
+        }
224
+        FCVT.D.S {
225
+            encoding: b0100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
226
+            args_disass:"f%rd$d, f%rs1$d";
227
+            val res[64] <= fdispatch_fconv_f2d(F[rs1]{32}, rm{8});
228
+            if(FLEN==64){
229
+                F[rd] <= res;
230
+            } else {
231
+                val upper[FLEN] <= -1;
232
+                F[rd] <= (upper<<64) | res;
233
+            }
234
+        }
235
+        FEQ.D {
236
+            encoding: b1010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
237
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
238
+            X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32));
239
+            val flags[32] <= fdispatch_fget_flags();
240
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
241
+        }
242
+        FLT.D {
243
+            encoding: b1010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
244
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
245
+            X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(2, 32));
246
+            val flags[32] <= fdispatch_fget_flags();
247
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
248
+        }
249
+        FLE.D {
250
+            encoding: b1010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
251
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
252
+            X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32));
253
+            val flags[32] <= fdispatch_fget_flags();
254
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
255
+        }
256
+        FCLASS.D {
257
+            encoding: b1110001 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
258
+            args_disass:"x%rd$d, f%rs1$d";
259
+            X[rd]<=fdispatch_fclass_d(F[rs1]{64});
260
+        }
261
+        FCVT.W.D {
262
+            encoding: b1100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
263
+            args_disass:"x%rd$d, f%rs1$d";
264
+            X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(0, 32), rm{8}), XLEN);
265
+            val flags[32] <= fdispatch_fget_flags();
266
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
267
+        }
268
+        FCVT.WU.D {
269
+            encoding: b1100001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
270
+            args_disass:"x%rd$d, f%rs1$d";
271
+            X[rd]<= zext(fdispatch_fcvt_d(F[rs1]{64}, zext(1, 32), rm{8}), XLEN);
272
+            val flags[32] <= fdispatch_fget_flags();
273
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
274
+        }
275
+        FCVT.D.W {
276
+            encoding: b1101001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
277
+            args_disass:"f%rd$d, x%rs1$d";
278
+            val res[64] <= fdispatch_fcvt_d(sext(X[rs1],64), zext(2, 32), rm{8});
279
+            if(FLEN==64)
280
+                F[rd] <= res;
281
+            else { // NaN boxing
282
+                val upper[FLEN] <= -1;
283
+                F[rd] <= (upper<<64) | res;
284
+            }
285
+        }
286
+        FCVT.D.WU {
287
+            encoding: b1101001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
288
+            args_disass:"f%rd$d, x%rs1$d";
289
+            val res[64] <=fdispatch_fcvt_d(zext(X[rs1],64), zext(3,32), rm{8});
290
+            if(FLEN==64)
291
+                F[rd] <= res;
292
+            else { // NaN boxing
293
+                val upper[FLEN] <= -1;
294
+                F[rd] <= (upper<<64) | res;
295
+            }
296
+        }
297
+    }
298 298
 }

+ 290
- 290
riscv/gen_input/RV32F.core_desc View File

@@ -1,294 +1,294 @@
1 1
 import "RV32IBase.core_desc"
2 2
 
3 3
 InsructionSet RV32F extends RV32IBase{
4
-	constants {
5
-		FLEN, FFLAG_MASK := 0x1f
6
-	} 
7
-	registers {
8
-		[31:0]    F[FLEN],  FCSR[32]
9
-    }	
10
-	instructions{
11
-		FLW {
12
-			encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
13
-			args_disass:"f%rd$d, %imm%(x%rs1$d)";
14
-			val offs[XLEN] <= X[rs1]+imm;
15
-			val res[32] <= MEM[offs]{32};
16
-			if(FLEN==32)
17
-				F[rd] <= res;
18
-			else { // NaN boxing
19
-				val upper[FLEN] <= -1;
20
-				F[rd] <= (upper<<32) | zext(res, FLEN);
21
-			}
22
-		}
23
-		FSW {
24
-			encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
25
-			args_disass:"f%rs2$d, %imm%(x%rs1$d)";
26
-			val offs[XLEN] <= X[rs1]+imm;
27
-			MEM[offs]{32}<=F[rs2]{32};
28
-		}
29
-		FMADD.S {
30
-			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
31
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
32
-			//F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
33
-			val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
34
-			if(FLEN==32)
35
-				F[rd] <= res;
36
-			else { // NaN boxing
37
-				val upper[FLEN] <= -1;
38
-				F[rd] <= (upper<<32) | zext(res, FLEN);
39
-			}
40
-			val flags[32] <= fdispatch_fget_flags();
41
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
42
-		}
43
-		FMSUB.S {
44
-			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
45
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
46
-			//F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
47
-			val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
48
-			if(FLEN==32)
49
-				F[rd] <= res;
50
-			else { // NaN boxing
51
-				val upper[FLEN] <= -1;
52
-				F[rd] <= (upper<<32) | zext(res, FLEN);
53
-			}
54
-			val flags[32] <= fdispatch_fget_flags();
55
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};	
56
-		}
57
-		FNMADD.S {
58
-			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
59
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
60
-			//F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
61
-			val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
62
-			if(FLEN==32)
63
-				F[rd] <= res;
64
-			else { // NaN boxing
65
-				val upper[FLEN] <= -1;
66
-				F[rd] <= (upper<<32) | zext(res, FLEN);
67
-			}
68
-			val flags[32] <= fdispatch_fget_flags();
69
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
70
-		}
71
-		FNMSUB.S {
72
-			encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
73
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
74
-			//F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
75
-			val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
76
-			if(FLEN==32)
77
-				F[rd] <= res;
78
-			else { // NaN boxing
79
-				val upper[FLEN] <= -1;
80
-				F[rd] <= (upper<<32) | zext(res, FLEN);
81
-			}
82
-			val flags[32] <= fdispatch_fget_flags();
83
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
84
-		}
85
-		FADD.S {
86
-			encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
87
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
88
-			// F[rd]f <= F[rs1]f + F[rs2]f;
89
-			val res[32] <= fdispatch_fadd_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
90
-			if(FLEN==32)
91
-				F[rd] <= res;
92
-			else { // NaN boxing
93
-				val upper[FLEN] <= -1;
94
-				F[rd] <= (upper<<32) | zext(res, FLEN);
95
-			}
96
-			val flags[32] <= fdispatch_fget_flags();
97
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
98
-		}
99
-		FSUB.S {
100
-			encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
101
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
102
-			// F[rd]f <= F[rs1]f - F[rs2]f;
103
-			val res[32] <= fdispatch_fsub_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
104
-			if(FLEN==32)
105
-				F[rd] <= res;
106
-			else { // NaN boxing
107
-				val upper[FLEN] <= -1;
108
-				F[rd] <= (upper<<32) | zext(res, FLEN);
109
-			}
110
-			val flags[32] <= fdispatch_fget_flags();
111
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
112
-		}
113
-		FMUL.S {
114
-			encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
115
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
116
-			// F[rd]f <= F[rs1]f * F[rs2]f;
117
-			val res[32] <= fdispatch_fmul_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
118
-			if(FLEN==32)
119
-				F[rd] <= res;
120
-			else { // NaN boxing
121
-				val upper[FLEN] <= -1;
122
-				F[rd] <= (upper<<32) | zext(res, FLEN);
123
-			}
124
-			val flags[32] <= fdispatch_fget_flags();
125
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
126
-		}
127
-		FDIV.S {
128
-			encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
129
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
130
-			// F[rd]f <= F[rs1]f / F[rs2]f;
131
-			val res[32] <= fdispatch_fdiv_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
132
-			if(FLEN==32)
133
-				F[rd] <= res;
134
-			else { // NaN boxing
135
-				val upper[FLEN] <= -1;
136
-				F[rd] <= (upper<<32) | zext(res, FLEN);
137
-			}
138
-			val flags[32] <= fdispatch_fget_flags();
139
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
140
-		}
141
-		FSQRT.S {
142
-			encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
143
-			args_disass:"f%rd$d, f%rs1$d";
144
-			//F[rd]f<=sqrt(F[rs1]f);
145
-			val res[32] <= fdispatch_fsqrt_s(F[rs1]{32}, choose(rm<7, rm{8}, FCSR{8}));
146
-			if(FLEN==32)
147
-				F[rd] <= res;
148
-			else { // NaN boxing
149
-				val upper[FLEN] <= -1;
150
-				F[rd] <= (upper<<32) | zext(res, FLEN);
151
-			}
152
-			val flags[32] <= fdispatch_fget_flags();
153
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
154
-		}
155
-		FSGNJ.S {
156
-			encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
157
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
158
-			val res[32] <= (F[rs1]{32} & 0x7fffffff) | (F[rs2]{32} & 0x80000000);
159
-			if(FLEN==32)
160
-				F[rd] <= res;
161
-			else { // NaN boxing
162
-				val upper[FLEN] <= -1;
163
-				F[rd] <= (upper<<32) | zext(res, FLEN);
164
-			}
165
-		}
166
-		FSGNJN.S {
167
-			encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
168
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
169
-			val res[32] <= (F[rs1]{32} & 0x7fffffff) | (~F[rs2]{32} & 0x80000000);
170
-			if(FLEN==32)
171
-				F[rd] <= res;
172
-			else { // NaN boxing
173
-				val upper[FLEN] <= -1;
174
-				F[rd] <= (upper<<32) | zext(res, FLEN);
175
-			}
176
-		}
177
-		FSGNJX.S {
178
-			encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
179
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
180
-			val res[32] <= F[rs1]{32} ^ (F[rs2]{32} & 0x80000000);
181
-			if(FLEN==32)
182
-				F[rd] <= res;
183
-			else { // NaN boxing
184
-				val upper[FLEN] <= -1;
185
-				F[rd] <= (upper<<32) | zext(res, FLEN);
186
-			}
187
-		}
188
-		FMIN.S  {
189
-			encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
190
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
191
-			//F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
192
-			val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
193
-			if(FLEN==32)
194
-				F[rd] <= res;
195
-			else { // NaN boxing
196
-				val upper[FLEN] <= -1;
197
-				F[rd] <= (upper<<32) | zext(res, FLEN);
198
-			}
199
-			val flags[32] <= fdispatch_fget_flags();
200
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
201
-		}
202
-		FMAX.S {
203
-			encoding: b0010100 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
204
-			args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
205
-			//F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
206
-			val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
207
-			if(FLEN==32)
208
-				F[rd] <= res;
209
-			else { // NaN boxing
210
-				val upper[FLEN] <= -1;
211
-				F[rd] <= (upper<<32) | zext(res, FLEN);
212
-			}
213
-			val flags[32] <= fdispatch_fget_flags();
214
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
215
-		}
216
-		FCVT.W.S {
217
-			encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
218
-			args_disass:"x%rd$d, f%rs1$d";
219
-			X[rd]<= sext(fdispatch_fcvt_s(F[rs1]{32}, zext(0, 32), rm{8}), XLEN);
220
-			val flags[32] <= fdispatch_fget_flags();
221
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
222
-		}
223
-		FCVT.WU.S {
224
-			encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
225
-			args_disass:"x%rd$d, f%rs1$d";
226
-			X[rd]<= zext(fdispatch_fcvt_s(F[rs1]{32}, zext(1, 32), rm{8}), XLEN);
227
-			val flags[32] <= fdispatch_fget_flags();
228
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
229
-		}
230
-		FEQ.S {
231
-			encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
232
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
233
-			X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
234
-			val flags[32] <= fdispatch_fget_flags();
235
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
236
-		}
237
-		FLT.S {
238
-			encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
239
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
240
-			X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32));
241
-			val flags[32] <= fdispatch_fget_flags();
242
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
243
-		}
244
-		FLE.S {
245
-			encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
246
-			args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
247
-			X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
248
-			val flags[32] <= fdispatch_fget_flags();
249
-			FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
250
-		}
251
-		FCLASS.S {
252
-			encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
253
-			args_disass:"x%rd$d, f%rs1$d";
254
-			X[rd]<=fdispatch_fclass_s(F[rs1]{32});
255
-		}
256
-		FCVT.S.W {
257
-			encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
258
-			args_disass:"f%rd$d, x%rs1$d";
259
-			val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
260
-			if(FLEN==32)
261
-				F[rd] <= res;
262
-			else { // NaN boxing
263
-				val upper[FLEN] <= -1;
264
-				F[rd] <= (upper<<32) | zext(res, FLEN);
265
-			}
266
-		}
267
-		FCVT.S.WU {
268
-			encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
269
-			args_disass:"f%rd$d, x%rs1$d";
270
-			val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
271
-			if(FLEN==32)
272
-				F[rd] <= res;
273
-			else { // NaN boxing
274
-				val upper[FLEN] <= -1;
275
-				F[rd] <= (upper<<32) | zext(res, FLEN);
276
-			}
277
-		}
278
-		FMV.X.W {
279
-			encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
280
-			args_disass:"x%rd$d, f%rs1$d";
281
-			X[rd]<=sext(F[rs1]{32});
282
-		}
283
-		FMV.W.X {
284
-			encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
285
-			args_disass:"f%rd$d, x%rs1$d";
286
-			if(FLEN==32)
287
-				F[rd] <= X[rs1];
288
-			else { // NaN boxing
289
-				val upper[FLEN] <= -1;
290
-				F[rd] <= (upper<<32) | zext(X[rs1], FLEN);
291
-			}
292
-		}
293
-	}
4
+    constants {
5
+        FLEN, FFLAG_MASK := 0x1f
6
+    } 
7
+    registers {
8
+        [31:0]    F[FLEN],  FCSR[32]
9
+    }    
10
+    instructions{
11
+        FLW {
12
+            encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111;
13
+            args_disass:"f%rd$d, %imm%(x%rs1$d)";
14
+            val offs[XLEN] <= X[rs1]+imm;
15
+            val res[32] <= MEM[offs]{32};
16
+            if(FLEN==32)
17
+                F[rd] <= res;
18
+            else { // NaN boxing
19
+                val upper[FLEN] <= -1;
20
+                F[rd] <= (upper<<32) | zext(res, FLEN);
21
+            }
22
+        }
23
+        FSW {
24
+            encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111;
25
+            args_disass:"f%rs2$d, %imm%(x%rs1$d)";
26
+            val offs[XLEN] <= X[rs1]+imm;
27
+            MEM[offs]{32}<=F[rs2]{32};
28
+        }
29
+        FMADD.S {
30
+            encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011;
31
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
32
+            //F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f;
33
+            val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(0, 32), choose(rm<7, rm{8}, FCSR{8}));
34
+            if(FLEN==32)
35
+                F[rd] <= res;
36
+            else { // NaN boxing
37
+                val upper[FLEN] <= -1;
38
+                F[rd] <= (upper<<32) | zext(res, FLEN);
39
+            }
40
+            val flags[32] <= fdispatch_fget_flags();
41
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
42
+        }
43
+        FMSUB.S {
44
+            encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111;
45
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
46
+            //F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f;
47
+            val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8}));
48
+            if(FLEN==32)
49
+                F[rd] <= res;
50
+            else { // NaN boxing
51
+                val upper[FLEN] <= -1;
52
+                F[rd] <= (upper<<32) | zext(res, FLEN);
53
+            }
54
+            val flags[32] <= fdispatch_fget_flags();
55
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};    
56
+        }
57
+        FNMADD.S {
58
+            encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111;
59
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
60
+            //F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f;
61
+            val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8}));
62
+            if(FLEN==32)
63
+                F[rd] <= res;
64
+            else { // NaN boxing
65
+                val upper[FLEN] <= -1;
66
+                F[rd] <= (upper<<32) | zext(res, FLEN);
67
+            }
68
+            val flags[32] <= fdispatch_fget_flags();
69
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
70
+        }
71
+        FNMSUB.S {
72
+            encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011;
73
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d";
74
+            //F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f;
75
+            val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8}));
76
+            if(FLEN==32)
77
+                F[rd] <= res;
78
+            else { // NaN boxing
79
+                val upper[FLEN] <= -1;
80
+                F[rd] <= (upper<<32) | zext(res, FLEN);
81
+            }
82
+            val flags[32] <= fdispatch_fget_flags();
83
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
84
+        }
85
+        FADD.S {
86
+            encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
87
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
88
+            // F[rd]f <= F[rs1]f + F[rs2]f;
89
+            val res[32] <= fdispatch_fadd_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
90
+            if(FLEN==32)
91
+                F[rd] <= res;
92
+            else { // NaN boxing
93
+                val upper[FLEN] <= -1;
94
+                F[rd] <= (upper<<32) | zext(res, FLEN);
95
+            }
96
+            val flags[32] <= fdispatch_fget_flags();
97
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
98
+        }
99
+        FSUB.S {
100
+            encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
101
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
102
+            // F[rd]f <= F[rs1]f - F[rs2]f;
103
+            val res[32] <= fdispatch_fsub_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
104
+            if(FLEN==32)
105
+                F[rd] <= res;
106
+            else { // NaN boxing
107
+                val upper[FLEN] <= -1;
108
+                F[rd] <= (upper<<32) | zext(res, FLEN);
109
+            }
110
+            val flags[32] <= fdispatch_fget_flags();
111
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
112
+        }
113
+        FMUL.S {
114
+            encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
115
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
116
+            // F[rd]f <= F[rs1]f * F[rs2]f;
117
+            val res[32] <= fdispatch_fmul_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
118
+            if(FLEN==32)
119
+                F[rd] <= res;
120
+            else { // NaN boxing
121
+                val upper[FLEN] <= -1;
122
+                F[rd] <= (upper<<32) | zext(res, FLEN);
123
+            }
124
+            val flags[32] <= fdispatch_fget_flags();
125
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
126
+        }
127
+        FDIV.S {
128
+            encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
129
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
130
+            // F[rd]f <= F[rs1]f / F[rs2]f;
131
+            val res[32] <= fdispatch_fdiv_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8}));
132
+            if(FLEN==32)
133
+                F[rd] <= res;
134
+            else { // NaN boxing
135
+                val upper[FLEN] <= -1;
136
+                F[rd] <= (upper<<32) | zext(res, FLEN);
137
+            }
138
+            val flags[32] <= fdispatch_fget_flags();
139
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
140
+        }
141
+        FSQRT.S {
142
+            encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
143
+            args_disass:"f%rd$d, f%rs1$d";
144
+            //F[rd]f<=sqrt(F[rs1]f);
145
+            val res[32] <= fdispatch_fsqrt_s(F[rs1]{32}, choose(rm<7, rm{8}, FCSR{8}));
146
+            if(FLEN==32)
147
+                F[rd] <= res;
148
+            else { // NaN boxing
149
+                val upper[FLEN] <= -1;
150
+                F[rd] <= (upper<<32) | zext(res, FLEN);
151
+            }
152
+            val flags[32] <= fdispatch_fget_flags();
153
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
154
+        }
155
+        FSGNJ.S {
156
+            encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
157
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
158
+            val res[32] <= (F[rs1]{32} & 0x7fffffff) | (F[rs2]{32} & 0x80000000);
159
+            if(FLEN==32)
160
+                F[rd] <= res;
161
+            else { // NaN boxing
162
+                val upper[FLEN] <= -1;
163
+                F[rd] <= (upper<<32) | zext(res, FLEN);
164
+            }
165
+        }
166
+        FSGNJN.S {
167
+            encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
168
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
169
+            val res[32] <= (F[rs1]{32} & 0x7fffffff) | (~F[rs2]{32} & 0x80000000);
170
+            if(FLEN==32)
171
+                F[rd] <= res;
172
+            else { // NaN boxing
173
+                val upper[FLEN] <= -1;
174
+                F[rd] <= (upper<<32) | zext(res, FLEN);
175
+            }
176
+        }
177
+        FSGNJX.S {
178
+            encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
179
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
180
+            val res[32] <= F[rs1]{32} ^ (F[rs2]{32} & 0x80000000);
181
+            if(FLEN==32)
182
+                F[rd] <= res;
183
+            else { // NaN boxing
184
+                val upper[FLEN] <= -1;
185
+                F[rd] <= (upper<<32) | zext(res, FLEN);
186
+            }
187
+        }
188
+        FMIN.S  {
189
+            encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
190
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
191
+            //F[rd]f<= choose(F[rs1]f<F[rs2]f, F[rs1]f, F[rs2]f);
192
+            val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
193
+            if(FLEN==32)
194
+                F[rd] <= res;
195
+            else { // NaN boxing
196
+                val upper[FLEN] <= -1;
197
+                F[rd] <= (upper<<32) | zext(res, FLEN);
198
+            }
199
+            val flags[32] <= fdispatch_fget_flags();
200
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
201
+        }
202
+        FMAX.S {
203
+            encoding: b0010100 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
204
+            args_disass:"f%rd$d, f%rs1$d, f%rs2$d";
205
+            //F[rd]f<= choose(F[rs1]f>F[rs2]f, F[rs1]f, F[rs2]f);
206
+            val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
207
+            if(FLEN==32)
208
+                F[rd] <= res;
209
+            else { // NaN boxing
210
+                val upper[FLEN] <= -1;
211
+                F[rd] <= (upper<<32) | zext(res, FLEN);
212
+            }
213
+            val flags[32] <= fdispatch_fget_flags();
214
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
215
+        }
216
+        FCVT.W.S {
217
+            encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
218
+            args_disass:"x%rd$d, f%rs1$d";
219
+            X[rd]<= sext(fdispatch_fcvt_s(F[rs1]{32}, zext(0, 32), rm{8}), XLEN);
220
+            val flags[32] <= fdispatch_fget_flags();
221
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
222
+        }
223
+        FCVT.WU.S {
224
+            encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
225
+            args_disass:"x%rd$d, f%rs1$d";
226
+            X[rd]<= zext(fdispatch_fcvt_s(F[rs1]{32}, zext(1, 32), rm{8}), XLEN);
227
+            val flags[32] <= fdispatch_fget_flags();
228
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
229
+        }
230
+        FEQ.S {
231
+            encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011;
232
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
233
+            X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32));
234
+            val flags[32] <= fdispatch_fget_flags();
235
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
236
+        }
237
+        FLT.S {
238
+            encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011;
239
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
240
+            X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32));
241
+            val flags[32] <= fdispatch_fget_flags();
242
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
243
+        }
244
+        FLE.S {
245
+            encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011;
246
+            args_disass:"x%rd$d, f%rs1$d, f%rs2$d";
247
+            X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32));
248
+            val flags[32] <= fdispatch_fget_flags();
249
+            FCSR <= (FCSR & ~FFLAG_MASK) + flags{5};
250
+        }
251
+        FCLASS.S {
252
+            encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011;
253
+            args_disass:"x%rd$d, f%rs1$d";
254
+            X[rd]<=fdispatch_fclass_s(F[rs1]{32});
255
+        }
256
+        FCVT.S.W {
257
+            encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
258
+            args_disass:"f%rd$d, x%rs1$d";
259
+            val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8});
260
+            if(FLEN==32)
261
+                F[rd] <= res;
262
+            else { // NaN boxing
263
+                val upper[FLEN] <= -1;
264
+                F[rd] <= (upper<<32) | zext(res, FLEN);
265
+            }
266
+        }
267
+        FCVT.S.WU {
268
+            encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011;
269
+            args_disass:"f%rd$d, x%rs1$d";
270
+            val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8});
271
+            if(FLEN==32)
272
+                F[rd] <= res;
273
+            else { // NaN boxing
274
+                val upper[FLEN] <= -1;
275
+                F[rd] <= (upper<<32) | zext(res, FLEN);
276
+            }
277
+        }
278
+        FMV.X.W {
279
+            encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
280
+            args_disass:"x%rd$d, f%rs1$d";
281
+            X[rd]<=sext(F[rs1]{32});
282
+        }
283
+        FMV.W.X {
284
+            encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011;
285
+            args_disass:"f%rd$d, x%rs1$d";
286
+            if(FLEN==32)
287
+                F[rd] <= X[rs1];
288
+            else { // NaN boxing
289
+                val upper[FLEN] <= -1;
290
+                F[rd] <= (upper<<32) | zext(X[rs1], FLEN);
291
+            }
292
+        }
293
+    }
294 294
 }

+ 308
- 307
riscv/gen_input/RV32IBase.core_desc View File

@@ -1,325 +1,326 @@
1 1
 InsructionSet RV32IBase {
2
-	constants {
3
-		XLEN,
4
-		PCLEN,
5
-		XLEN_BIT_MASK:=0x1f,
2
+    constants {
3
+        XLEN,
4
+        PCLEN,
5
+        XLEN_BIT_MASK:=0x1f,
6 6
         fence:=0,
7 7
         fencei:=1,
8 8
         fencevmal:=2,
9 9
         fencevmau:=3
10
-	}
11
-	
12
-	address_spaces { 
13
-		MEM[8], CSR[XLEN], FENCE[XLEN]
14
-	}
15
-				
16
-	registers { 
17
-		[31:0]   X[XLEN],
18
-                PC[XLEN](is_pc)
19
-	}
20
-	 
21
-	instructions { 
22
-		LUI{
23
-		    encoding: imm[31:12]s | rd[4:0] | b0110111;
24
-		    args_disass: "x%rd$d, 0x%imm$05x";
25
-		    if(rd!=0) X[rd] <= imm;
26
-		}
27
-		AUIPC{
28
-		    encoding: imm[31:12]s | rd[4:0] | b0010111;
29
-		    args_disass: "x%rd%, 0x%imm$08x";
30
-		    if(rd!=0) X[rd] <= PC+imm;
31
-		}
32
-	    JAL(no_cont){
33
-    		encoding: imm[20:20]s | imm[10:1]s | imm[11:11]s | imm[19:12]s | rd[4:0] | b1101111;
34
-		    args_disass: "x%rd$d, 0x%imm$x";
35
-    		if(rd!=0) X[rd] <= PC+4;
36
-    		PC<=PC+imm;
37
-		}
38
-	    JALR(no_cont){
39
-	    	encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
40
-		    args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
10
+    }
11
+    
12
+    address_spaces { 
13
+        MEM[8], CSR[XLEN], FENCE[XLEN]
14
+    }
15
+                
16
+    registers { 
17
+        [31:0]   X[XLEN],
18
+                PC[XLEN](is_pc),
19
+                alias ZERO[XLEN] is X[0] 
20
+    }
21
+     
22
+    instructions { 
23
+        LUI{
24
+            encoding: imm[31:12]s | rd[4:0] | b0110111;
25
+            args_disass: "x%rd$d, 0x%imm$05x";
26
+            if(rd!=0) X[rd] <= imm;
27
+        }
28
+        AUIPC{
29
+            encoding: imm[31:12]s | rd[4:0] | b0010111;
30
+            args_disass: "x%rd%, 0x%imm$08x";
31
+            if(rd!=0) X[rd] <= PC+imm;
32
+        }
33
+        JAL(no_cont){
34
+            encoding: imm[20:20]s | imm[10:1]s | imm[11:11]s | imm[19:12]s | rd[4:0] | b1101111;
35
+            args_disass: "x%rd$d, 0x%imm$x";
36
+            if(rd!=0) X[rd] <= PC+4;
37
+            PC<=PC+imm;
38
+        }
39
+        JALR(no_cont){
40
+            encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111;
41
+            args_disass: "x%rd$d, x%rs1$d, 0x%imm$x";
41 42
             val new_pc[XLEN] <= X[rs1]+ imm;
42 43
             val align[XLEN] <= new_pc & 0x2;
43
-		    if(align != 0){
44
-		        raise(0, 0);
45
-		    } else {
46
-        		if(rd!=0) X[rd] <= PC+4;
47
-        		PC<=new_pc & ~0x1;
48
-    		}
49
-	    }
50
-		BEQ(no_cont,cond){
51
-		    encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011;
52
-		    args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
53
-		    PC<=choose(X[rs1]==X[rs2], PC+imm, PC+4);
54
-		}
55
-		BNE(no_cont,cond){
56
-		    encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011;
57
-		    args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
58
-	    	PC<=choose(X[rs1]!=X[rs2], PC+imm, PC+4);
59
-		}
60
-		BLT(no_cont,cond){
61
-		    encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011;
62
-		    args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
63
-	    	PC<=choose(X[rs1]s<X[rs2]s, PC+imm, PC+4);
64
-		}
65
-		BGE(no_cont,cond) {
66
-		    encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b101 | imm[4:1]s | imm[11:11]s | b1100011;
67
-		    args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
68
-	    	PC<=choose(X[rs1]s>=X[rs2]s, PC+imm, PC+4);
69
-		}
70
-		BLTU(no_cont,cond) {
71
-		    encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011;
72
-		    args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
73
-	    	PC<=choose(X[rs1]<X[rs2],PC+imm, PC+4);
74
-		}
75
-		BGEU(no_cont,cond) {
76
-		    encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b111 | imm[4:1]s | imm[11:11]s | b1100011;
77
-		    args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
78
-	    	PC<=choose(X[rs1]>=X[rs2], PC+imm, PC+4);
79
-		}
80
-		LB {
81
-		    encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0000011;
82
-		    args_disass:"x%rd$d, %imm%(x%rs1$d)";
83
-		    val offs[XLEN] <= X[rs1]+imm;
84
-		    if(rd!=0) X[rd]<=sext(MEM[offs]);
85
-		}
86
-		LH {
87
-		    encoding: imm[11:0]s | rs1[4:0] | b001 | rd[4:0] | b0000011;
88
-		    args_disass:"x%rd$d, %imm%(x%rs1$d)";
89
-		    val offs[XLEN] <= X[rs1]+imm;
90
-		    if(rd!=0) X[rd]<=sext(MEM[offs]{16});		    
91
-		}
92
-		LW {
93
-		    encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011;
94
-		    args_disass:"x%rd$d, %imm%(x%rs1$d)";
95
-		    val offs[XLEN] <= X[rs1]+imm;
96
-		    if(rd!=0) X[rd]<=sext(MEM[offs]{32});
97
-		}
98
-		LBU {
99
-		    encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0000011;
100
-		    args_disass:"x%rd$d, %imm%(x%rs1$d)";
101
-		    val offs[XLEN] <= X[rs1]+imm;
102
-		    if(rd!=0) X[rd]<=zext(MEM[offs]);
103
-		}
104
-		LHU {
105
-		    encoding: imm[11:0]s | rs1[4:0] | b101 | rd[4:0] | b0000011;
106
-		    args_disass:"x%rd$d, %imm%(x%rs1$d)";
107
-		    val offs[XLEN] <= X[rs1]+imm;
108
-		    if(rd!=0) X[rd]<=zext(MEM[offs]{16});		    
109
-		}
110
-		SB {
111
-		    encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:0]s | b0100011;
112
-		    args_disass:"x%rs2$d, %imm%(x%rs1$d)";
113
-	    	val offs[XLEN] <= X[rs1] + imm;
114
-	    	MEM[offs] <= X[rs2];
115
-		}
116
-		SH {
117
-		    encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:0]s | b0100011;
118
-		    args_disass:"x%rs2$d, %imm%(x%rs1$d)";
119
-	    	val offs[XLEN] <= X[rs1] + imm;
120
-	    	MEM[offs]{16} <= X[rs2];
121
-		}
122
-	    SW {
123
-	    	encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100011;
124
-		    args_disass:"x%rs2$d, %imm%(x%rs1$d)";
125
-	    	val offs[XLEN] <= X[rs1] + imm;
126
-	    	MEM[offs]{32} <= X[rs2];
127
-	    }
128
-		ADDI {
129
-			encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0010011;
130
-		    args_disass:"x%rd$d, x%rs1$d, %imm%";
131
-			if(rd != 0) X[rd] <= X[rs1] + imm;
132
-		}
133
-		SLTI {
134
-			encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0010011;
135
-		    args_disass:"x%rd$d, x%rs1$d, %imm%";
136
-			if (rd != 0) X[rd] <= choose(X[rs1]s < imm's, 1, 0); //TODO: needs fix
137
-		}
138
-	    SLTIU {
139
-	        encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0010011;
140
-		    args_disass:"x%rd$d, x%rs1$d, %imm%";
141
-		    val full_imm[XLEN] <= imm's;
142
-	        if (rd != 0) X[rd] <= choose(X[rs1]'u < full_imm'u, 1, 0);
143
-	    }
144
-		XORI {
145
-			encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0010011;
146
-		    args_disass:"x%rd$d, x%rs1$d, %imm%";
147
-			if(rd != 0) X[rd] <= X[rs1] ^ imm;
148
-		}
149
-		ORI {
150
-			encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0010011;
151
-		    args_disass:"x%rd$d, x%rs1$d, %imm%";
152
-			if(rd != 0) X[rd] <= X[rs1] | imm;
153
-		}
154
-		ANDI {
155
-			encoding: imm[11:0]s | rs1[4:0] | b111 | rd[4:0] | b0010011;
156
-		    args_disass:"x%rd$d, x%rs1$d, %imm%";
157
-			if(rd != 0) X[rd] <= X[rs1] & imm;
158
-		}
159
-		SLLI {
160
-		    encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
161
-		    args_disass:"x%rd$d, x%rs1$d, %shamt%";
162
-		    if(shamt > 31){
163
-		        raise(0,0);
164
-		    } else {
165
-		        if(rd != 0) X[rd] <= shll(X[rs1], shamt);
166
-		    }
167
-		}
168
-		SRLI {
169
-		    encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
170
-		    args_disass:"x%rd$d, x%rs1$d, %shamt%";
44
+            if(align != 0){
45
+                raise(0, 0);
46
+            } else {
47
+                if(rd!=0) X[rd] <= PC+4;
48
+                PC<=new_pc & ~0x1;
49
+            }
50
+        }
51
+        BEQ(no_cont,cond){
52
+            encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011;
53
+            args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
54
+            PC<=choose(X[rs1]==X[rs2], PC+imm, PC+4);
55
+        }
56
+        BNE(no_cont,cond){
57
+            encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011;
58
+            args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
59
+            PC<=choose(X[rs1]!=X[rs2], PC+imm, PC+4);
60
+        }
61
+        BLT(no_cont,cond){
62
+            encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011;
63
+            args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
64
+            PC<=choose(X[rs1]s<X[rs2]s, PC+imm, PC+4);
65
+        }
66
+        BGE(no_cont,cond) {
67
+            encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b101 | imm[4:1]s | imm[11:11]s | b1100011;
68
+            args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
69
+            PC<=choose(X[rs1]s>=X[rs2]s, PC+imm, PC+4);
70
+        }
71
+        BLTU(no_cont,cond) {
72
+            encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011;
73
+            args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
74
+            PC<=choose(X[rs1]<X[rs2],PC+imm, PC+4);
75
+        }
76
+        BGEU(no_cont,cond) {
77
+            encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b111 | imm[4:1]s | imm[11:11]s | b1100011;
78
+            args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x";
79
+            PC<=choose(X[rs1]>=X[rs2], PC+imm, PC+4);
80
+        }
81
+        LB {
82
+            encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0000011;
83
+            args_disass:"x%rd$d, %imm%(x%rs1$d)";
84
+            val offs[XLEN] <= X[rs1]+imm;
85
+            if(rd!=0) X[rd]<=sext(MEM[offs]);
86
+        }
87
+        LH {
88
+            encoding: imm[11:0]s | rs1[4:0] | b001 | rd[4:0] | b0000011;
89
+            args_disass:"x%rd$d, %imm%(x%rs1$d)";
90
+            val offs[XLEN] <= X[rs1]+imm;
91
+            if(rd!=0) X[rd]<=sext(MEM[offs]{16});            
92
+        }
93
+        LW {
94
+            encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011;
95
+            args_disass:"x%rd$d, %imm%(x%rs1$d)";
96
+            val offs[XLEN] <= X[rs1]+imm;
97
+            if(rd!=0) X[rd]<=sext(MEM[offs]{32});
98
+        }
99
+        LBU {
100
+            encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0000011;
101
+            args_disass:"x%rd$d, %imm%(x%rs1$d)";
102
+            val offs[XLEN] <= X[rs1]+imm;
103
+            if(rd!=0) X[rd]<=zext(MEM[offs]);
104
+        }
105
+        LHU {
106
+            encoding: imm[11:0]s | rs1[4:0] | b101 | rd[4:0] | b0000011;
107
+            args_disass:"x%rd$d, %imm%(x%rs1$d)";
108
+            val offs[XLEN] <= X[rs1]+imm;
109
+            if(rd!=0) X[rd]<=zext(MEM[offs]{16});            
110
+        }
111
+        SB {
112
+            encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:0]s | b0100011;
113
+            args_disass:"x%rs2$d, %imm%(x%rs1$d)";
114
+            val offs[XLEN] <= X[rs1] + imm;
115
+            MEM[offs] <= X[rs2];
116
+        }
117
+        SH {
118
+            encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:0]s | b0100011;
119
+            args_disass:"x%rs2$d, %imm%(x%rs1$d)";
120
+            val offs[XLEN] <= X[rs1] + imm;
121
+            MEM[offs]{16} <= X[rs2];
122
+        }
123
+        SW {
124
+            encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100011;
125
+            args_disass:"x%rs2$d, %imm%(x%rs1$d)";
126
+            val offs[XLEN] <= X[rs1] + imm;
127
+            MEM[offs]{32} <= X[rs2];
128
+        }
129
+        ADDI {
130
+            encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0010011;
131
+            args_disass:"x%rd$d, x%rs1$d, %imm%";
132
+            if(rd != 0) X[rd] <= X[rs1] + imm;
133
+        }
134
+        SLTI {
135
+            encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0010011;
136
+            args_disass:"x%rd$d, x%rs1$d, %imm%";
137
+            if (rd != 0) X[rd] <= choose(X[rs1]s < imm's, 1, 0);
138
+        }
139
+        SLTIU {
140
+            encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0010011;
141
+            args_disass:"x%rd$d, x%rs1$d, %imm%";
142
+            val full_imm[XLEN] <= imm's;
143
+            if (rd != 0) X[rd] <= choose(X[rs1]'u < full_imm'u, 1, 0);
144
+        }
145
+        XORI {
146
+            encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0010011;
147
+            args_disass:"x%rd$d, x%rs1$d, %imm%";
148
+            if(rd != 0) X[rd] <= X[rs1] ^ imm;
149
+        }
150
+        ORI {
151
+            encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0010011;
152
+            args_disass:"x%rd$d, x%rs1$d, %imm%";
153
+            if(rd != 0) X[rd] <= X[rs1] | imm;
154
+        }
155
+        ANDI {
156
+            encoding: imm[11:0]s | rs1[4:0] | b111 | rd[4:0] | b0010011;
157
+            args_disass:"x%rd$d, x%rs1$d, %imm%";
158
+            if(rd != 0) X[rd] <= X[rs1] & imm;
159
+        }
160
+        SLLI {
161
+            encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0010011;
162
+            args_disass:"x%rd$d, x%rs1$d, %shamt%";
163
+            if(shamt > 31){
164
+                raise(0,0);
165
+            } else {
166
+                if(rd != 0) X[rd] <= shll(X[rs1], shamt);
167
+            }
168
+        }
169
+        SRLI {
170
+            encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
171
+            args_disass:"x%rd$d, x%rs1$d, %shamt%";
171 172
             if(shamt > 31){
172 173
                 raise(0,0);
173 174
             } else {
174
-		        if(rd != 0) X[rd] <= shrl(X[rs1], shamt);
175
-		    }
176
-		}
177
-		SRAI {
178
-		    encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
179
-		    args_disass:"x%rd$d, x%rs1$d, %shamt%";
180
-		    if(shamt > 31){
175
+                if(rd != 0) X[rd] <= shrl(X[rs1], shamt);
176
+            }
177
+        }
178
+        SRAI {
179
+            encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011;
180
+            args_disass:"x%rd$d, x%rs1$d, %shamt%";
181
+            if(shamt > 31){
181 182
                 raise(0,0);
182 183
             } else {
183
-		        if(rd != 0) X[rd] <= shra(X[rs1], shamt);
184
-		    }
185
-		}
186
-		ADD {
187
-		    encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
188
-		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
189
-			if(rd != 0) X[rd] <= X[rs1] + X[rs2];
190
-		}
191
-		SUB {
192
-		    encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
193
-		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
194
-			if(rd != 0) X[rd] <= X[rs1] - X[rs2];
195
-		}
196
-		SLL {
197
-		    encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
198
-		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
199
-		    if(rd != 0) X[rd] <= shll(X[rs1], X[rs2]&XLEN_BIT_MASK);
200
-		}
201
-		SLT {
202