Browse Source

Streamline arch descriptions according to latest CoreDSL changes

Eyck Jentzsch 1 year ago
parent
commit
142654b0a2

+ 34
- 0
etc/dbt-riscv dhrystone.launch View File

@@ -0,0 +1,34 @@
1
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
2
+<launchConfiguration type="org.eclipse.cdt.launch.applicationLaunchType">
3
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.AUTO_SOLIB" value="true"/>
4
+<listAttribute key="org.eclipse.cdt.dsf.gdb.AUTO_SOLIB_LIST"/>
5
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="gdb"/>
6
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_ON_FORK" value="false"/>
7
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.GDB_INIT" value=".gdbinit"/>
8
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
9
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE" value="false"/>
10
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE_MODE" value="UseSoftTrace"/>
11
+<listAttribute key="org.eclipse.cdt.dsf.gdb.SOLIB_PATH"/>
12
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.TRACEPOINT_MODE" value="TP_NORMAL_ONLY"/>
13
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
14
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.internal.ui.launching.LocalApplicationCDebuggerTab.DEFAULTS_SET" value="true"/>
15
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
16
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
17
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="gdb"/>
18
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
19
+<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
20
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
21
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_ARGUMENTS" value="-v4&#10;${project_loc:dhrystone}/dhrystone"/>
22
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="build/Release/riscv/bin/riscv"/>
23
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="DBT-RISE-RISCV"/>
24
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
25
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
26
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
27
+<listEntry value="/DBT-RISE-RISCV"/>
28
+</listAttribute>
29
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
30
+<listEntry value="4"/>
31
+</listAttribute>
32
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#10;"/>
33
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
34
+</launchConfiguration>

+ 1
- 1
riscv/gen_input/RV32D.core_desc View File

@@ -2,7 +2,7 @@ import "RV32IBase.core_desc"
2 2
 
3 3
 InsructionSet RV32D extends RV32IBase{
4 4
 	constants {
5
-		FLEN, FFLAG_MASK
5
+		FLEN, FFLAG_MASK := 0x1f
6 6
 	} 
7 7
 	registers {
8 8
 		[31:0]    F[FLEN],  FCSR[32]

+ 1
- 1
riscv/gen_input/RV32F.core_desc View File

@@ -2,7 +2,7 @@ import "RV32IBase.core_desc"
2 2
 
3 3
 InsructionSet RV32F extends RV32IBase{
4 4
 	constants {
5
-		FLEN, FFLAG_MASK
5
+		FLEN, FFLAG_MASK := 0x1f
6 6
 	} 
7 7
 	registers {
8 8
 		[31:0]    F[FLEN],  FCSR[32]

+ 5
- 5
riscv/gen_input/RV32IBase.core_desc View File

@@ -1,12 +1,12 @@
1 1
 InsructionSet RV32IBase {
2 2
 	constants {
3 3
 		XLEN,
4
-		XLEN_BIT_MASK,
5 4
 		PCLEN,
6
-		fence,
7
-		fencei,
8
-		fencevmal,
9
-		fencevmau
5
+		XLEN_BIT_MASK:=0x1f,
6
+        fence:=0,
7
+        fencei:=1,
8
+        fencevmal:=2,
9
+        fencevmau:=3
10 10
 	}
11 11
 	
12 12
 	address_spaces { 

+ 5
- 5
riscv/gen_input/RV32M.core_desc View File

@@ -2,14 +2,14 @@ import "RV32IBase.core_desc"
2 2
 
3 3
 InsructionSet RV32M extends RV32IBase {
4 4
 	constants {
5
-		XLEN2
5
+		MAXLEN:=128
6 6
 	}
7 7
 	instructions{       
8 8
 		MUL{
9 9
 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
10 10
 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
11 11
 		    if(rd != 0){
12
-		        val res[XLEN2] <= zext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
12
+		        val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
13 13
 		    	X[rd]<= zext(res , XLEN);
14 14
 		    }
15 15
 		}
@@ -17,7 +17,7 @@ InsructionSet RV32M extends RV32IBase {
17 17
 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
18 18
 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
19 19
 		    if(rd != 0){
20
-		        val res[XLEN2] <= sext(X[rs1], XLEN2) * sext(X[rs2], XLEN2);
20
+		        val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN);
21 21
                 X[rd]<= zext(res >> XLEN, XLEN);
22 22
 		    }
23 23
 		}
@@ -25,7 +25,7 @@ InsructionSet RV32M extends RV32IBase {
25 25
 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
26 26
 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
27 27
 		    if(rd != 0){
28
-                val res[XLEN2] <= sext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
28
+                val res[MAXLEN] <= sext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
29 29
                 X[rd]<= zext(res >> XLEN, XLEN);
30 30
 		    }
31 31
 		}
@@ -33,7 +33,7 @@ InsructionSet RV32M extends RV32IBase {
33 33
 			encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
34 34
 		    args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
35 35
 		    if(rd != 0){
36
-                val res[XLEN2] <= zext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
36
+                val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
37 37
                 X[rd]<= zext(res >> XLEN, XLEN);
38 38
 		    }
39 39
 		}

+ 5
- 21
riscv/gen_input/minres_rv.core_desc View File

@@ -13,15 +13,10 @@ Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
13 13
     template:"vm_riscv.in.cpp";
14 14
     constants {
15 15
         XLEN:=32;
16
-        XLEN2:=64;
17
-        XLEN_BIT_MASK:=0x1f;
18 16
         PCLEN:=32;
19
-        fence:=0;
20
-        fencei:=1;
21
-        fencevmal:=2;
22
-        fencevmau:=3;
17
+        // definitions for the architecture wrapper
23 18
         //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
24
-        MISA_VAL:=0b01000000000101000001000100000001;
19
+        MISA_VAL:=0b01000000000101000001000100000101;
25 20
         PGSIZE := 4096; //1 << 12;
26 21
         PGMASK := 4095; //PGSIZE-1
27 22
     }
@@ -31,18 +26,12 @@ Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32
31 26
     constants {
32 27
         XLEN:=32;
33 28
         FLEN:=64;
34
-        XLEN2:=64;
35
-        XLEN_BIT_MASK:=0x1f;
36 29
         PCLEN:=32;
37
-        fence:=0;
38
-        fencei:=1;
39
-        fencevmal:=2;
40
-        fencevmau:=3;
30
+        // definitions for the architecture wrapper
41 31
         //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
42
-        MISA_VAL:=0b01000000000101000001000100000001;
32
+        MISA_VAL:=0b01000000000101000001000100101101;
43 33
         PGSIZE := 4096; //1 << 12;
44 34
         PGMASK := 4095; //PGSIZE-1
45
-        FFLAG_MASK:=0x1f;
46 35
     }
47 36
 }
48 37
 
@@ -51,13 +40,8 @@ Core RV64IA provides RV64IBase, RV64A, RV32A {
51 40
     template:"vm_riscv.in.cpp";
52 41
     constants {
53 42
         XLEN:=64;
54
-        XLEN2:=128;
55
-        XLEN_BIT_MASK:=0x3f;
56 43
         PCLEN:=64;
57
-        fence:=0;
58
-        fencei:=1;
59
-        fencevmal:=2;
60
-        fencevmau:=3;
44
+        // definitions for the architecture wrapper
61 45
         //          XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
62 46
         MISA_VAL:=0b10000000000001000000000100000001;
63 47
         PGSIZE := 4096; //1 << 12;

+ 1
- 1
riscv/incl/iss/arch/rv32gc.h View File

@@ -48,7 +48,7 @@ struct traits<rv32gc> {
48 48
 
49 49
 	constexpr static char const* const core_type = "RV32GC";
50 50
     
51
-    enum constants {XLEN=32, FLEN=64, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095, FFLAG_MASK=31};
51
+    enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=1075056941, PGSIZE=4096, PGMASK=4095};
52 52
 
53 53
     constexpr static unsigned FP_REGS_SIZE = 64;
54 54
 

+ 1
- 1
riscv/incl/iss/arch/rv32imac.h View File

@@ -48,7 +48,7 @@ struct traits<rv32imac> {
48 48
 
49 49
 	constexpr static char const* const core_type = "RV32IMAC";
50 50
     
51
-    enum constants {XLEN=32, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095};
51
+    enum constants {XLEN=32, PCLEN=32, MISA_VAL=1075056901, PGSIZE=4096, PGMASK=4095};
52 52
 
53 53
     constexpr static unsigned FP_REGS_SIZE = 0;
54 54
 

+ 1
- 1
riscv/incl/iss/arch/rv64ia.h View File

@@ -48,7 +48,7 @@ struct traits<rv64ia> {
48 48
 
49 49
 	constexpr static char const* const core_type = "RV64IA";
50 50
     
51
-    enum constants {XLEN=64, XLEN2=128, XLEN_BIT_MASK=63, PCLEN=64, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095};
51
+    enum constants {XLEN=64, PCLEN=64, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095};
52 52
 
53 53
     constexpr static unsigned FP_REGS_SIZE = 0;
54 54
 

+ 8
- 8
riscv/src/internal/vm_rv32gc.cpp View File

@@ -2578,11 +2578,11 @@ private:
2578 2578
     	    Value* res_val = this->builder.CreateMul(
2579 2579
     	        this->gen_ext(
2580 2580
     	            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2581
-    	            64,
2581
+    	            128,
2582 2582
     	            false),
2583 2583
     	        this->gen_ext(
2584 2584
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2585
-    	            64,
2585
+    	            128,
2586 2586
     	            false));
2587 2587
     	    Value* X_rd_val = this->gen_ext(
2588 2588
     	        res_val,
@@ -2625,11 +2625,11 @@ private:
2625 2625
     	    Value* res_val = this->builder.CreateMul(
2626 2626
     	        this->gen_ext(
2627 2627
     	            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2628
-    	            64,
2628
+    	            128,
2629 2629
     	            true),
2630 2630
     	        this->gen_ext(
2631 2631
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2632
-    	            64,
2632
+    	            128,
2633 2633
     	            true));
2634 2634
     	    Value* X_rd_val = this->gen_ext(
2635 2635
     	        this->builder.CreateLShr(
@@ -2674,11 +2674,11 @@ private:
2674 2674
     	    Value* res_val = this->builder.CreateMul(
2675 2675
     	        this->gen_ext(
2676 2676
     	            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2677
-    	            64,
2677
+    	            128,
2678 2678
     	            true),
2679 2679
     	        this->gen_ext(
2680 2680
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2681
-    	            64,
2681
+    	            128,
2682 2682
     	            false));
2683 2683
     	    Value* X_rd_val = this->gen_ext(
2684 2684
     	        this->builder.CreateLShr(
@@ -2723,11 +2723,11 @@ private:
2723 2723
     	    Value* res_val = this->builder.CreateMul(
2724 2724
     	        this->gen_ext(
2725 2725
     	            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2726
-    	            64,
2726
+    	            128,
2727 2727
     	            false),
2728 2728
     	        this->gen_ext(
2729 2729
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2730
-    	            64,
2730
+    	            128,
2731 2731
     	            false));
2732 2732
     	    Value* X_rd_val = this->gen_ext(
2733 2733
     	        this->builder.CreateLShr(

+ 8
- 8
riscv/src/internal/vm_rv32imac.cpp View File

@@ -2458,11 +2458,11 @@ private:
2458 2458
     	    Value* res_val = this->builder.CreateMul(
2459 2459
     	        this->gen_ext(
2460 2460
     	            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2461
-    	            64,
2461
+    	            128,
2462 2462
     	            false),
2463 2463
     	        this->gen_ext(
2464 2464
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2465
-    	            64,
2465
+    	            128,
2466 2466
     	            false));
2467 2467
     	    Value* X_rd_val = this->gen_ext(
2468 2468
     	        res_val,
@@ -2505,11 +2505,11 @@ private:
2505 2505
     	    Value* res_val = this->builder.CreateMul(
2506 2506
     	        this->gen_ext(
2507 2507
     	            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2508
-    	            64,
2508
+    	            128,
2509 2509
     	            true),
2510 2510
     	        this->gen_ext(
2511 2511
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2512
-    	            64,
2512
+    	            128,
2513 2513
     	            true));
2514 2514
     	    Value* X_rd_val = this->gen_ext(
2515 2515
     	        this->builder.CreateLShr(
@@ -2554,11 +2554,11 @@ private:
2554 2554
     	    Value* res_val = this->builder.CreateMul(
2555 2555
     	        this->gen_ext(
2556 2556
     	            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2557
-    	            64,
2557
+    	            128,
2558 2558
     	            true),
2559 2559
     	        this->gen_ext(
2560 2560
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2561
-    	            64,
2561
+    	            128,
2562 2562
     	            false));
2563 2563
     	    Value* X_rd_val = this->gen_ext(
2564 2564
     	        this->builder.CreateLShr(
@@ -2603,11 +2603,11 @@ private:
2603 2603
     	    Value* res_val = this->builder.CreateMul(
2604 2604
     	        this->gen_ext(
2605 2605
     	            this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2606
-    	            64,
2606
+    	            128,
2607 2607
     	            false),
2608 2608
     	        this->gen_ext(
2609 2609
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2610
-    	            64,
2610
+    	            128,
2611 2611
     	            false));
2612 2612
     	    Value* X_rd_val = this->gen_ext(
2613 2613
     	        this->builder.CreateLShr(

+ 3
- 3
riscv/src/internal/vm_rv64ia.cpp View File

@@ -2128,7 +2128,7 @@ private:
2128 2128
     	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2129 2129
     	        this->builder.CreateAnd(
2130 2130
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2131
-    	            this->gen_const(64U, 63)));
2131
+    	            this->gen_const(64U, 31)));
2132 2132
     	    this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
2133 2133
     	}
2134 2134
     	this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
@@ -2298,7 +2298,7 @@ private:
2298 2298
     	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2299 2299
     	        this->builder.CreateAnd(
2300 2300
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2301
-    	            this->gen_const(64U, 63)));
2301
+    	            this->gen_const(64U, 31)));
2302 2302
     	    this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
2303 2303
     	}
2304 2304
     	this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
@@ -2337,7 +2337,7 @@ private:
2337 2337
     	        this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
2338 2338
     	        this->builder.CreateAnd(
2339 2339
     	            this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
2340
-    	            this->gen_const(64U, 63)));
2340
+    	            this->gen_const(64U, 31)));
2341 2341
     	    this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
2342 2342
     	}
2343 2343
     	this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);