Generic RISC-V ISS
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  1. ////////////////////////////////////////////////////////////////////////////////
  2. // Copyright (C) 2017, MINRES Technologies GmbH
  3. // All rights reserved.
  4. //
  5. // Redistribution and use in source and binary forms, with or without
  6. // modification, are permitted provided that the following conditions are met:
  7. //
  8. // 1. Redistributions of source code must retain the above copyright notice,
  9. // this list of conditions and the following disclaimer.
  10. //
  11. // 2. Redistributions in binary form must reproduce the above copyright notice,
  12. // this list of conditions and the following disclaimer in the documentation
  13. // and/or other materials provided with the distribution.
  14. //
  15. // 3. Neither the name of the copyright holder nor the names of its contributors
  16. // may be used to endorse or promote products derived from this software
  17. // without specific prior written permission.
  18. //
  19. // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20. // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21. // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22. // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23. // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24. // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25. // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26. // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27. // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28. // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29. // POSSIBILITY OF SUCH DAMAGE.
  30. //
  31. ////////////////////////////////////////////////////////////////////////////////
  32. #ifndef _RV64IA_H_
  33. #define _RV64IA_H_
  34. #include <iss/arch_if.h>
  35. #include <iss/vm_if.h>
  36. #include <iss/arch/traits.h>
  37. #include <array>
  38. namespace iss {
  39. namespace arch {
  40. struct rv64ia;
  41. template<>
  42. struct traits<rv64ia> {
  43. constexpr static char const* const core_type = "RV64IA";
  44. enum constants {XLEN=64, PCLEN=64, MISA_VAL=0b10000000000001000000000100000001, PGSIZE=0x1000, PGMASK=0xfff};
  45. constexpr static unsigned FP_REGS_SIZE = 0;
  46. enum reg_e {
  47. X0,
  48. X1,
  49. X2,
  50. X3,
  51. X4,
  52. X5,
  53. X6,
  54. X7,
  55. X8,
  56. X9,
  57. X10,
  58. X11,
  59. X12,
  60. X13,
  61. X14,
  62. X15,
  63. X16,
  64. X17,
  65. X18,
  66. X19,
  67. X20,
  68. X21,
  69. X22,
  70. X23,
  71. X24,
  72. X25,
  73. X26,
  74. X27,
  75. X28,
  76. X29,
  77. X30,
  78. X31,
  79. PC,
  80. NUM_REGS,
  81. NEXT_PC=NUM_REGS,
  82. TRAP_STATE,
  83. PENDING_TRAP,
  84. MACHINE_STATE,
  85. LAST_BRANCH,
  86. ICOUNT
  87. };
  88. using reg_t = uint64_t;
  89. using addr_t = uint64_t;
  90. using code_word_t = uint64_t; //TODO: check removal
  91. using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
  92. using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
  93. constexpr static unsigned reg_bit_width(unsigned r) {
  94. constexpr std::array<const uint32_t, 39> RV64IA_reg_size{{64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,32,64}};
  95. return RV64IA_reg_size[r];
  96. }
  97. constexpr static unsigned reg_byte_offset(unsigned r) {
  98. constexpr std::array<const uint32_t, 40> RV64IA_reg_byte_offset{{0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,284,288,296}};
  99. return RV64IA_reg_byte_offset[r];
  100. }
  101. static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
  102. enum sreg_flag_e {FLAGS};
  103. enum mem_type_e {MEM, CSR, FENCE, RES};
  104. };
  105. struct rv64ia: public arch_if {
  106. using virt_addr_t = typename traits<rv64ia>::virt_addr_t;
  107. using phys_addr_t = typename traits<rv64ia>::phys_addr_t;
  108. using reg_t = typename traits<rv64ia>::reg_t;
  109. using addr_t = typename traits<rv64ia>::addr_t;
  110. rv64ia();
  111. ~rv64ia();
  112. void reset(uint64_t address=0) override;
  113. uint8_t* get_regs_base_ptr() override;
  114. /// deprecated
  115. void get_reg(short idx, std::vector<uint8_t>& value) override {}
  116. void set_reg(short idx, const std::vector<uint8_t>& value) override {}
  117. /// deprecated
  118. bool get_flag(int flag) override {return false;}
  119. void set_flag(int, bool value) override {};
  120. /// deprecated
  121. void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
  122. uint64_t get_icount() { return reg.icount;}
  123. inline phys_addr_t v2p(const iss::addr_t& addr){
  124. if(addr.space != traits<rv64ia>::MEM ||
  125. addr.type == iss::address_type::PHYSICAL ||
  126. addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL){
  127. return phys_addr_t(addr.access, addr.space, addr.val&traits<rv64ia>::addr_mask);
  128. } else
  129. return virt2phys(addr);
  130. }
  131. virtual phys_addr_t virt2phys(const iss::addr_t& addr);
  132. virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
  133. inline
  134. uint32_t get_last_branch(){return reg.last_branch;}
  135. protected:
  136. struct RV64IA_regs {
  137. uint64_t X0 = 0;
  138. uint64_t X1 = 0;
  139. uint64_t X2 = 0;
  140. uint64_t X3 = 0;
  141. uint64_t X4 = 0;
  142. uint64_t X5 = 0;
  143. uint64_t X6 = 0;
  144. uint64_t X7 = 0;
  145. uint64_t X8 = 0;
  146. uint64_t X9 = 0;
  147. uint64_t X10 = 0;
  148. uint64_t X11 = 0;
  149. uint64_t X12 = 0;
  150. uint64_t X13 = 0;
  151. uint64_t X14 = 0;
  152. uint64_t X15 = 0;
  153. uint64_t X16 = 0;
  154. uint64_t X17 = 0;
  155. uint64_t X18 = 0;
  156. uint64_t X19 = 0;
  157. uint64_t X20 = 0;
  158. uint64_t X21 = 0;
  159. uint64_t X22 = 0;
  160. uint64_t X23 = 0;
  161. uint64_t X24 = 0;
  162. uint64_t X25 = 0;
  163. uint64_t X26 = 0;
  164. uint64_t X27 = 0;
  165. uint64_t X28 = 0;
  166. uint64_t X29 = 0;
  167. uint64_t X30 = 0;
  168. uint64_t X31 = 0;
  169. uint64_t PC = 0;
  170. uint64_t NEXT_PC = 0;
  171. uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
  172. uint64_t icount = 0;
  173. } reg;
  174. std::array<address_type, 4> addr_mode;
  175. uint32_t get_fcsr(){return 0;}
  176. void set_fcsr(uint32_t val){}
  177. };
  178. }
  179. }
  180. #endif /* _RV64IA_H_ */