Generic RISC-V ISS
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  1. ////////////////////////////////////////////////////////////////////////////////
  2. // Copyright (C) 2017, MINRES Technologies GmbH
  3. // All rights reserved.
  4. //
  5. // Redistribution and use in source and binary forms, with or without
  6. // modification, are permitted provided that the following conditions are met:
  7. //
  8. // 1. Redistributions of source code must retain the above copyright notice,
  9. // this list of conditions and the following disclaimer.
  10. //
  11. // 2. Redistributions in binary form must reproduce the above copyright notice,
  12. // this list of conditions and the following disclaimer in the documentation
  13. // and/or other materials provided with the distribution.
  14. //
  15. // 3. Neither the name of the copyright holder nor the names of its contributors
  16. // may be used to endorse or promote products derived from this software
  17. // without specific prior written permission.
  18. //
  19. // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20. // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21. // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22. // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23. // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24. // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25. // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26. // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27. // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28. // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29. // POSSIBILITY OF SUCH DAMAGE.
  30. //
  31. ////////////////////////////////////////////////////////////////////////////////
  32. #ifndef _RV32GC_H_
  33. #define _RV32GC_H_
  34. #include <iss/arch_if.h>
  35. #include <iss/vm_if.h>
  36. #include <iss/arch/traits.h>
  37. #include <array>
  38. namespace iss {
  39. namespace arch {
  40. struct rv32gc;
  41. template<>
  42. struct traits<rv32gc> {
  43. constexpr static char const* const core_type = "RV32GC";
  44. enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff};
  45. constexpr static unsigned FP_REGS_SIZE = 64;
  46. enum reg_e {
  47. X0,
  48. X1,
  49. X2,
  50. X3,
  51. X4,
  52. X5,
  53. X6,
  54. X7,
  55. X8,
  56. X9,
  57. X10,
  58. X11,
  59. X12,
  60. X13,
  61. X14,
  62. X15,
  63. X16,
  64. X17,
  65. X18,
  66. X19,
  67. X20,
  68. X21,
  69. X22,
  70. X23,
  71. X24,
  72. X25,
  73. X26,
  74. X27,
  75. X28,
  76. X29,
  77. X30,
  78. X31,
  79. PC,
  80. F0,
  81. F1,
  82. F2,
  83. F3,
  84. F4,
  85. F5,
  86. F6,
  87. F7,
  88. F8,
  89. F9,
  90. F10,
  91. F11,
  92. F12,
  93. F13,
  94. F14,
  95. F15,
  96. F16,
  97. F17,
  98. F18,
  99. F19,
  100. F20,
  101. F21,
  102. F22,
  103. F23,
  104. F24,
  105. F25,
  106. F26,
  107. F27,
  108. F28,
  109. F29,
  110. F30,
  111. F31,
  112. FCSR,
  113. NUM_REGS,
  114. NEXT_PC=NUM_REGS,
  115. TRAP_STATE,
  116. PENDING_TRAP,
  117. MACHINE_STATE,
  118. LAST_BRANCH,
  119. ICOUNT
  120. };
  121. using reg_t = uint32_t;
  122. using addr_t = uint32_t;
  123. using code_word_t = uint32_t; //TODO: check removal
  124. using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
  125. using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
  126. constexpr static unsigned reg_bit_width(unsigned r) {
  127. constexpr std::array<const uint32_t, 72> RV32GC_reg_size{{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,32,32,32,64}};
  128. return RV32GC_reg_size[r];
  129. }
  130. constexpr static unsigned reg_byte_offset(unsigned r) {
  131. constexpr std::array<const uint32_t, 73> RV32GC_reg_byte_offset{{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,280,288,296,304,312,320,328,336,344,352,360,368,376,384,392,396,400,404,408,412,416,424}};
  132. return RV32GC_reg_byte_offset[r];
  133. }
  134. static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
  135. enum sreg_flag_e {FLAGS};
  136. enum mem_type_e {MEM, CSR, FENCE, RES};
  137. };
  138. struct rv32gc: public arch_if {
  139. using virt_addr_t = typename traits<rv32gc>::virt_addr_t;
  140. using phys_addr_t = typename traits<rv32gc>::phys_addr_t;
  141. using reg_t = typename traits<rv32gc>::reg_t;
  142. using addr_t = typename traits<rv32gc>::addr_t;
  143. rv32gc();
  144. ~rv32gc();
  145. void reset(uint64_t address=0) override;
  146. uint8_t* get_regs_base_ptr() override;
  147. /// deprecated
  148. void get_reg(short idx, std::vector<uint8_t>& value) override {}
  149. void set_reg(short idx, const std::vector<uint8_t>& value) override {}
  150. /// deprecated
  151. bool get_flag(int flag) override {return false;}
  152. void set_flag(int, bool value) override {};
  153. /// deprecated
  154. void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
  155. uint64_t get_icount() { return reg.icount;}
  156. inline phys_addr_t v2p(const iss::addr_t& addr){
  157. if(addr.space != traits<rv32gc>::MEM ||
  158. addr.type == iss::address_type::PHYSICAL ||
  159. addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL){
  160. return phys_addr_t(addr.access, addr.space, addr.val&traits<rv32gc>::addr_mask);
  161. } else
  162. return virt2phys(addr);
  163. }
  164. virtual phys_addr_t virt2phys(const iss::addr_t& addr);
  165. virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
  166. inline
  167. uint32_t get_last_branch(){return reg.last_branch;}
  168. protected:
  169. struct RV32GC_regs {
  170. uint32_t X0 = 0;
  171. uint32_t X1 = 0;
  172. uint32_t X2 = 0;
  173. uint32_t X3 = 0;
  174. uint32_t X4 = 0;
  175. uint32_t X5 = 0;
  176. uint32_t X6 = 0;
  177. uint32_t X7 = 0;
  178. uint32_t X8 = 0;
  179. uint32_t X9 = 0;
  180. uint32_t X10 = 0;
  181. uint32_t X11 = 0;
  182. uint32_t X12 = 0;
  183. uint32_t X13 = 0;
  184. uint32_t X14 = 0;
  185. uint32_t X15 = 0;
  186. uint32_t X16 = 0;
  187. uint32_t X17 = 0;
  188. uint32_t X18 = 0;
  189. uint32_t X19 = 0;
  190. uint32_t X20 = 0;
  191. uint32_t X21 = 0;
  192. uint32_t X22 = 0;
  193. uint32_t X23 = 0;
  194. uint32_t X24 = 0;
  195. uint32_t X25 = 0;
  196. uint32_t X26 = 0;
  197. uint32_t X27 = 0;
  198. uint32_t X28 = 0;
  199. uint32_t X29 = 0;
  200. uint32_t X30 = 0;
  201. uint32_t X31 = 0;
  202. uint32_t PC = 0;
  203. uint64_t F0 = 0;
  204. uint64_t F1 = 0;
  205. uint64_t F2 = 0;
  206. uint64_t F3 = 0;
  207. uint64_t F4 = 0;
  208. uint64_t F5 = 0;
  209. uint64_t F6 = 0;
  210. uint64_t F7 = 0;
  211. uint64_t F8 = 0;
  212. uint64_t F9 = 0;
  213. uint64_t F10 = 0;
  214. uint64_t F11 = 0;
  215. uint64_t F12 = 0;
  216. uint64_t F13 = 0;
  217. uint64_t F14 = 0;
  218. uint64_t F15 = 0;
  219. uint64_t F16 = 0;
  220. uint64_t F17 = 0;
  221. uint64_t F18 = 0;
  222. uint64_t F19 = 0;
  223. uint64_t F20 = 0;
  224. uint64_t F21 = 0;
  225. uint64_t F22 = 0;
  226. uint64_t F23 = 0;
  227. uint64_t F24 = 0;
  228. uint64_t F25 = 0;
  229. uint64_t F26 = 0;
  230. uint64_t F27 = 0;
  231. uint64_t F28 = 0;
  232. uint64_t F29 = 0;
  233. uint64_t F30 = 0;
  234. uint64_t F31 = 0;
  235. uint32_t FCSR = 0;
  236. uint32_t NEXT_PC = 0;
  237. uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
  238. uint64_t icount = 0;
  239. } reg;
  240. std::array<address_type, 4> addr_mode;
  241. uint32_t get_fcsr(){return reg.FCSR;}
  242. void set_fcsr(uint32_t val){reg.FCSR = val;}
  243. };
  244. }
  245. }
  246. #endif /* _RV32GC_H_ */