Generic RISC-V ISS
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  1. ////////////////////////////////////////////////////////////////////////////////
  2. // Copyright (C) 2017, MINRES Technologies GmbH
  3. // All rights reserved.
  4. //
  5. // Redistribution and use in source and binary forms, with or without
  6. // modification, are permitted provided that the following conditions are met:
  7. //
  8. // 1. Redistributions of source code must retain the above copyright notice,
  9. // this list of conditions and the following disclaimer.
  10. //
  11. // 2. Redistributions in binary form must reproduce the above copyright notice,
  12. // this list of conditions and the following disclaimer in the documentation
  13. // and/or other materials provided with the distribution.
  14. //
  15. // 3. Neither the name of the copyright holder nor the names of its contributors
  16. // may be used to endorse or promote products derived from this software
  17. // without specific prior written permission.
  18. //
  19. // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20. // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21. // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22. // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23. // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24. // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25. // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26. // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27. // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28. // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29. // POSSIBILITY OF SUCH DAMAGE.
  30. //
  31. ////////////////////////////////////////////////////////////////////////////////
  32. <%
  33. import com.minres.coredsl.coreDsl.Register
  34. import com.minres.coredsl.coreDsl.RegisterFile
  35. def getTypeSize(size){
  36. if(size > 32) 64 else if(size > 16) 32 else if(size > 8) 16 else 8
  37. }
  38. %>
  39. #ifndef _${coreDef.name.toUpperCase()}_H_
  40. #define _${coreDef.name.toUpperCase()}_H_
  41. #include <iss/arch_if.h>
  42. #include <iss/vm_if.h>
  43. #include <iss/arch/traits.h>
  44. #include <array>
  45. namespace iss {
  46. namespace arch {
  47. struct ${coreDef.name.toLowerCase()};
  48. template<>
  49. struct traits<${coreDef.name.toLowerCase()}> {
  50. constexpr static char const* const core_type = "${coreDef.name}";
  51. enum constants {${coreDef.constants.collect{c -> c.name+"="+c.value}.join(', ')}};
  52. constexpr static unsigned FP_REGS_SIZE = ${coreDef.constants.find {it.name=='FLEN'}?.value?:0};
  53. enum reg_e {<%
  54. allRegs.each { reg ->
  55. if( reg instanceof RegisterFile) {
  56. (reg.range.right..reg.range.left).each{%>
  57. ${reg.name}${it},<%
  58. }
  59. } else if(reg instanceof Register){ %>
  60. ${reg.name},<%
  61. }
  62. }%>
  63. NUM_REGS,
  64. NEXT_${pc.name}=NUM_REGS,
  65. TRAP_STATE,
  66. PENDING_TRAP,
  67. MACHINE_STATE,
  68. LAST_BRANCH,
  69. ICOUNT
  70. };
  71. using reg_t = uint${regDataWidth}_t;
  72. using addr_t = uint${addrDataWidth}_t;
  73. using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
  74. using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
  75. using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
  76. constexpr static unsigned reg_bit_width(unsigned r) {
  77. constexpr std::array<const uint32_t, ${regSizes.size}> ${coreDef.name}_reg_size{{${regSizes.join(",")}}};
  78. return ${coreDef.name}_reg_size[r];
  79. }
  80. constexpr static unsigned reg_byte_offset(unsigned r) {
  81. constexpr std::array<const uint32_t, ${regOffsets.size}> ${coreDef.name}_reg_byte_offset{{${regOffsets.join(",")}}};
  82. return ${coreDef.name}_reg_byte_offset[r];
  83. }
  84. static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
  85. enum sreg_flag_e {FLAGS};
  86. enum mem_type_e {${allSpaces.collect{s -> s.name}.join(', ')}};
  87. };
  88. struct ${coreDef.name.toLowerCase()}: public arch_if {
  89. using virt_addr_t = typename traits<${coreDef.name.toLowerCase()}>::virt_addr_t;
  90. using phys_addr_t = typename traits<${coreDef.name.toLowerCase()}>::phys_addr_t;
  91. using reg_t = typename traits<${coreDef.name.toLowerCase()}>::reg_t;
  92. using addr_t = typename traits<${coreDef.name.toLowerCase()}>::addr_t;
  93. ${coreDef.name.toLowerCase()}();
  94. ~${coreDef.name.toLowerCase()}();
  95. void reset(uint64_t address=0) override;
  96. uint8_t* get_regs_base_ptr() override;
  97. /// deprecated
  98. void get_reg(short idx, std::vector<uint8_t>& value) override {}
  99. void set_reg(short idx, const std::vector<uint8_t>& value) override {}
  100. /// deprecated
  101. bool get_flag(int flag) override {return false;}
  102. void set_flag(int, bool value) override {};
  103. /// deprecated
  104. void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
  105. uint64_t get_icount() { return reg.icount;}
  106. inline phys_addr_t v2p(const iss::addr_t& addr){
  107. if(addr.space != traits<${coreDef.name.toLowerCase()}>::MEM ||
  108. addr.type == iss::address_type::PHYSICAL ||
  109. addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL){
  110. return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
  111. } else
  112. return virt2phys(addr);
  113. }
  114. virtual phys_addr_t virt2phys(const iss::addr_t& addr);
  115. virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
  116. inline
  117. uint32_t get_last_branch(){return reg.last_branch;}
  118. protected:
  119. struct ${coreDef.name}_regs {<%
  120. allRegs.each { reg ->
  121. if( reg instanceof RegisterFile) {
  122. (reg.range.right..reg.range.left).each{%>
  123. uint${generator.getSize(reg)}_t ${reg.name}${it} = 0;<%
  124. }
  125. } else if(reg instanceof Register){ %>
  126. uint${generator.getSize(reg)}_t ${reg.name} = 0;<%
  127. }
  128. }%>
  129. uint${generator.getSize(pc)}_t NEXT_${pc.name} = 0;
  130. uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
  131. uint64_t icount = 0;
  132. } reg;
  133. std::array<address_type, 4> addr_mode;
  134. <%
  135. def fcsr = allRegs.find {it.name=='FCSR'}
  136. if(fcsr != null) {%>
  137. uint${generator.getSize(fcsr)}_t get_fcsr(){return reg.FCSR;}
  138. void set_fcsr(uint${generator.getSize(fcsr)}_t val){reg.FCSR = val;}
  139. <%} else { %>
  140. uint32_t get_fcsr(){return 0;}
  141. void set_fcsr(uint32_t val){}
  142. <%}%>
  143. };
  144. }
  145. }
  146. #endif /* _${coreDef.name.toUpperCase()}_H_ */