RISC-V instruction set architecture description in CoreDSL
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Eyck Jentzsch b005607fc3 add debug mode state register and DRET instruction description 2 months ago
README.md update README 11 months ago
RISCVBase.core_desc add debug mode state register and DRET instruction description 2 months ago
RV32I.core_desc add debug mode state register and DRET instruction description 2 months ago
RV64I.core_desc adapt to fixed bitfield description 11 months ago
RVA.core_desc adapt to fixed bitfield description 11 months ago
RVC.core_desc add instruction alignment setting 4 months ago
RVD.core_desc adapt to fixed bitfield description 11 months ago
RVF.core_desc adapt to fixed bitfield description 11 months ago
RVM.core_desc fix RVM description bugs 10 months ago

README.md

CoreDSL-Instruction-Set-Description of RISC-V

Instruction set description of the RISC-V standard extensions in CoreDSL2